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KR100548723B1 - Method of measuring film thickness of semiconductor wafer having pattern for measuring film thickness and wafer using same - Google Patents

Method of measuring film thickness of semiconductor wafer having pattern for measuring film thickness and wafer using same Download PDF

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KR100548723B1
KR100548723B1 KR1020030101338A KR20030101338A KR100548723B1 KR 100548723 B1 KR100548723 B1 KR 100548723B1 KR 1020030101338 A KR1020030101338 A KR 1020030101338A KR 20030101338 A KR20030101338 A KR 20030101338A KR 100548723 B1 KR100548723 B1 KR 100548723B1
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pattern
film thickness
wafer
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이진규
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동부아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

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Abstract

본 발명은 반도체 웨이퍼에 대하여 화학기계적 연마(Chemical Mechanical Polishing: CMP) 공정(이하, "CMP 공정"이라고 함)을 수행할 때, 웨이퍼에 형성된 막 두께를 측정함에 있어서, 해당 막 내에 형성된 패턴 밀도를 반영하여 막의 두께를 측정할 수 있도록 하는 막 두께 측정용 패턴이 형성된 반도체 웨이퍼 및 이러한 패턴을 이용한 웨이퍼의 막 두께 측정방법에 관한 것이다. In the present invention, when performing a chemical mechanical polishing (CMP) process (hereinafter, referred to as a "CMP process") on a semiconductor wafer, the pattern density formed in the film is measured by measuring the film thickness formed on the wafer. The present invention relates to a semiconductor wafer on which a film thickness measurement pattern is formed to reflect and measure the film thickness, and to a method for measuring the film thickness of a wafer using such a pattern.

본 발명에서는, 다층의 박막층이 형성된 반도체 웨이퍼의 각 박막층을 연마공정할 때, 각 박막층의 두께를 측정하는 위치가 되는 막 두께 측정용 패턴(10)이 형성된 반도체 웨이퍼로서, 상기 막 두께 측정용 패턴(10)은, 웨이퍼의 각 박막층이 가지는 패턴의 밀도에 대응되는 패턴 밀도를 가지도록 형성된 복수 종류의 측정 패턴으로 이루어지며; 상기 막 두께 측정용 패턴(10)은, 반도체 웨이퍼의 다이 사이에 존재하는 스크라이브 라인 상에 형성되는 것을 특징으로 하는 반도체 웨이퍼 및 이러한 패턴을 이용한 웨이퍼의 막 두께 측정방법이 제공된다. In the present invention, when the thin film layer of the semiconductor wafer on which the multilayer thin film layer is formed is polished, the semiconductor wafer is provided with a film thickness measurement pattern 10 which becomes a position for measuring the thickness of each thin film layer. (10) is composed of a plurality of types of measurement patterns formed to have a pattern density corresponding to the density of the pattern of each thin film layer of the wafer; The film thickness measuring pattern 10 is provided on a scribe line existing between dies of a semiconductor wafer, and a method for measuring film thickness of a wafer using such a pattern is provided.

웨이퍼, 막두께, 연마, 측정, 스크라이브 라인 Wafer, Film Thickness, Polishing, Measurement, Scribe Line

Description

막 두께 측정용 패턴이 형성된 반도체 웨이퍼 및 이를 이용한 웨이퍼의 막 두께 측정방법{Semiconductor Wafer having Patterns for Monitoring Thickness of Layer and Method for Monitoring Thickness of Layer using such Patterns} Semiconductor Wafer Having Patterns for Monitoring Thickness of Layer and Method for Monitoring Thickness of Layer using such Patterns}             

도 1은 STI CMP 공정에서 적용할 수 있는 본 발명에 따른 막 두께 측정용 패턴의 일예를 도시한 평면도이다. 1 is a plan view showing an example of a film thickness measurement pattern according to the present invention that can be applied in the STI CMP process.

도 2는 웨이퍼의 스크라이브 라인 상에 본 발명에 따른 막 두께 측정용 패턴의 일실시예가 형성되어 있는 것을 도시한 개략도이다. 2 is a schematic diagram showing an embodiment of a film thickness measurement pattern according to the present invention formed on a scribe line of a wafer.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

10 막 두께 측정용 패턴 30 웨이퍼10 Pattern for film thickness measurement 30 Wafer

31 다이 32 스크라이브 라인31 die 32 scribe lines

본 발명은 막 두께 측정용 패턴이 형성된 반도체 웨이퍼, 및 이를 이용한 웨이퍼의 막 두께 측정방법에 관한 것으로서, 구체적으로는 반도체 웨이퍼에 대하여 화학기계적 연마(Chemical Mechanical Polishing: CMP) 공정(이하, "CMP 공정"이라고 함)을 수행할 때, 웨이퍼에 형성된 막 두께를 측정함에 있어서, 해당 막 내에 형성된 패턴 밀도를 반영하여 막의 두께를 측정할 수 있도록 하는 막 두께 측정용 패턴이 형성된 반도체 웨이퍼 및 이러한 패턴을 이용한 웨이퍼의 막 두께 측정방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer having a film thickness measurement pattern, and a method for measuring a film thickness of the wafer using the same, specifically, a chemical mechanical polishing (CMP) process (hereinafter, referred to as a "CMP process") for a semiconductor wafer. In the measurement of the film thickness formed on the wafer, the semiconductor wafer on which the film thickness measurement pattern is formed to reflect the pattern density formed in the film so that the film thickness can be measured and using the pattern A method for measuring a film thickness of a wafer.

다층의 박막층이 형성된 웨이퍼의 제작과정에서 CMP 공정을 행함에 있어서는 연마할 각 층의 막 두께를 정확히 측정하는 것이 중요하다. 특히, 연마공정에 있어서는 해당 층에 형성된 패턴의 밀도를 고려하는 것이 중요한데, 예를 들어 패턴의 밀도가 높은 경우에는 연마의 정도를 높여야 하고, 패턴의 밀도가 낮은 경우에는 연마의 정도를 낮추어야 한다. 그럼에도 불구하고, 종래에는, 막 두께를 측정함에 있어서, 이러한 패턴의 밀도가 전혀 고려되지 아니하였다. In performing the CMP process in the manufacturing process of the wafer on which the multilayer thin film layer is formed, it is important to accurately measure the film thickness of each layer to be polished. In particular, in the polishing process, it is important to consider the density of the pattern formed on the layer. For example, when the pattern density is high, the degree of polishing should be increased, and when the pattern density is low, the degree of polishing should be reduced. Nevertheless, conventionally, in measuring the film thickness, the density of such a pattern was not considered at all.

구체적으로, STI CMP 공정에서는 모우트 패턴 밀도(Moat Pattern Density)가, 그리고 PMD(Pre-Metal Dielectric) CMP 공정에서는 게이트 폴리 패턴 밀도(Gate Poly Pattern Density)가 중요한 인자로 작용하며, IMD(Inter-Metal Dielectric) CMP 공정에서는 금속 패턴 밀도(Metal Pattern Density)가 중요한 인자로 작용하는 등, 각 단계의 CMP 공정에서는 패턴의 밀도가 중요한 것임에도 불구하고, 종래의 막 두께 측정방법에서는 이러한 패턴의 밀도를 전혀 고려하지 아니하였던 것이다. 그 결과로, 높은 패턴 밀도를 가지는 영역임에도 불구하고 낮은 패턴 밀도를 가지는 영역에 대하여 막 두께를 측정함으로써, 결과적으로 패턴 밀도가 높은 영역에 대하여 저 연마(Under Polish)가 이루어지는 경우가 발생한다. 또한, 낮은 패턴 밀도를 가지는 영역임에도 불구하고 높은 패턴 밀도를 가지는 영역에 대하여 막 두께를 측정함으로써 실제로는 낮은 패턴 밀도를 가지는 영역에 대하여 과도 연마(Over Polish)가 행해지는 경우가 발생하게 된다. 이러한 부적절한 연마는 결국 웨이퍼 불량의 원인이 된다. Specifically, in the STI CMP process, Moat Pattern Density, and in the PMD (Pre-Metal Dielectric) CMP process, Gate Poly Pattern Density is an important factor, and IMD (Inter- Metal Dielectric) Although the density of patterns is important in the CMP process at each step, such as metal pattern density, which is an important factor in the CMP process, the conventional film thickness measurement method uses the density of such patterns. It was not considered at all. As a result, by measuring the film thickness for a region having a low pattern density even though it is a region having a high pattern density, as a result, under polishing occurs for a region having a high pattern density. In addition, by measuring the film thickness of a region having a high pattern density even though it is a region having a low pattern density, in practice, over polishing is performed on a region having a low pattern density. This improper polishing eventually leads to wafer failure.

특히, 막 두께의 측정 지점 역시 측정자의 개인적인 경험이 차이, 측정시의 패턴의 상태, 시간의 긴급성, 패턴의 모양에 따라 변동되었는바, 그에 따라 정확한 막 두께 측정이 이루어지지 아니하였다. In particular, the measurement point of the film thickness also varied depending on the individual experience of the measurer, the state of the pattern at the time of measurement, the urgency of the time, the shape of the pattern, and thus the accurate film thickness measurement was not made.

본 발명은 위와 같은 종래 기술의 문제점을 해결하기 위하여 제안된 것으로서, CMP 공정에서 웨이퍼의 연마되는 각 층의 막 두께를 측정함에 있어서, 연마하고자 하는 해당 층의 패턴 밀도에 따라, 그에 적합한 위치에서 막 두께를 측정할 수 있도록 하므로써, 적절한 연마공정이 이루어지도록 하는 것을 목적으로 한다.
The present invention has been proposed to solve the above problems of the prior art, in measuring the film thickness of each layer of the wafer polished in the CMP process, according to the pattern density of the layer to be polished, the film at a suitable position The object of the present invention is to enable an appropriate polishing process by allowing the thickness to be measured.

본 발명에서는 상기와 같은 목적을 달성하기 위하여, 다층의 박막층이 형성된 반도체 웨이퍼의 각 박막층을 연마공정할 때, 각 박막층의 두께를 측정하는 위치가 되는 막 두께 측정용 패턴이 형성된 반도체 웨이퍼로서, 상기 막 두께 측정용 패턴은, 웨이퍼의 각 박막층이 가지는 패턴의 밀도에 대응되는 패턴 밀도를 가지도록 형성된 복수 종류의 측정 패턴으로 이루어지며; 상기 막 두께 측정용 패턴은, 반도체 웨이퍼의 다이 사이에 존재하는 스크라이브 라인 상에 형성되는 것을 특징으로 하는 반도체 웨이퍼가 제공된다. In the present invention, in order to achieve the above object, when polishing a thin film layer of a semiconductor wafer having a multi-layered thin film layer, the semiconductor wafer is formed with a film thickness measurement pattern which is a position for measuring the thickness of each thin film layer, The film thickness measurement pattern is composed of a plurality of types of measurement patterns formed to have a pattern density corresponding to the density of the pattern of each thin film layer of the wafer; The film thickness measuring pattern is provided on a scribe line existing between dies of a semiconductor wafer.

본 발명에서는 구체적인 실시예로서, 상기 막 두께 측정용 패턴(10)이, 복수 종류의 패턴 밀도를 가지는 각각의 측정 패턴이 패턴 밀도 값의 크기 순서에 따라 순차적으로 배열되어 형성되는 것을 특징으로 하는 반도체 웨이퍼가 제공된다. In the present invention, as a specific embodiment, the film thickness measurement pattern 10 is a semiconductor, characterized in that each measurement pattern having a plurality of types of pattern density are formed in order in order of the order of the pattern density value A wafer is provided.

또한, 본 발명에서는, 다층의 박막층이 형성된 반도체 웨이퍼의 각 박막층을 연마공정할 때, 각 박막층의 두께를 측정하는 방법으로서, 웨이퍼의 각 박막층이 가지는 패턴의 밀도에 대응되는 패턴 밀도를 가지도록 형성된 복수 종류의 측정 패턴으로 이루어진 상기 막 두께 측정용 패턴을, 반도체 웨이퍼의 다이 사이에 존재하는 스크라이브 라인 상에 형성하고; 상기 막 두께 측정용 패턴을 이루는 측정 패턴 중에서, 해당 연마공정이 이루어진 박막층의 패턴 밀도에 해당하는 패턴 밀도를 가지는 측정 패턴을 막 두께 측정 위치로 하여 박막층의 두께를 측정하는 것을 특징으로 하는 반도체 웨이퍼의 막 두께 측정방법이 제공된다. In the present invention, when the thin film layer of the semiconductor wafer having a multi-layered thin film layer is polished, the thickness of each thin film layer is measured to have a pattern density corresponding to the pattern density of each thin film layer of the wafer. Forming the film thickness measurement pattern comprising a plurality of types of measurement patterns on a scribe line existing between dies of the semiconductor wafer; Among the measurement patterns constituting the film thickness measurement pattern, the thickness of the thin film layer is measured using a measurement pattern having a pattern density corresponding to the pattern density of the thin film layer subjected to the polishing step as the film thickness measurement position. A film thickness measurement method is provided.

상기한 본 발명에 따른 반도체 웨이퍼의 막 두께 측정 방법에서, 상기 막 두께 측정용 패턴을 형성할 때, 복수 종류의 패턴 밀도를 가지는 각각의 측정 패턴을 패턴 밀도 값의 크기 순서에 따라 순차적으로 배열하여 막 두께 측정용 패턴을 형성할 수도 있다. In the above-described method for measuring the thickness of a semiconductor wafer according to the present invention, when forming the film thickness measurement pattern, each measurement pattern having a plurality of types of pattern densities is sequentially arranged in the order of the size of the pattern density values. The pattern for film thickness measurement can also be formed.

다음에서는 첨부도면을 참고하여 본 발명의 구체적인 실시예들을 살펴봄으로써 본 발명의 구성에 대하여 설명한다. Next, the configuration of the present invention will be described by referring to specific embodiments of the present invention with reference to the accompanying drawings.

본 발명에서는, 반도체 웨이퍼의 다이(die) 사이에 형성되는 스크라이브 라인(scribe line) 상에, 다층으로 형성된 웨이퍼 상의 각 박막층이 가지는 패턴의 밀도에 대응되는 패턴 밀도를 가지는 복수 종류의 두께 측정 패턴으로 이루어진 막 두께 측정용 패턴이 형성된다. In the present invention, a plurality of thickness measurement patterns having a pattern density corresponding to the density of the pattern of each thin film layer on the wafer formed in multiple layers on a scribe line formed between dies of the semiconductor wafer. The formed film thickness measurement pattern is formed.

도 1에는 STI CMP 공정에서 적용할 수 있는 본 발명에 따른 막 두께 측정용 패턴(1)의 일예가 평면도로 도시되어 있다. Figure 1 shows an example of a film thickness measurement pattern 1 according to the present invention that can be applied in the STI CMP process in a plan view.

상기 막 두께 측정용 패턴(1)은, 웨이퍼에 형성된 패턴이 가질 수 있는 여러 패턴 밀도 값에 대응하는 패턴 밀도를 갖게 되는 여러 형태의 패턴으로 이루어진다. 요컨대, 웨이퍼에 형성된 각 박막층의 패턴이 가질 수 있는 패턴의 밀도값을 P1, P2, P3, P4 라고 하였을 때, 상기 막 두께 측정용 패턴(1)은, 각 박막층의 패턴 밀도에 대응하는 패턴 밀도 값을 갖도록 형성된 제1 측정 패턴(11), 제2 측정 패턴(12), 제3 측정 패턴(13) 및 제4 측정 패턴(14)으로 구성되는 것이다. 여기서 제1 측정 패턴(11)의 패턴 밀도 값은 P1이고, 제2 측정 패턴(12)의 패턴 밀도 값은 P2이며, 제2 측정 패턴(13)의 패턴 밀도 값은 P3이고, 제4 측정 패턴(14)의 패턴 밀도 값은 P4이다. The film thickness measurement pattern 1 is formed of various types of patterns having a pattern density corresponding to various pattern density values that the pattern formed on the wafer may have. In other words, when the density value of the pattern of the pattern of each thin film layer formed on the wafer is P1, P2, P3, P4, the film thickness measurement pattern 1 corresponds to the pattern density of each thin film layer. The first measurement pattern 11, the second measurement pattern 12, the third measurement pattern 13, and the fourth measurement pattern 14 are formed to have a value. Here, the pattern density value of the first measurement pattern 11 is P1, the pattern density value of the second measurement pattern 12 is P2, the pattern density value of the second measurement pattern 13 is P3, and the fourth measurement pattern The pattern density value of (14) is P4.

도 1에 도시된 실시예는 STI CMP 공정에서 적용할 수 있는 막 두께 측정용 패턴(1)에 대한 것으로서, 동일한 면적에 대하여 300um 피치의 패턴과, 100um 피치의 패턴, 그리고 50um 피치의 패턴과 30um 피치의 패턴이 배열되므로써 각각 제1 측정 패턴(11), 제2 측정 패턴(12), 제3 측정 패턴(13) 및 제4 측정 패턴(14)을 이루고 있다. 여기서 각 패턴의 중앙에 사각형으로 표시된 부분은 두께 측정점(20) 을 나타낸다. The embodiment shown in FIG. 1 relates to the film thickness measurement pattern 1 applicable to the STI CMP process, and has a pattern of 300 um pitch, pattern of 100 um pitch, pattern of 50 um pitch, and 30 um for the same area. The pitch patterns are arranged to form the first measurement pattern 11, the second measurement pattern 12, the third measurement pattern 13, and the fourth measurement pattern 14, respectively. Here, the portion indicated by the square at the center of each pattern represents the thickness measurement point 20.

본 발명에서는 위와 같이, 웨이퍼에 형성된 각 박막층의 패턴이 가질 수 있는 패턴의 밀도값(P1, P2, P3, P4)을 갖는 측정 패턴(11, 12, 13, 14)으로 이루어진 막 두께 측정용 패턴(10)이, 웨이퍼의 다이와 다이 사이에 존재하는 스크라이브 라인 상에 형성된다. In the present invention, as described above, the film thickness measurement pattern consisting of the measurement pattern (11, 12, 13, 14) having a density value (P1, P2, P3, P4) of the pattern of each thin film layer formed on the wafer 10 is formed on a scribe line existing between the die and the die of the wafer.

도 2에는 웨이퍼의 스크라이브 라인 상에 본 발명에 따른 막 두께 측정용 패턴(10)의 일실시예가 형성되어 있는 것이 개략적으로 도시되어 있는데, 도면에 도시된 것처럼, 웨이퍼(30)의 다이(31)와 다이(31) 사이에 존재하는 스크라이브 라인(32) 내에, 각 박막층의 패턴 밀도에 대응되는 패턴의 밀도값(P1, P2, P3, P4)을 갖는 측정 패턴(11, 12, 13, 14)이 서로 연이어서 순차적으로 배열되어 구성되는 막 두께 측정용 패턴(10)이 형성되는 것이다. 여기서, 여러 패턴 밀도값을 갖는 측정 패턴(11, 12, 13, 14)을 배치함에 있어서, 도면에 도시된 것처럼 이들 측정 패턴을 각 패턴 밀도의 크기에 따라서 순차적으로 배열하고, 이를 반복하여 배열할 수도 있다. 그러나 각 패턴 밀도를 배열하는 순서는 반드시 이에 한정되지 아니한다. 2 schematically shows that an embodiment of the film thickness measurement pattern 10 according to the present invention is formed on a scribe line of a wafer. As shown in the drawing, the die 31 of the wafer 30 is shown. And measurement patterns 11, 12, 13, 14 having density values P1, P2, P3, and P4 of patterns corresponding to the pattern densities of the respective thin film layers in the scribe lines 32 existing between the die 31 and the die 31. The film thickness measurement pattern 10 is formed by successively arranged next to each other. Here, in arranging the measurement patterns 11, 12, 13, and 14 having various pattern density values, these measurement patterns are sequentially arranged according to the size of each pattern density, as shown in the drawing, and then repeatedly arranged. It may be. However, the order of arranging each pattern density is not necessarily limited thereto.

이와 같이, 웨이퍼의 스크라이브 라인 상에 본 발명에 따른 막 두께 측정용 패턴(10)을 형성한 후, 각 박막층에 대하여 CMP공정을 수행할 때, 해당 박막층의 패턴 밀도에 대응되는 막 두께 측정용 패턴(10) 내의 측정 패턴에서 막 두께를 측정한다. 즉, 해당 박막층의 패턴 밀도가 반영되어 있는 측정 패턴에 대하여 막 두께를 측정하게 되는 것이다. Thus, after forming the film thickness measurement pattern 10 according to the present invention on the scribe line of the wafer, when performing the CMP process for each thin film layer, the film thickness measurement pattern corresponding to the pattern density of the thin film layer The film thickness is measured in the measurement pattern in (10). That is, the film thickness is measured with respect to the measurement pattern in which the pattern density of the thin film layer is reflected.

따라서, 해당 박막층의 패턴 밀도를 고려한 막 두께를 측정할 수 있게 되며, 그에 따라, 과도한 연마 또는 부족한 연마 현상이 발생하는 것을 방지할 수 있게 된다. Therefore, it is possible to measure the film thickness in consideration of the pattern density of the thin film layer, thereby preventing excessive polishing or insufficient polishing phenomenon from occurring.

위에서 설명한 바와 같이, 본 발명에 따르면 해당 박막층의 패턴 밀도를 고려한 막 두께를 측정할 수 있게 되며, 그에 따라, 과도한 연마 또는 부족한 연마 현상이 발생하는 것을 방지할 수 있게 된다는 효과이외에도 다음과 같은 장점이 있다. As described above, according to the present invention, it is possible to measure the film thickness in consideration of the pattern density of the thin film layer, and accordingly, besides the effect of being able to prevent excessive polishing or insufficient polishing, the following advantages are obtained. have.

종래에는 작업자가 임의의 위치에서 막 두께를 측정하였으며, 장비에 따라서도 막 두께 측정위치가 상이하였으나, 위와 같이 막 두께 측정용 패턴을 형성하여 두고, 각 박막층에 해당하는 패턴 밀도를 가진 측정 패턴에서 두께를 측정하게 되면, 작업자간, 그리고 장비간의 막 두께 위치선정에 있어서 통일성을 기할 수 있으며, 그에 따라 공정의 표준화 및 공정상의 오류 발생을 최소화할 수 있게 된다. In the related art, the operator measured the film thickness at an arbitrary position, and the film thickness measurement position was different depending on the equipment. However, as described above, the film thickness measurement pattern was formed, and in the measurement pattern having the pattern density corresponding to each thin film layer By measuring the thickness, uniformity can be achieved in the positioning of the film thickness between workers and equipment, thereby minimizing process standardization and process errors.

Claims (4)

다층의 박막층이 형성된 반도체 웨이퍼의 각 박막층을 연마공정할 때, 각 박막층의 두께를 측정하는 위치가 되는 막 두께 측정용 패턴(10)이 형성된 반도체 웨이퍼로서, A semiconductor wafer in which the film thickness measurement pattern 10, which becomes a position for measuring the thickness of each thin film layer, is formed when polishing a thin film layer of a semiconductor wafer on which a multilayer thin film layer is formed, 상기 막 두께 측정용 패턴(10)은, 웨이퍼의 각 박막층이 가지는 패턴의 밀도에 대응되는 패턴 밀도를 가지도록 형성된 복수 종류의 측정 패턴으로 이루어지며; The film thickness measurement pattern 10 includes a plurality of types of measurement patterns formed to have a pattern density corresponding to the density of the pattern of each thin film layer of the wafer; 상기 막 두께 측정용 패턴(10)은, 반도체 웨이퍼의 다이 사이에 존재하는 스크라이브 라인 상에 형성되는 것을 특징으로 하는 반도체 웨이퍼. The film thickness measurement pattern (10) is a semiconductor wafer, characterized in that formed on the scribe line existing between the die of the semiconductor wafer. 제1항에 있어서, The method of claim 1, 상기 막 두께 측정용 패턴(10)은, The film thickness measurement pattern 10, 복수 종류의 패턴 밀도를 가지는 각각의 측정 패턴이 패턴 밀도값의 크기 순서에 따라 순차적으로 배열되어 형성되는 것을 특징으로 하는 반도체 웨이퍼. A semiconductor wafer, characterized in that each measurement pattern having a plurality of types of pattern densities is sequentially arranged in accordance with the magnitude order of the pattern density values. 다층의 박막층이 형성된 반도체 웨이퍼의 각 박막층을 연마공정할 때, 각 박막층의 두께를 측정하는 방법으로서, As a method of measuring the thickness of each thin film layer when polishing a thin film layer of a semiconductor wafer having a multilayer thin film layer, 웨이퍼의 각 박막층이 가지는 패턴의 밀도에 대응되는 패턴 밀도를 가지도록 형성된 복수 종류의 측정 패턴으로 이루어진 상기 막 두께 측정용 패턴(10)을, 반도체 웨이퍼의 다이 사이에 존재하는 스크라이브 라인 상에 형성하고; The film thickness measurement pattern 10 formed of a plurality of types of measurement patterns formed to have a pattern density corresponding to the pattern density of each thin film layer of the wafer is formed on a scribe line existing between dies of the semiconductor wafer, ; 상기 막 두께 측정용 패턴(10)을 이루는 측정 패턴 중에서, 해당 연마공정이 이루어진 박막층의 패턴 밀도에 해당하는 패턴 밀도를 가지는 측정 패턴을 막 두께 측정 위치로 하여 박막층의 두께를 측정하는 것을 특징으로 하는 반도체 웨이퍼의 막 두께 측정방법. Among the measurement patterns constituting the film thickness measurement pattern 10, the thickness of the thin film layer is measured by using a measurement pattern having a pattern density corresponding to the pattern density of the thin film layer subjected to the polishing process as the film thickness measurement position. Method for measuring film thickness of semiconductor wafers. 제3항에 있어서, The method of claim 3, 상기 막 두께 측정용 패턴(10)을 형성함에 있어서, In forming the film thickness measurement pattern 10, 복수 종류의 패턴 밀도를 가지는 각각의 측정 패턴을 패턴 밀도값의 크기 순서에 따라 순차적으로 배열하여 막 두께 측정용 패턴(10)을 형성하는 것을 특징으로 하는 반도체 웨이퍼의 막 두께 측정방법.A method for measuring a film thickness of a semiconductor wafer, characterized by forming a film thickness measurement pattern (10) by sequentially arranging each measurement pattern having a plurality of types of pattern densities according to the order of the pattern density values.
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