KR100568595B1 - Electro-luminescence display - Google Patents

Abstract

The present invention relates to an electro-luminescence display device capable of ensuring a high aperture ratio.

In an exemplary embodiment, an electro-luminescence display device includes: electroluminescence cells disposed at intersections of gate lines and data lines, and the electroluminescence cells connected to each of the electroluminescence cells. A plurality of cell driving circuits controlling current supplied to each of the plurality of cell driving circuits, which are shared by the cell driving circuits vertically neighboring, and selectively transmitting the video signal from each of the data lines to the vertically neighboring cell driving circuits. It is characterized by having a plurality of control circuits for supplying.

Description

Electro-Luminescence Display Apparatus}             

1 is a cross-sectional view showing an organic light emitting cell of a general electroluminescent display panel.

2 shows a conventional electro-luminescence display.

FIG. 3 is an equivalent circuit diagram of the pixel cells PE shown in FIG. 2.

4 is a diagram illustrating a gate signal supplied to gate lines shown in FIG. 2.

5 is a schematic view of an electroluminescent display device according to a first embodiment of the present invention.

FIG. 6 is a waveform diagram illustrating a driving waveform for driving the pixel cells shown in FIG. 5.

FIG. 7 is a circuit diagram equivalently showing pixel cells PE shown in FIG. 5.

8 is a schematic view of an electroluminescent display device according to a second embodiment of the present invention.

FIG. 9 is a waveform diagram illustrating driving waveforms for driving the pixel cells shown in FIG. 8; FIG.

FIG. 10 is an equivalent circuit diagram of pixel cells PE illustrated in FIG. 8.

11 is an equivalent circuit diagram illustrating pixel cells PE according to a third exemplary embodiment of the present invention.

FIG. 12 is a waveform diagram illustrating a driving waveform for driving the pixel cells shown in FIG. 11.

FIG. 13 is an equivalent circuit diagram of pixel cells PE according to a fourth exemplary embodiment of the present invention.

14 is an equivalent circuit diagram illustrating pixel cells PE according to a fifth exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

2: cathode 4: electron injection layer

6: electron transport layer 8: light emitting layer

10 hole transport layer 12 hole injection layer

14: anode 16, 40: display panel

18,118,218: first gate driver 19,119,219: second gate driver

20,120,220: Data driver 22,122,222,322: Pixel cell

50,150,250,350: Cell driving circuit 124,224,324: Control circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electroluminescent display device, and more particularly to an electroluminescent display device capable of ensuring a high aperture ratio.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include a liquid crystal display, a field emission display, a plasma display panel, and an electro-luminescence (hereinafter, referred to as "EL"). Display).

Here, the EL display device is a self-luminous device that emits a fluorescent material by recombination of electrons and holes, and is roughly divided into inorganic EL and organic EL according to materials and structures. This EL display device has the advantage of having a fast response speed, such as a cathode ray tube, compared to a passive light emitting device that requires a separate light source like a liquid crystal display device.

1 is a cross-sectional view showing a general organic EL structure for explaining the light emission principle of an EL display device. Among the EL display devices, the organic EL includes an electron injection layer 4, an electron transport layer 6, a light emitting layer 8, a hole transport layer 10, and a hole injection layer 12 stacked between the cathode 2 and the anode 14. It is provided.

When a voltage is applied between the anode 14, which is a transparent electrode, and the cathode 2, which is a metal electrode, electrons generated from the cathode 2 are directed toward the light emitting layer 8 through the electron injection layer 4 and the electron transport layer 6. Move. In addition, holes generated from the anode 14 move toward the light emitting layer 8 through the hole injection layer 12 and the hole transport layer 10. Accordingly, in the light emitting layer 8, light is generated by collision between electrons and holes supplied from the electron transport layer 6 and the hole transport layer 10 and recombination, and the light is externally transmitted through the anode 14 which is a transparent electrode. Is emitted so that the image is displayed.

2 is a diagram showing a conventional Active Matrix Type EL display device.

Referring to FIG. 2, a conventional EL display device includes an EL cell including pixel cells 22 (hereinafter referred to as “PE”) arranged at each intersection of two gate lines GL and data lines DL. The display panel 16 includes first and second gate drivers 18 and 19 for driving the gate lines GL, and a data driver 20 for driving the data lines DL.

The first gate driver 18 sequentially supplies the first scan pulses to the odd-numbered gate lines GL1, GL3,... The second gate driver 19 sequentially supplies the second scan pulses to the even-numbered gate electrode lines GL2, GL4,... Here, the first scan pulse and the second scan pulse are set to have the same width (for example, 1H) and are supplied to overlap for a predetermined period.

The data driver 20 supplies a video signal corresponding to the data to the PE cell 22 through the data lines DL. In this case, the data driver 20 supplies one horizontal line of video signals to the data lines DL every one horizontal period in which the first and second scan pulses are supplied.

The PE cells 22 display an image corresponding to the video signal by emitting light corresponding to the video signal (that is, the current signal) supplied to the data lines DL. To this end, each of the PE cells 22 is a cell driving circuit for driving the light emitting cell OEL according to a driving signal supplied from each of the data line DL and the gate electrode lines GL, as shown in FIG. 3. And a light emitting cell OEL connected between the cell driving circuit 50 and the ground voltage source GND.

The cell driving circuit 50 includes a driving thin film transistor (TFT) DT connected between the voltage supply line VDD and the light emitting cell OEL, and the odd gate line GLo. And the first switching TFT T1 connected between the data line DL and the second switching TFT T2 connected between the first switching TFT T1 and the even-numbered gate line GLe, A mirror TFT MT connected between the node N1 between the second switching TFTs T1 and T2 and the voltage supply line VDD to form a current mirror circuit with the driving TFT DT, and the driving TFT DT; And a storage capacitor Cst connected between the node N2 between the mirror TFT MT and the voltage supply line VDD. Here, the TFTs are P-type electron metal oxide semiconductor field effect transistors (MOSFETs).

The gate terminal of the driving TFT DT is connected to the gate terminal of the mirror TFT MT, and the source terminal is connected to the voltage supply line VDD. The drain terminal of the driving TFT DT is connected to the light emitting cell OEL. A first node having a source terminal of the mirror TFT MT connected to a voltage supply line VDD, and a drain terminal connected to a drain terminal of the first switching TFT T1 and a source terminal of the second switching TFT T2. It is connected to (N1). Here, the driving TFT DT and the mirror TFT MT are connected to form a current mirror. Therefore, assuming that the driving TFT DT and the mirror TFT MT have the same channel width, the amount of current flowing through the driving TFT DT and the mirror TFT MT is set equally.

The source terminal of the first switching TFT T1 is connected to the data line DL, and the gate terminal is connected to the odd-numbered gate line GLo. The drain terminal of the second switching TFT T2 is connected to the second node N2, and the gate terminal is connected to the even-numbered gate line GLe.

The operation process of the cell driving circuit 50 will be described in detail using the driving waveform of FIG. 4. First, the cell driving circuit 50 has the same width as the odd-numbered electrode line GLo and the even-numbered electrode line GLe forming the same horizontal line. The first and second scan pulses SP1 and SP2 are supplied to overlap each other for a predetermined period. Here, the second scan pulse SP2 is applied before the first scan pulse SP1.

When the first and second scan pulses SP1 and SP2 are supplied, the first and second switching TFTs T1 and T2 are turned on. When the first and second switching TFTs T1 and T2 are turned on, the video signal from the data line DL is driven through the first and second switching TFTs T1 and T2 and the driving TFT DT and the mirror TFT. It is supplied to the gate terminal of the MT (ie, the second node N2). The driving TFT DT and the mirror TFT MT are turned on by the video signal supplied on the second node N2 via the first and second switching TFTs T1 and T2. Accordingly, the driving TFT DT controls the current flowing from its source terminal (ie, VDD) to the drain terminal according to the video signal supplied to its gate terminal and supplies the light to the light emitting cell OEL by supplying the light emitting cell OEL. ) Controls to emit light of brightness corresponding to the video signal.

At the same time, the mirror TFT MT supplies the current id supplied from the voltage supply line VDD to the data line DL via the first switching TFT T1. Here, since the driving TFT DT and the mirror TFT MT form a current mirror circuit, the same current I flows through the driving TFT DT and the mirror TFT MT. Meanwhile, the storage capacitor Cst stores the voltage from the voltage supply line VDD so as to correspond to the amount of current id flowing to the mirror TFT MT. In the storage capacitor Cst, the first and second scan pulses SP1 and SP2 are turned off (for example, the base potential), and the first and second switching TFTs T1 and T2 are turned off. When the driving TFT DT is turned on using the voltage stored therein, the current is supplied to the light emitting cell OEL until the video signal of the next frame is supplied. On the other hand, in the related art, since the second scan pulse SP2 is first switched to the off signal, that is, since the second switching TFT T2 is turned off before the first switching TFT T1, the storage capacitor Cst is charged. The discharged voltage can be prevented from being discharged to the outside.

Substantially, the conventional EL display device sequentially supplies the first and second scan pulses SP1 and SP2 to the odd-numbered gate lines GLo and the even-numbered gate electrode lines GLe, as well as the data lines. The predetermined image is displayed by supplying the video signal to the DL). However, the conventional EL display device has a low aperture ratio because two gate lines GLO and GLe are formed in one horizontal line and four TFTs are formed to drive one light emitting cell OEL. There is this.

Accordingly, it is an object of the present invention to provide an electro-luminescence display device capable of ensuring a high aperture ratio.

In order to achieve the above object, an electro-luminescence display device according to an embodiment of the present invention is connected to each of the electro luminescence cells arranged at each intersection of gate lines and data lines, and to each of the electro luminescence cells. A plurality of cell driving circuits configured to control a current supplied to each of the electroluminescent cells and the cell driving circuits vertically neighboring the video signal from each of the data lines. And a plurality of control circuits selectively supplying the cell driving circuit.

The electro-luminescence display is a voltage supply line for supplying a driving voltage to the electroluminescence cells, and a first scan pulse having a turn-on potential for one horizontal period to the gate lines. And a first gate driver and a second gate driver for supplying the plurality of control circuits with a second scan pulse having a turn-on potential for two horizontal periods.

In the electro-luminescence display, each of the cell driving circuits includes a driving thin film transistor having a source terminal connected to the supply voltage line and a drain terminal connected to the electroluminescent cell, and a gate terminal connected to a gate line. A first switching thin film transistor having a source terminal connected to the control circuit and a drain terminal connected to a gate terminal of a driving thin film transistor, and a node between a gate terminal of the driving thin film transistor and a drain terminal of the first switching thin film transistor And a storage capacitor connected between the supply voltage source.

Each of the control circuits in the electro-luminescence display includes a mirror thin film transistor having a source terminal connected to the supply voltage line and a drain terminal connected to a gate terminal thereof, and a clock signal supplied with the second scan pulse. And a second switching thin film transistor having a gate terminal connected to a supply line, a source terminal connected between the data lines, and a drain terminal connected to a gate terminal of the mirror thin film transistor.

The source terminal of the first switching thin film transistor in the electro-luminescence display is connected to a first node between the drain terminal of the second switching thin film transistor and the gate terminal of the mirror thin film transistor.

In the electro-luminescence display, an upper cell of the neighboring cell driving circuits is formed in a first section in which the first scan pulse supplied to the i-th gate line and the second scan pulse supplied to the clock signal supply line overlap each other. The video signal is supplied to a driving circuit.

In the electro-luminescence display, the video signal from the data line in the first section is passed through the second switching thin film transistor, the first node, and the first switching thin film transistor of the upper cell driving circuit. And a gate terminal of the driving thin film transistor.

In the second period in which the first scan pulse supplied to the i + 1 th gate line and the second scan pulse supplied to the clock signal supply line overlap each other in the electro-luminescence display device, The video signal is supplied to a lower cell driving circuit.

In the electro-luminescence display, the video signal from the data line in the second section is transferred via the second switching thin film transistor, the first node, and the first switching thin film transistor of the lower cell driving circuit. And a gate terminal of the driving thin film transistor.

In the electro-luminescence display, the mirror thin film transistor forms a current mirror with the driving thin film transistor to transfer a current corresponding to the video signal from the voltage supply line to the data line via the second switching thin film transistor. It is characterized by the supply.

In the electro-luminescence display, the second scan pulse is supplied before the first scan pulse for a predetermined period.

In the electro-luminescence display, the first and second gate drivers are integrated into one chip.

In accordance with another aspect of the present invention, an electroluminescent display device includes an electroluminescence cell disposed at each intersection of gate lines and data lines, and a supply voltage for supplying a driving voltage to the electroluminescence cells. A plurality of cell driving circuits connected to a voltage supply line and each of the electro luminescence cells to supply a current corresponding to the video signal from the data line to the electro luminescence cell from the voltage supply line; A plurality of control circuits, which are shared by the cell driving circuits adjacent to each other and selectively supply current from the voltage supply line to the data line, corresponding to the video signal supplied to each of the up and down neighboring cell driving circuits. It is characterized by including.

In the electro-luminescence display, each of the cell driving circuits includes a driving thin film transistor having a source terminal connected to the supply voltage line and a drain terminal connected to the electroluminescent cell, and a gate terminal connected to a gate line. A first switching thin film transistor having a source terminal connected to the data line and a drain terminal connected to a gate terminal of a driving thin film transistor, and a first between a gate terminal of the driving thin film transistor and a drain terminal of the first switching thin film transistor. And a storage capacitor connected between the node and the supply voltage source.

The electro-luminescence display device includes a first gate driver for supplying a first scan pulse having a turn-on potential to the gate lines for one horizontal period, and a turn to the plurality of control circuits for one horizontal period. And a second gate driver for supplying a second scan pulse having an on-potential.

In the electro-luminescence display, each of the control circuits includes a mirror thin film transistor having a source terminal connected to the supply voltage line and a drain terminal connected to its gate terminal, and an i th second supplying the second scan pulse. (I is a natural number) A gate terminal is connected to a clock signal supply line, a source terminal is connected to the first node of an upper cell driving circuit among the neighboring cell driving circuits, and a drain terminal is connected to the gate terminal of the mirror thin film transistor. And a gate terminal connected to an i + 1 th clock signal supply line, a source terminal connected to the first node of a lower cell driving circuit among the neighboring cell driving circuits, and the mirror thin film And a third switching thin film transistor having a drain terminal connected to the gate terminal of the transistor. It is done.

In the electro-luminescence display, the mirror thin film transistor includes the neighboring portion in a first section in which the first scan pulse supplied to an i-th gate line and the second scan pulse supplied to the i-th clock signal supply line overlap each other. The current corresponding to the video signal supplied to the upper cell driving circuit of the cell driving circuit is supplied from the supply voltage line to the data line.

In the electro-luminescence display, the current corresponding to the video signal in the first section is transmitted through the second switching thin film transistor, the first node of the upper cell driving circuit, and the first switching thin film transistor. It is characterized by being supplied to the line.

In the electro-luminescence display, the mirror thin film transistor includes a second overlapping first scan pulse supplied to an i + 1 th gate line and a second scan pulse supplied to the i + 1 th clock signal supply line; And supplying a current corresponding to the video signal supplied to the lower cell driving circuit among the neighboring cell driving circuits from the supply voltage line to the data line in the section.

The current corresponding to the video signal in the second period in the electro-luminescence display is configured to pass the data through the third switching thin film transistor, the first node of the lower cell driving circuit, and the first switching thin film transistor. It is characterized by being supplied to the line.

In the electro-luminescence display, the second scan pulse is supplied before the first scan pulse for a predetermined period.

In the electro-luminescence display, the first and second gate drivers are integrated into one chip.

The electro-luminescence display further includes a gate driver for sequentially supplying scan pulses having a turn-on potential to the gate lines for one horizontal period.

In the electro-luminescence display, each of the control circuits includes a mirror thin film transistor having a source terminal connected to the supply voltage line and a drain terminal connected to its gate terminal, and a gate terminal connected to the i-th gate line. And a second switching thin film transistor having a source terminal connected to the first node of an upper cell driving circuit among the neighboring cell driving circuits, and a drain terminal connected to a gate terminal of the mirror thin film transistor, and the i + 1 th gate. A third switching thin film transistor having a gate terminal connected to a line, a source terminal connected to the first node of a lower cell driving circuit among the neighboring cell driving circuits, and a drain terminal connected to a gate terminal of the mirror thin film transistor; Characterized in that.

In the electro-luminescence display, the mirror thin film transistor corresponds to the video signal supplied to an upper cell driving circuit among neighboring cell driving circuits in a first section in which the scan pulse is supplied to the i-th gate line. The current is supplied from the supply voltage line to the data line.

In the electro-luminescence display, the current corresponding to the video signal in the first section is transmitted through the second switching thin film transistor, the first node of the upper cell driving circuit, and the first switching thin film transistor. It is characterized by being supplied to the line.

In the electro-luminescence display, the mirror thin film transistor is connected to the video signal supplied to a lower cell driving circuit among the neighboring cell driving circuits in a second section in which the scan pulse is supplied to the i + 1th gate line. The corresponding current is supplied from the supply voltage line to the data line.

The current corresponding to the video signal in the second period in the electro-luminescence display is configured to pass the data through the third switching thin film transistor, the first node of the lower cell driving circuit, and the first switching thin film transistor. It is characterized by being supplied to the line.

In the electro-luminescence display, each of the control circuits includes a mirror thin film transistor having a source terminal connected to the supply voltage line and a drain terminal connected to its gate terminal, and an i th second supplying the second scan pulse. A gate terminal is connected to a clock signal supply line, a source terminal is connected to a second node between the first switching thin film transistor of the upper cell driving circuit and the data line among the neighboring cell driving circuits, and the gate terminal of the mirror thin film transistor. A second switching thin film transistor having a drain terminal connected thereto, and a gate terminal connected to the i + 1 th clock signal supply line, and between the first switching thin film transistor of a lower cell driving circuit of the neighboring cell driving circuit and the data line. A source terminal is connected to the second node, and the mirror thin film transistor A drain terminal connected to the gate terminal of the claim is characterized in that it comprises three switching thin film transistor.

In the electro-luminescence display, the mirror thin film transistor may be formed in a first section in which the first scan pulse supplied to the i-th gate line and the second scan pulse supplied to the i-th clock signal supply line overlap each other. A current corresponding to the video signal supplied to an upper cell driving circuit among neighboring cell driving circuits is supplied from the supply voltage line to the data line.

In the electro-luminescence display, a current corresponding to the video signal in the first section is supplied to the data line via the second switching thin film transistor and the second node of the upper cell driving circuit. It is done.

In the electro-luminescence display, the mirror thin film transistor includes the first scan pulse supplied to the i + 1 th gate line and the second scan pulse supplied to the i + 1 th clock signal supply line. And supplying a current corresponding to the video signal supplied to a lower cell driving circuit among the neighboring cell driving circuits from the supply voltage line to the data line in a second section.

The current corresponding to the video signal in the second period of the electro-luminescence display is supplied to the data line via the third node of the third switching thin film transistor and the lower cell driving circuit. It is done.

In the electro-luminescence display, each of the control circuits includes a mirror thin film transistor having a source terminal connected to the supply voltage line and a drain terminal connected to its gate terminal, and a gate terminal connected to the i-th gate line. And a second switching node having a source terminal connected to a second node between the first switching thin film transistor of the upper cell driving circuit and the data line among the neighboring cell driving circuits, and a drain terminal connected to a gate terminal of the mirror thin film transistor. A gate terminal is connected to the thin film transistor and the i + 1 th gate line, and a source terminal is connected to a second node between the first switching thin film transistor of the lower cell driving circuit and the data line among the neighboring cell driving circuits. A drain terminal is connected to the gate terminal of the mirror thin film transistor Article characterized in that it comprises three switching thin film transistor.

In the electro-luminescence display, the mirror thin film transistor corresponds to the video signal supplied to an upper cell driving circuit among neighboring cell driving circuits in a first section in which the scan pulse is supplied to the i-th gate line. The current is supplied from the supply voltage line to the data line.

In the electro-luminescence display, a current corresponding to the video signal in the first section is supplied to the data line via the second switching thin film transistor and the second node of the upper cell driving circuit. It is done.

In the electro-luminescence display, the mirror thin film transistor is connected to the video signal supplied to a lower cell driving circuit among the neighboring cell driving circuits in a second section in which the scan pulse is supplied to the i + 1th gate line. The corresponding current is supplied from the supply voltage line to the data line.

The current corresponding to the video signal in the second period of the electro-luminescence display is supplied to the data line via the third node of the third switching thin film transistor and the lower cell driving circuit. It is done.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 14.

Referring to FIG. 5, an EL display device according to an exemplary embodiment of the present invention includes an EL display panel 116 including PE cells 122 arranged at intersections of a gate line GL and a data line DL; The first gate driver 118 for supplying the first scan pulse SP1 to the gate lines GL, the data driver 120 for driving the data lines DL, and the adjacent gate line GL. Supplying the second scan pulse SP2 to the control circuits 124 and the control circuits 124 to control the two PE cells 122 according to the second scan pulse SP2 that is formed and input between them. The second gate driver 119 is provided.

As illustrated in FIG. 6, the first gate driver 118 sequentially shifts the first scan pulse SP1 having a width of one horizontal section and sequentially supplies the first scan pulse SP1 to the gate lines GL. The second gate driver 119 sequentially generates a second scan pulse SP2 having a width between two horizontal sections and sequentially supplies the clock signal supply line GM formed between adjacent gate lines GL. At this time, the first scan pulse SP1 is supplied to overlap the second scan pulse SP2 for one horizontal section. Meanwhile, the first and second gate drivers 118 and 119 may be integrated into one chip. Accordingly, the one-chip first gate driver 118 generates the aforementioned first and second scan pulses SP1 and SP2 and supplies them to the gate line GL and the clock signal supply line GM.

The data driver 120 supplies a video signal corresponding to the data to the PE cell 122 via the data lines DL and the control circuit 124. In this case, the data driver 120 supplies one horizontal line of video signals to the data lines DL every one horizontal period in which the first scan pulse SP1 is supplied.

The PE cells 122 display an image corresponding to the video signal by emitting light corresponding to the video signal (that is, the current signal) supplied to the data lines DL. To this end, each of the PE cells 122 is a light emitting cell OEL connected between the voltage supply line VDD and the base voltage source GND and a light emitting cell OEL as shown in FIG. 7. The cell drive circuit 150 is provided.

The cell driving circuit 150 includes a driving thin film transistor (TFT) DT connected between the voltage supply line VDD and the light emitting cell OEL, a driving TFT DT, and a gate. Storage connected between the first switching TFT T1 connected between the lines GL and the first node N1 and the voltage supply line VDD between the driving TFT DT and the first switching TFT T1. Capacitor Cst is provided. Here, the TFTs are P-type electron metal oxide semiconductor field effect transistors (MOSFETs).

The gate terminal of the driving TFT DT is connected to the drain terminal of the first switching TFT T1, that is, the first node N1, and the source terminal is connected to the voltage supply line VDD. The drain terminal of the driving TFT DT is connected to the light emitting cell OEL. The source terminal of the first switching TFT T1 is connected to the control circuit 124, and the gate terminal is connected to the gate line GL. The drain terminal of the first switching TFT T1 is connected to the first node N1, that is, the gate terminal of the driving TFT DT. The storage capacitor Cst stores the video signal on the first node N1 when the first switching TFT T1 is in an on state, and when the first switching TFT T1 is turned off, the storage capacitor Cst stores the video signal of the next frame using the stored video signal. It serves to maintain the on state of the driving TFT DT until the video signal is supplied.

The cell driving circuit 150 may emit light according to a video signal supplied from the data line DL via the control circuits 124 according to the first scan pulse SP1 supplied to the gate line GL. The amount of current from the voltage supply line VDD via OEL) is controlled.

Each of the control circuits 124 includes a second switching TFT T2 connected between the data line DL and the clock signal supply line GM, and between the second switching TFT T2 and the voltage supply line VDD. A connected mirror TFT (MT) is provided.

The source terminal of the second switching TFT T2 is connected to the data line DL, and the gate terminal is connected to the clock signal supply line GM. The drain terminal of the second switching TFT T2 is connected to the gate terminal of the mirror TFT MT.

The source terminal of the mirror TFT MT is connected to the supply voltage line VDD, and the drain terminal and the gate terminal are connected to the drain terminal of the second switching TFT T2. At this time, the second node N2 between the second switching TFT T2 and the mirror TFT MT is connected to the first switching TFT T1 of the cell driving circuit 150 connected to the i-th gate line GLi. It is connected to the source terminal and to the source terminal of the first switching TFT T1 of the cell driving circuit 150 connected to the i + 1th gate line GLi + 1. The mirror TFT MT is formed by scanning in the same direction to form a current mirror with the driving TFT DT of each of the cell driving circuits 150 adjacent to the upper and lower sides. Therefore, assuming that the driving TFT DT and the mirror TFT MT of each of the adjacent cell driving circuits 150 have the same channel width, the driving TFT DT and the mirror TFT MT of each of the adjacent cell driving circuits 150 are MT. The amount of current flowing through) is set equally.

The operation of the PE cells 122 according to the present invention will be described in detail with reference to the driving waveform shown in FIG. 6. First, a second scan having a turn-on potential in the clock signal supply line GM for two horizontal periods will be described. In addition to supplying the pulse SP2, the first scan pulse SP1 shifted by one horizontal period is sequentially supplied to the gate line GL. At this time, the first scan pulse SP1 is supplied before the second scan pulse SP2 for a predetermined period.

First, the cell driving circuit 150 connected to the i-th gate line GLi is hereinafter referred to as the upper cell driving circuit 150, and the cell driving circuit 150 connected to the i + 1 th gate line GLi + 1. Hereinafter referred to as a lower cell driving circuit 150.

The first switching TFT T1 of the upper cell driving circuit 150 is turned on by the first scan pulse SP1 supplied to the i-th gate line GLi. The second switching pulse of the control circuit 124 is supplied by supplying the second scan pulse SP2 to the i-th clock signal supply line GMi while the first switching TFT T1 of the upper cell driving circuit 150 is turned on. The TFT T2 is turned on. When the second switching TFT T2 of the control circuit 124 connected to the i-th clock signal supply line GMi is turned on, the video signal from the data line DL passes through the second switching TFT T2. It is supplied on the second node N2. The video signal supplied on the second node N2 is supplied to the gate terminal of the driving TFT DT via the first switching TFT T1 of the upper cell driving circuit 150. Accordingly, the driving TFT DT of the upper cell driving circuit 150 adjusts the current flowing from its source terminal (ie, VDD) to the drain terminal according to the video signal supplied to its gate terminal, thereby emitting the light emitting cell OEL. ) To control the light of the brightness corresponding to the video signal to be emitted from each of the light emitting cells OEL connected to the i-th gate line GLi.

At the same time, the mirror TFT MT of the control circuit 124 supplies the current supplied from the voltage supply line VDD to the data line DL via the second switching TFT T2. Here, since the driving TFT DT and the mirror TFT MT form a current mirror circuit, the same current flows in the driving TFT DT and the mirror TFT MT.

Meanwhile, the storage capacitor Cst of the upper cell driving circuit 150 stores the voltage from the voltage supply line VDD so as to correspond to the amount of current flowing to the mirror TFT MT of the control circuit 124. The storage capacitor Cst of the upper cell driving circuit 150 turns on the driving TFT DT of the upper cell driving circuit 150 using the voltage stored therein when the video signal is not supplied, thereby turning on the next frame. The current is supplied to the light emitting cell OEL until the video signal is supplied.

Subsequently, the first scan pulse SP1 supplied to the i-th gate line GLi is turned off, and the first scan pulse SP1 is supplied to the i + 1 th gate line GLi + 1, so that the lower cell driving circuit ( The first switching TFT T1 of 150 is turned on. At this time, the second switching TFT T2 of the control circuit 124 is kept in the on state by the second scan pulse SP2.

When the first switching TFT T1 of the lower cell driving circuit 150 is turned on, the video signal from the data line DL is supplied on the second node N2 via the second switching TFT T2. . The video signal supplied on the second node N2 is supplied to the gate terminal of the driving TFT DT via the first switching TFT T1 of the lower cell driving circuit 150. Accordingly, the driving TFT DT of the lower cell driving circuit 150 adjusts the current flowing from its source terminal (ie, VDD) to the drain terminal according to the video signal supplied to its gate terminal, thereby emitting the light emitting cell OEL. ) To control the light of the brightness corresponding to the video signal to be emitted from each of the light emitting cells OEL connected to the i + 1 th gate line GLi + 1.

At the same time, the mirror TFT MT of the control circuit 124 supplies the current supplied from the voltage supply line VDD to the data line DL via the second switching TFT T2. Here, since the driving TFT DT and the mirror TFT MT form a current mirror circuit, the same current flows in the driving TFT DT and the mirror TFT MT.

On the other hand, the storage capacitor Cst of the lower cell driving circuit 150 stores the voltage from the voltage supply line VDD so as to correspond to the amount of current flowing to the mirror TFT MT of the control circuit 124. The storage capacitor Cst of the lower cell driving circuit 150 turns on the driving TFT DT of the lower cell driving circuit 150 by using a voltage stored therein when the video signal is not supplied, thereby turning on the next frame. The current is supplied to the light emitting cell OEL until the video signal is supplied.

In practice, the EL display device according to the first embodiment of the present invention displays a predetermined image while repeating such a process.

In the EL display device according to the first exemplary embodiment of the present invention, one control circuit 150 is provided between upper and lower adjacent cell driving circuits 122 and a second scan supplied to the control circuit 150 is provided. The current is compensated by connecting the driving TFT DT of the cell driving circuit 122 and the mirror TFT MT of the control circuit 124 in the form of a current mirror on the upper and lower sides according to the pulse SP2. Accordingly, the EL display device according to the first embodiment of the present invention can increase the aperture ratio by reducing the number of TFTs for driving two light emitting cells OEL adjacent to the top / bottom side from the conventional eight to six. In addition, the EL display device according to the first embodiment of the present invention drives two light emitting cells OEL adjacent up and down by using one clock signal supply line GM and two gate lines GL. Therefore, the aperture ratio can be increased by reducing the conventional four horizontal lines to three. As a result, the EL display device according to the first embodiment of the present invention can further improve the aperture ratio due to the reduction in the number of TFTs and the number of horizontal lines for driving two light emitting cells OEL adjacent to the top and bottom sides. .

Referring to FIG. 8, the EL display device according to the second exemplary embodiment of the present invention includes an EL display panel 216 including PE cells 222 arranged at each intersection of the gate line GL and the data line DL. And a first gate driver 218 for supplying the first scan pulse SP1 to the gate lines GL, a data driver 220 for driving the data lines DL, and an adjacent gate line. Control circuits 224 for controlling two PE cells 222 adjacent to each other up and down according to the second scan pulse SP2 that is formed and input between GLs, and a second scan to the control circuits 224. A second gate driver 219 for supplying the pulse SP2 is provided.

As illustrated in FIG. 9, the first gate driver 218 sequentially shifts the first scan pulse SP1 having a width of one horizontal section and sequentially supplies the first scan pulse SP1 to the gate lines GL. The second gate driver 219 generates a second scan pulse SP2 having the same width as the first scan pulse SP1 and sequentially supplies the control signal supply line GM formed between adjacent gate lines GL. do. At this time, the second scan pulse SP2 is supplied before the first scan pulse SP1 for a predetermined period. Meanwhile, the first and second gate drivers 218 and 219 may be integrated into one chip. Accordingly, the one-chip first gate driver 218 generates the above-described first and second scan pulses SP1 and SP2 and supplies them to the gate line GL and the clock signal supply line GM.

The data driver 220 supplies a video signal corresponding to the data to the PE cell 222 via the data lines DL and the control circuits 224. In this case, the data driver 220 supplies one horizontal line of video signals to the data lines DL every one horizontal period in which the first scan pulse SP1 is supplied.

The PE cells 222 display an image corresponding to the video signal by emitting light corresponding to the video signal (ie, the current signal) supplied to the data lines DL. To this end, each of the PE cells 222 is a light emitting cell OEL connected between the voltage supply line VDD and the base voltage source GND and a light emitting cell OEL as shown in FIG. 10. The cell driving circuit 250 is provided.

The cell driving circuit 250 is connected between the driving TFT DT connected between the voltage supply line VDD and the light emitting cell OEL, and is connected between the driving TFT DT, the gate line GL, and the data line DL. And a storage capacitor Cst connected between the first switching TFT T1 and the first node N1 between the driving TFT DT and the first switching TFT T1 and the voltage supply line VDD. Here, the TFTs are P-type electron metal oxide semiconductor field effect transistors (MOSFETs).

The gate terminal of the driving TFT DT is connected to the drain terminal of the first switching TFT T1, that is, the first node N1, and the source terminal is connected to the voltage supply line VDD. The drain terminal of the driving TFT DT is connected to the light emitting cell OEL. The source terminal of the first switching TFT T1 is connected to the data line DL, and the gate terminal is connected to the gate line GL. The drain terminal of the first switching TFT T1 is connected to the first node N1, that is, the gate terminal of the driving TFT DT. The storage capacitor Cst stores the video signal on the first node N1 when the first switching TFT T1 is in an on state, and when the first switching TFT T1 is turned off, the storage capacitor Cst stores the video signal of the next frame using the stored video signal. It serves to maintain the on state of the driving TFT DT until the video signal is supplied.

The cell driving circuit 250 emits light according to a video signal supplied from the data line DL via the control circuits 124 according to the first scan pulse SP1 supplied to the gate line GL. The amount of current from the voltage supply line VDD via OEL) is controlled.

Each of the control circuits 224 includes a second switching TFT T2 connected between the cell driving circuit 250 connected to the i-th gate line GLi and the i-th clock signal supply line GMi, and i + 1. A third switching TFT T3 and a second switching TFT T2 connected between the cell driving circuit 250 connected to the first gate line GLi + 1 and the i + 1 th clock signal supply line GMi + 1; ) And a mirror TFT MT connected between the second node N2 and the supply voltage line VDD between the third switching TFT T3.

The source terminal of the second switching TFT T2 is connected to the gate terminal of the second node N2, that is, the mirror TFT MT, and the gate terminal is connected to the i-th clock signal supply line GMi. The drain terminal of the second switching TFT T2 is connected to the first node N1 of the cell driving circuit 250 connected to the i-th gate line GLi. The source terminal of the third switching TFT T3 is connected to the gate terminal of the second node N2, that is, the mirror TFT MT, and the gate terminal is connected to the i + 1 th clock signal supply line GMi + 1. . The drain terminal of the third switching TFT T3 is connected to the first node N1 of the cell driving circuit 250 connected to the i + 1th gate line GLi + 1.

The source terminal of the mirror TFT MT is connected to the supply voltage line VDD, and the drain terminal and the gate terminal are connected to the second node N2, that is, the source terminals of the second and third switching TFTs T2 and T3. do. The mirror TFT MT is formed by scanning in the same direction to form a current mirror with the driving TFT DT of each of the cell driving circuits 250 adjacent to the upper and lower sides. Therefore, assuming that the driving TFT DT and the mirror TFT MT of each of the adjacent cell driving circuits 250 have the same channel width, the driving TFT DT and the mirror TFT MT of each of the adjacent cell driving circuits 250 are MT. The amount of current flowing through) is set equally.

The operation process of the PE cells 222 of the EL display device according to the second embodiment of the present invention will be described in detail by using the driving waveform shown in FIG. 9. First, one horizontal period in the clock signal supply line GM will be described. The second scan pulse SP2 of the turn-on potential shifted in units is supplied, and the first scan pulse SP1 shifted in units of one horizontal period is sequentially supplied to the gate line GL. At this time, the second scan pulse SP2 is supplied before the first scan pulse SP1 for a predetermined period. In addition, the cell driving circuit 250 connected to the i-th gate line GLi is hereinafter referred to as the upper cell driving circuit 150, and the cell driving circuit 250 connected to the i + 1 th gate line GLi + 1. Hereinafter referred to as a lower cell driving circuit 150.

The second switching TFT T2 of the control circuit 224 is turned on by the second scan pulse SP2 supplied to the i-th clock signal supply line GMi. Since the first scan pulse SP1 is supplied to the i-th gate line GLi with the second switching TFT T2 of the control circuit 224 turned on, the first switching TFT of the upper cell driving circuit 250 ( T1) is turned on. The first switching TFT T1 of the upper cell driving circuit 250 is turned on so that a video signal from the data line DL is supplied on the first node N1 via the first switching TFT T1. . The video signal supplied on the first node N1 is supplied to the gate terminal of the driving TFT DT of the upper cell driving circuit 250 and via the second switching TFT T2 of the control circuit 224. It is supplied on the second node N2. The driving TFT DT and the mirror TFT MT are turned on by the video signals supplied on the first and second nodes N1 and N2. Accordingly, the driving TFT DT of the upper cell driving circuit 250 adjusts the current flowing from its source terminal (ie, VDD) to the drain terminal according to the video signal supplied to its gate terminal, thereby emitting the light emitting cell OEL. ) To control the light of the brightness corresponding to the video signal to be emitted from each of the light emitting cells OEL connected to the i-th gate line GLi.

At the same time, the mirror TFT MT of the control circuit 224 receives the current supplied from the voltage supply line VDD from the first node of the second node N2, the second switching TFT T2, and the upper cell driving circuit 250. The data line DL is supplied to the data line DL via the node N1 and the first switching TFT T1. Here, since the driving TFT DT and the mirror TFT MT form a current mirror circuit, the same current flows in the driving TFT DT and the mirror TFT MT.

Meanwhile, the storage capacitor Cst of the upper cell driving circuit 250 stores the voltage from the voltage supply line VDD so as to correspond to the amount of current flowing to the mirror TFT MT of the control circuit 224. The storage capacitor Cst of the upper cell driving circuit 250 turns on the driving TFT DT of the upper cell driving circuit 250 using a voltage stored therein when the video signal is not supplied, thereby turning on the next frame. The current is supplied to the light emitting cell OEL until the video signal is supplied.

Thereafter, the second scan pulse SP2 supplied to the i-th clock signal supply line GMi is turned off, and the second scan pulse SP2 is supplied to the i + 1 th clock signal supply line GMi + 1. Accordingly, the third switching TFT T3 of the control circuit 224 is turned on by the second scan pulse SP2 supplied to the i + 1 th clock signal supply line GMi + 1. When the third switching TFT T3 of the control circuit 224 is turned on, the first scan pulse SP1 is supplied to the i + 1 th gate line GLi + 1 to supply the first cell of the lower cell driving circuit 250. 1 switching TFT T1 is turned on. The first switching TFT T1 of the lower cell driving circuit 250 is turned on so that the video signal from the data line DL is supplied on the first node N1 via the first switching TFT T1. . The video signal supplied on the first node N1 is supplied to the gate terminal of the driving TFT DT of the lower cell driving circuit 250 and via the third switching TFT T3 of the control circuit 224. It is supplied on the second node N2. The driving TFT DT and the mirror TFT MT are turned on by the video signals supplied on the first and second nodes N1 and N2. Accordingly, the driving TFT DT of the lower cell driving circuit 250 adjusts the current flowing from its source terminal (ie, VDD) to the drain terminal according to the video signal supplied to its gate terminal, thereby causing the light emitting cell OEL. ) To control the light of the brightness corresponding to the video signal to be emitted from each of the light emitting cells OEL connected to the i + 1 th gate line GLi + 1.

At the same time, the mirror TFT MT of the control circuit 224 receives the current supplied from the voltage supply line VDD from the first node of the second node N2, the third switching TFT T3, and the lower cell driving circuit 250. The data line DL is supplied to the data line DL via the node N1 and the first switching TFT T1. Here, since the driving TFT DT and the mirror TFT MT form a current mirror circuit, the same current flows in the driving TFT DT and the mirror TFT MT.

The storage capacitor Cst of the lower cell driving circuit 250 stores the voltage from the voltage supply line VDD so as to correspond to the amount of current flowing to the mirror TFT MT of the control circuit 224. The storage capacitor Cst of the lower cell driving circuit 250 turns on the driving TFT DT of the lower cell driving circuit 250 using the voltage stored therein when the video signal is not supplied, thereby turning on the next frame. The current is supplied to the light emitting cell OEL until the video signal is supplied.

In practice, the EL display device according to the second embodiment of the present invention displays a predetermined image while repeating such a process.

In the EL display device according to the second exemplary embodiment of the present invention, one control circuit 250 is provided between upper and lower adjacent cell driving circuits 222 and a second scan supplied to the control circuit 250 is provided. The current is compensated by connecting the driving TFT DT of the cell driving circuit 222 and the mirror TFT MT of the control circuit 224 in the form of a current mirror on the upper and lower sides according to the pulse SP2. Accordingly, the EL display device according to the second embodiment of the present invention can increase the aperture ratio by reducing the number of TFTs for driving two light emitting cells OEL adjacent to the top / bottom side from the conventional eight to seven.

Referring to FIG. 11, the EL display device according to the third exemplary embodiment of the present invention may include a clock signal supply line GM and a second gate driver in the EL display device according to the second exemplary embodiment of the present invention illustrated in FIG. 10. It will have the same components, except that 219 is deleted. In other words, the EL display device according to the third embodiment of the present invention is identical to the EL display device according to the second embodiment of the present invention except for the connection relationship between the second and third switching TFTs T2 and T3. It has a configuration and connection relationship. Therefore, in the EL display device according to the third embodiment of the present invention, only the connection relationship between the second and third switching TFTs T2 and T3 is described, and then the same reference numerals as those of the EL display device according to the second embodiment of the present invention. The operation of the PE cell 222 will be described with reference to FIG.

In the EL display device according to the third embodiment of the present invention, the gate terminal of the second switching TFT (T2) is connected to the i-th gate line GLi, and the gate terminal of the third switching TFT (T3) is i + 1th. It is connected to the gate line GLi + 1. Accordingly, the second switching TFT T2 is simultaneously turned on or turned on to the first switching TFT T1 of the upper cell driving circuit 250 by the scan pulse SP supplied to the i-th gate line GLi. -Off. In addition, the third switching TFT T3 is simultaneously turned on to the first switching TFT T1 of the lower cell driving circuit 250 by the scan pulse SP supplied to the i + 1 th gate line GLi + 1. On or off.

The operation of the PE cells 222 of the EL display device according to the third embodiment of the present invention will be described in detail with reference to the driving waveform shown in FIG.

The first switching TFT T1 of the upper cell driving circuit 250 and the second switching TFT T2 of the control circuit 224 are turned on by the scan pulse SP supplied to the i-th gate line GLi. do. As the first switching TFT T1 of the upper cell driving circuit 250 is turned on, the first switching TFT T1 of the upper cell driving circuit 250 is turned on. The first switching TFT T1 of the upper cell driving circuit 250 is turned on so that a video signal from the data line DL is supplied on the first node N1 via the first switching TFT T1. . The video signal supplied on the first node N1 is supplied to the gate terminal of the driving TFT DT of the upper cell driving circuit 250 and via the second switching TFT T2 of the control circuit 224. It is supplied on the second node N2. The driving TFT DT and the mirror TFT MT are turned on by the video signals supplied on the first and second nodes N1 and N2. Accordingly, the driving TFT DT of the upper cell driving circuit 250 adjusts the current flowing from its source terminal (ie, VDD) to the drain terminal according to the video signal supplied to its gate terminal, thereby emitting the light emitting cell OEL. ) To control the light of the brightness corresponding to the video signal to be emitted from each of the light emitting cells OEL connected to the i-th gate line GLi.

At the same time, the mirror TFT MT of the control circuit 224 receives the current supplied from the voltage supply line VDD from the first node of the second node N2, the second switching TFT T2, and the upper cell driving circuit 250. The data line DL is supplied to the data line DL via the node N1 and the first switching TFT T1. Here, since the driving TFT DT and the mirror TFT MT form a current mirror circuit, the same current flows in the driving TFT DT and the mirror TFT MT.

Meanwhile, the storage capacitor Cst of the upper cell driving circuit 250 stores the voltage from the voltage supply line VDD so as to correspond to the amount of current flowing to the mirror TFT MT of the control circuit 224. The storage capacitor Cst of the upper cell driving circuit 250 turns on the driving TFT DT of the upper cell driving circuit 250 by using a voltage stored therein when the video signal is not supplied. The current is supplied to the light emitting cell OEL until the video signal is supplied.

Thereafter, the scan pulse SP supplied to the i-th gate line GLi is turned off, and the scan pulse SP is supplied to the i + 1 th gate line GLi + 1. Accordingly, the first switching TFT T1 of the lower cell driving circuit 250 and the third switching TFT T3 of the control circuit 224 are driven by the scan pulse SP supplied to the i-th gate line GLi. Is turned on. As the first switching TFT T1 of the lower cell driving circuit 250 is turned on, the first switching TFT T1 of the lower cell driving circuit 250 is turned on. The first switching TFT T1 of the lower cell driving circuit 250 is turned on so that the video signal from the data line DL is supplied on the first node N1 via the first switching TFT T1. . The video signal supplied on the first node N1 is supplied to the gate terminal of the driving TFT DT of the lower cell driving circuit 250 and via the third switching TFT T3 of the control circuit 224. It is supplied on the second node N2. The driving TFT DT and the mirror TFT MT are turned on by the video signals supplied on the first and second nodes N1 and N2. Accordingly, the driving TFT DT of the lower cell driving circuit 250 adjusts the current flowing from its source terminal (ie, VDD) to the drain terminal according to the video signal supplied to its gate terminal, thereby causing the light emitting cell OEL. ) To control the light of the brightness corresponding to the video signal to be emitted from each of the light emitting cells OEL connected to the i + 1 th gate line GLi + 1.

At the same time, the mirror TFT MT of the control circuit 224 receives the current supplied from the voltage supply line VDD from the first node of the second node N2, the third switching TFT T3, and the lower cell driving circuit 250. The data line DL is supplied to the data line DL via the node N1 and the first switching TFT T1. Here, since the driving TFT DT and the mirror TFT MT form a current mirror circuit, the same current flows in the driving TFT DT and the mirror TFT MT.

The storage capacitor Cst of the lower cell driving circuit 250 stores the voltage from the voltage supply line VDD so as to correspond to the amount of current flowing to the mirror TFT MT of the control circuit 224. The storage capacitor Cst of the lower cell driving circuit 250 turns on the driving TFT DT of the lower cell driving circuit 250 using the voltage stored therein when the video signal is not supplied, thereby turning on the next frame. The current is supplied to the light emitting cell OEL until the video signal is supplied.

In practice, the EL display device according to the third embodiment of the present invention displays a predetermined image while repeating such a process.

In the EL display device according to the third exemplary embodiment of the present invention, one control circuit 250 is provided between the cell driving circuits 222 adjacent to the upper and lower sides, and the scan pulse supplied to the gate line GL ( According to the SP, the driving TFT DT of the cell driving circuit 222 and the mirror TFT MT of the control circuit 224 are connected in a current mirror to compensate for current. Accordingly, the EL display device according to the third embodiment of the present invention can increase the aperture ratio by reducing the number of TFTs for driving two upper and lower adjacent light emitting cells OEL from eight to seven. In addition, since the EL display device according to the third exemplary embodiment of the present invention drives two light emitting cells OEL adjacent up and down by using two gate lines GL, four conventional horizontal lines are divided into two. Reduction can further increase the aperture ratio. As a result, the EL display device according to the third embodiment of the present invention can further improve the aperture ratio due to the reduction of the number of TFTs and the number of horizontal lines for driving two light emitting cells OEL adjacent to the top and bottom sides. .

Referring to Fig. 13, the EL display device according to the fourth embodiment of the present invention includes the first switching TFT T1 of the cell driving circuit 350, the second switching TFT T2 and the third of the control circuit 324. Except for the connection relationship of the switching TFT T3, it has the same components and connection relationship as the EL display device according to the second embodiment of the present invention shown in FIG. Therefore, in the EL display device according to the fourth embodiment of the present invention, the first switching TFT T1 of the cell driving circuit 350, the second switching TFT T2 and the third switching TFT of the control circuit 324 ( Only the connection relationship of T3) will be described.

In the EL display device according to the third embodiment of the present invention, the source terminal of the first switching TFT T1 of the cell driving circuit 350 is connected to the data line DL, and the gate terminal is the i-th gate line GLi. Is connected to. The drain terminal of the first switching TFT T1 is connected to the gate terminal of the driving TFT DT.

In the EL display device according to the third embodiment of the present invention, in the control circuit 324, the gate terminal of the second switching TFT T2 is connected to the i-th clock signal supply line GMi, and the source terminal is the data line DL. And the third node N3 between the first switching TFT T1. The drain terminal of the second switching TFT T2 is connected to the gate terminal of the mirror TFT MT through the second node N2. A gate node of the third switching TFT T3 is connected to the i + 1 th clock signal supply line GMi + 1, and a source node is connected between the data line DL and the first switching TFT T1. N3). The drain terminal of the third switching TFT T3 is connected to the gate terminal of the mirror TFT MT through the second node N2.

The operation of the PE cells 322 of the EL display device according to the second embodiment of the present invention will be described in detail with reference to the driving waveform shown in FIG.

The second switching TFT T2 of the control circuit 324 is turned on by the second scan pulse SP2 supplied to the i-th clock signal supply line GMi. Since the first scan pulse SP1 is supplied to the i-th gate line GLi while the second switching TFT T2 of the control circuit 324 is turned on, the first switching TFT of the upper cell driving circuit 350 ( T1) is turned on. The first switching TFT T1 of the upper cell driving circuit 350 is turned on so that the video signal from the data line DL is transferred to the first node via the third node N3 and the first switching TFT T1. It is supplied on (N1). Also, the video signal from the data line DL is supplied on the second node N2 via the third node N3 and the second switching TFT T2 of the control circuit 324. The driving TFT DT and the mirror TFT MT are turned on by the video signals supplied on the first and second nodes N1 and N2. Accordingly, the driving TFT DT of the upper cell driving circuit 350 adjusts the current flowing from its source terminal (ie, VDD) to the drain terminal according to the video signal supplied to its gate terminal, thereby emitting the light emitting cell OEL. ) To control the light of the brightness corresponding to the video signal to be emitted from each of the light emitting cells OEL connected to the i-th gate line GLi.

At the same time, the mirror TFT MT of the control circuit 324 receives the current supplied from the voltage supply line VDD via the second node N2, the second switching TFT T2, and the third node N3. Supply to the line DL. Here, since the driving TFT DT and the mirror TFT MT form a current mirror circuit, the same current flows in the driving TFT DT and the mirror TFT MT.

The storage capacitor Cst of the upper cell driving circuit 350 stores the voltage from the voltage supply line VDD so as to correspond to the amount of current flowing to the mirror TFT MT of the control circuit 324. The storage capacitor Cst of the upper cell driving circuit 350 turns on the driving TFT DT of the upper cell driving circuit 350 using the voltage stored therein when the video signal is not supplied, thereby turning on the next frame. The current is supplied to the light emitting cell OEL until the video signal is supplied.

Thereafter, the second scan pulse SP2 supplied to the i-th clock signal supply line GMi is turned off, and the second scan pulse SP2 is supplied to the i + 1 th clock signal supply line GMi + 1. Accordingly, the third switching TFT T3 of the control circuit 324 is turned on by the second scan pulse SP2 supplied to the i + 1 th clock signal supply line GMi + 1. The first scan pulse SP1 is supplied to the i + 1 th gate line GLi + 1 while the third switching TFT T3 of the control circuit 324 is turned on, thereby providing the first voltage of the lower cell driving circuit 350. 1 switching TFT T1 is turned on. The first switching TFT T1 of the lower cell driving circuit 350 is turned on so that the video signal from the data line DL is transferred to the first node via the third node N3 and the first switching TFT T1. It is supplied on (N1). In addition, the video signal from the data line DL is supplied on the second node N2 via the third node N3 and the third switching TFT T3 of the control circuit 324. The driving TFT DT and the mirror TFT MT are turned on by the video signals supplied on the first and second nodes N1 and N2. Accordingly, the driving TFT DT of the lower cell driving circuit 350 adjusts the current flowing from its source terminal (ie, VDD) to the drain terminal according to the video signal supplied to its gate terminal, thereby emitting the light emitting cell OEL. ) To control the light of the brightness corresponding to the video signal to be emitted from each of the light emitting cells OEL connected to the i + 1 th gate line GLi + 1.

At the same time, the mirror TFT MT of the control circuit 324 receives the current supplied from the voltage supply line VDD via the second node N2, the third switching TFT T3, and the third node N3. Supply to the line DL. Here, since the driving TFT DT and the mirror TFT MT form a current mirror circuit, the same current flows in the driving TFT DT and the mirror TFT MT.

On the other hand, the storage capacitor Cst of the lower cell driving circuit 350 stores the voltage from the voltage supply line VDD so as to correspond to the amount of current flowing to the mirror TFT MT of the control circuit 324. The storage capacitor Cst of the lower cell driving circuit 350 turns on the driving TFT DT of the lower cell driving circuit 350 by using the voltage stored therein when the video signal is not supplied, thereby turning on the next frame. The current is supplied to the light emitting cell OEL until the video signal is supplied.

In fact, the EL display device according to the fourth embodiment of the present invention displays a predetermined image while repeating such a process.

In the EL display device according to the fourth exemplary embodiment of the present invention, one control circuit 350 is provided between upper and lower adjacent cell driving circuits 322 and a second scan supplied to the control circuit 350 is provided. In response to the pulse SP2, the driving TFT DT of the cell driving circuit 322 and the mirror TFT MT of the control circuit 324 are connected in the form of a current mirror to compensate for the current. Accordingly, the EL display device according to the fourth embodiment of the present invention can increase the aperture ratio by reducing the number of TFTs for driving two light emitting cells OEL adjacent to the upper and lower sides from the conventional eight to seven.

Referring to FIG. 14, the EL display device according to the fifth embodiment of the present invention is deleted from the clock signal supply line GM in the EL display device according to the fourth embodiment of the present invention shown in FIG. 13. Will have the same components. In other words, the EL display device according to the fourth embodiment of the present invention is identical to the EL display device according to the fourth embodiment of the present invention except for the connection relationship between the second and third switching TFTs T2 and T3. It has a configuration and connection relationship. Therefore, in the EL display device according to the fifth embodiment of the present invention, only the connection relationship between the second and third switching TFTs T2 and T3 is described, and then the same reference numerals as those of the EL display device according to the fourth embodiment of the present invention. The operation of the PE cell 322 will be described with reference to FIG.

In the EL display device according to the fourth embodiment of the present invention, the gate terminal of the second switching TFT (T2) is connected to the i-th gate line GLi, and the gate terminal of the third switching TFT (T3) is i + 1th. It is connected to the gate line GLi + 1. Accordingly, the second switching TFT T2 is simultaneously turned on or turned on to the first switching TFT T1 of the upper cell driving circuit 350 by the scan pulse SP supplied to the i-th gate line GLi. -Off. The third switching TFT T3 is simultaneously turned on to the first switching TFT T1 of the lower cell driving circuit 350 by the scan pulse SP supplied to the i + 1 th gate line GLi + 1. On or off.

The operation of the PE cells 322 of the EL display device according to the fifth embodiment of the present invention will be described in detail with reference to the driving waveform shown in FIG.

The first switching TFT T1 of the upper cell driving circuit 350 and the second switching TFT T2 of the control circuit 224 are turned on by the scan pulse SP supplied to the i-th gate line GLi. do. As the first switching TFT T1 of the upper cell driving circuit 350 is turned on, the driving TFT DT of the upper cell driving circuit 350 is turned on. As the driving TFT DT of the upper cell driving circuit 350 is turned on, the video signal from the data line DL is transferred to the first node N1 via the third node N3 and the first switching TFT T1. ) And at the same time is supplied to the second node (N2) via the third node (N3) and the second switching TFT (T2). The driving TFT DT and the mirror TFT MT of the upper cell driving circuit 350 are turned on by the video signals supplied on the first and second nodes N1 and N2. Accordingly, the driving TFT DT of the upper cell driving circuit 350 adjusts the current flowing from its source terminal (ie, VDD) to the drain terminal according to the video signal supplied to its gate terminal, thereby emitting the light emitting cell OEL. ) To control the light of the brightness corresponding to the video signal to be emitted from each of the light emitting cells OEL connected to the i-th gate line GLi.

At the same time, the mirror TFT MT of the control circuit 324 receives the current supplied from the voltage supply line VDD via the second node N2, the second switching TFT T2, and the third node N3. Supply to the data line DL. Here, since the driving TFT DT and the mirror TFT MT form a current mirror circuit, the same current flows in the driving TFT DT and the mirror TFT MT.

The storage capacitor Cst of the upper cell driving circuit 350 stores the voltage from the voltage supply line VDD so as to correspond to the amount of current flowing to the mirror TFT MT of the control circuit 324. The storage capacitor Cst of the upper cell driving circuit 350 turns on the driving TFT DT of the upper cell driving circuit 350 using the voltage stored therein when the video signal is not supplied, thereby turning on the next frame. The current is supplied to the light emitting cell OEL until the video signal is supplied.

Thereafter, the scan pulse SP supplied to the i-th gate line GLi is turned off, and the scan pulse SP is supplied to the i + 1 th gate line GLi + 1. Accordingly, the first switching TFT T1 of the lower cell driving circuit 350 and the third switching TFT T3 of the control circuit 324 are driven by the scan pulse SP supplied to the i-th gate line GLi. Is turned on. As the first switching TFT T1 of the lower cell driving circuit 350 is turned on, the driving switching TFT DT of the lower cell driving circuit 350 is turned on. The driving switching TFT DT of the lower cell driving circuit 350 is turned on so that the video signal from the data line DL is supplied on the first node N1 via the first switching TFT T1. As the driving TFT DT of the lower cell driving circuit 350 is turned on, the video signal from the data line DL is transmitted to the first node N1 via the third node N3 and the first switching TFT T1. ) And at the same time is supplied to the second node (N2) via the third node (N3) and the third switching TFT (T3). The driving TFT DT and the mirror TFT MT of the lower cell driving circuit 350 are turned on by the video signals supplied on the first and second nodes N1 and N2. Accordingly, the driving TFT DT of the lower cell driving circuit 350 adjusts the current flowing from its source terminal (ie, VDD) to the drain terminal according to the video signal supplied to its gate terminal, thereby emitting the light emitting cell OEL. ) To control the light of the brightness corresponding to the video signal to be emitted from each of the light emitting cells OEL connected to the i + 1 th gate line GLi + 1.

At the same time, the mirror TFT MT of the control circuit 324 receives the current supplied from the voltage supply line VDD via the second node N2, the third switching TFT T3, and the third node N3. Supply to the line DL. Here, since the driving TFT DT and the mirror TFT MT form a current mirror circuit, the same current flows in the driving TFT DT and the mirror TFT MT.

On the other hand, the storage capacitor Cst of the lower cell driving circuit 350 stores the voltage from the voltage supply line VDD so as to correspond to the amount of current flowing to the mirror TFT MT of the control circuit 324. The storage capacitor Cst of the lower cell driving circuit 350 turns on the driving TFT DT of the lower cell driving circuit 350 by using the voltage stored therein when the video signal is not supplied, thereby turning on the next frame. The current is supplied to the light emitting cell OEL until the video signal is supplied.

In fact, the EL display device according to the fifth embodiment of the present invention displays a predetermined image while repeating such a process.

In the EL display device according to the fifth embodiment of the present invention, one control circuit 350 is provided between upper and lower adjacent cell driving circuits 322 and a scan pulse supplied to the gate line GL ( According to the SP, the driving TFT DT of the cell driving circuit 322 and the mirror TFT MT of the control circuit 324 are connected in the form of a current mirror to compensate for current. Accordingly, the EL display device according to the fifth embodiment of the present invention can increase the aperture ratio by reducing the number of TFTs for driving two light emitting cells OEL adjacent to the top / bottom side from the conventional eight to seven. In addition, since the EL display device according to the fifth embodiment of the present invention drives two light emitting cells OEL adjacent to each other up and down using two gate lines GL, four conventional horizontal lines are divided into two. Reduction can further increase the aperture ratio. As a result, the EL display device according to the fifth embodiment of the present invention can further improve the aperture ratio due to the reduction of the number of TFTs and the number of horizontal lines for driving two light emitting cells OEL adjacent to the top and bottom sides. .

As described above, the electro-luminescence display device according to the embodiment of the present invention is provided with one control circuit between cell driving circuits adjacent to the upper and lower sides, and the upper and lower sides according to the scan pulse supplied to the gate line. The driving TFT of the cell driving circuit and the mirror TFT of the control circuit are connected in the form of a current mirror to compensate for the current. Accordingly, the present invention can increase the aperture ratio by reducing at least one of the number of TFTs for driving two light emitting cells adjacent to the top and the bottom. The present invention can further increase the aperture ratio by reducing at least one of the number of conventional horizontal lines. As a result, the present invention can further improve the aperture ratio due to the reduction in the number of TFTs and the number of horizontal lines for driving two light emitting cells adjacent to each other up and down.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (38)

Electro luminescence cells disposed at each intersection of the gate lines and the data lines, A plurality of cell driving circuits connected to each of the electro luminescence cells to control a current supplied to each of the electro luminescence cells; And a plurality of control circuits shared by the cell driving circuits vertically neighboring and selectively supplying the video signal from each of the data lines to the cell driving circuits vertically neighboring. Ness display. The method of claim 1, A voltage supply line for supplying a driving voltage to the electroluminescent cells; A first gate driver for supplying the gains with a first scan pulse having a turn-on potential for one horizontal period; And a second gate driver for supplying the plurality of control circuits with a second scan pulse having a turn-on potential for two horizontal periods. The method of claim 2, Each of the cell driving circuits, A driving thin film transistor having a source terminal connected to the supply voltage line and a drain terminal connected to the electroluminescent cell; A first switching thin film transistor having a gate terminal connected to a gate line, a source terminal connected to the control circuit, and a drain terminal connected to a gate terminal of a driving thin film transistor; And a storage capacitor connected between the node between the gate terminal of the driving thin film transistor and the drain terminal of the first switching thin film transistor and the supply voltage source. The method of claim 3, wherein Each of the control circuits, A mirror thin film transistor having a source terminal connected to the supply voltage line and a drain terminal connected to a gate terminal thereof; A second switching thin film transistor having a gate terminal connected to a clock signal supply line supplied with the second scan pulse, a source terminal connected between the data lines, and a drain terminal connected to a gate terminal of the mirror thin film transistor; An electroluminescent display device, characterized in that. The method of claim 4, wherein And a source terminal of the first switching thin film transistor is connected to a first node between a drain terminal of the second switching thin film transistor and a gate terminal of the mirror thin film transistor. The method of claim 5, wherein The video signal is supplied to an upper cell driving circuit among the neighboring cell driving circuits in a first section in which the first scan pulse supplied to the i-th gate line and the second scan pulse supplied to the clock signal supply line overlap. An electroluminescent display device, characterized in that. The method of claim 6, In the first period, the video signal from the data line is supplied to the gate terminal of the driving thin film transistor via the second switching thin film transistor, the first node, and the first switching thin film transistor of the upper cell driving circuit. An electroluminescent display device, characterized in that. The method of claim 5, wherein The video signal is applied to a lower cell driving circuit among the neighboring cell driving circuits in a second section in which the first scan pulse supplied to the i + 1th gate line and the second scan pulse supplied to the clock signal supply line overlap. An electroluminescent display device, characterized in that it is supplied. The method of claim 8, The video signal from the data line is supplied to the gate terminal of the driving thin film transistor through the second switching thin film transistor, the first node, and the first switching thin film transistor of the lower cell driving circuit in the second section. An electroluminescent display device, characterized in that. The method of claim 5, wherein The mirror thin film transistor forms a current mirror with the driving thin film transistor to supply a current corresponding to the video signal from the voltage supply line to the data line via the second switching thin film transistor. Ness display. The method of claim 2, And the second scan pulse is supplied before the first scan pulse for a predetermined period of time. The method of claim 2, And the first and second gate drivers are integrated into one chip. Electro luminescence cells disposed at each intersection of the gate lines and the data lines, A voltage supply line for supplying a driving voltage to the electroluminescent cells; A plurality of cell driving circuits connected to each of the electro luminescence cells and supplying a current corresponding to the video signal from the data line to the electro luminescence cell from the voltage supply line; A plurality of control circuits selectively supplied from the voltage supply line to the data line, the current corresponding to the video signal shared by the cell driving circuits vertically neighboring and supplied to each of the cell driving circuits neighboring up and down; And an electroluminescent display device. The method of claim 13, Each of the cell driving circuits, A driving thin film transistor having a source terminal connected to the supply voltage line and a drain terminal connected to the electroluminescent cell; A first switching thin film transistor having a gate terminal connected to a gate line, a source terminal connected to the data line, and a drain terminal connected to a gate terminal of a driving thin film transistor; And a storage capacitor connected between the first node between the gate terminal of the driving thin film transistor and the drain terminal of the first switching thin film transistor and the supply voltage source. The method of claim 14, A first gate driver for supplying a first scan pulse having a turn-on potential to the gate lines for one horizontal period; And a second gate driver for supplying a second scan pulse having a turn-on potential to the plurality of control circuits for one horizontal period. The method of claim 15, Each of the control circuits, A mirror thin film transistor having a source terminal connected to the supply voltage line and a drain terminal connected to a gate terminal thereof; A gate terminal is connected to an i-th (where i is a natural number) clock signal supply line to which the second scan pulse is supplied, and a source terminal is connected to the first node of an upper cell driving circuit among the neighboring cell driving circuits. A second switching thin film transistor having a drain terminal connected to a gate terminal of the mirror thin film transistor; A gate terminal is connected to an i + 1 th clock signal supply line, a source terminal is connected to the first node of a lower cell driving circuit among the neighboring cell driving circuits, and a drain terminal is connected to a gate terminal of the mirror thin film transistor. And a third switching thin film transistor. The method of claim 16, The mirror thin film transistor includes an upper cell driving circuit among the neighboring cell driving circuits in a first section in which the first scan pulse supplied to the i-th gate line and the second scan pulse supplied to the i-th clock signal supply line overlap each other. And a current corresponding to the video signal supplied to the data line from the supply voltage line to the data line. The method of claim 17, The current corresponding to the video signal in the first section is supplied to the data line via the second switching thin film transistor, the first node of the upper cell driving circuit and the first switching thin film transistor. -Luminescence display. The method of claim 16, The mirror thin film transistor may include one of the neighboring cell driving circuits in a second section in which the first scan pulse supplied to the i + 1 th gate line and the second scan pulse supplied to the i + 1 th clock signal supply line overlap each other. And a current corresponding to the video signal supplied to the lower cell driving circuit from the supply voltage line to the data line. The method of claim 19, The current corresponding to the video signal in the second section is supplied to the data line via the third switching thin film transistor, the first node of the lower cell driving circuit and the first switching thin film transistor. -Luminescence display. The method of claim 15, And the second scan pulse is supplied before the first scan pulse for a predetermined period of time. The method of claim 15, And the first and second gate drivers are integrated into one chip. The method of claim 14, And a gate driver for sequentially supplying scan pulses having a turn-on potential to the gate lines for one horizontal period. The method of claim 23, Each of the control circuits, A mirror thin film transistor having a source terminal connected to the supply voltage line and a drain terminal connected to a gate terminal thereof; A second switching circuit having a gate terminal connected to the i-th gate line, a source terminal connected to the first node of an upper cell driving circuit among the neighboring cell driving circuits, and a drain terminal connected to a gate terminal of the mirror thin film transistor; A thin film transistor, A gate terminal connected to the i + 1 th gate line, a source terminal connected to the first node of a lower cell driving circuit among the neighboring cell driving circuits, and a drain terminal connected to a gate terminal of the mirror thin film transistor; An electroluminescent display device comprising three switching thin film transistors. The method of claim 24, The mirror thin film transistor is configured to receive a current corresponding to the video signal supplied to an upper cell driving circuit among the neighboring cell driving circuits in a first section in which the scan pulse is supplied to the i-th gate line from the supply voltage line. An electro-luminescence display characterized by being supplied to a data line. The method of claim 25, The current corresponding to the video signal in the first section is supplied to the data line via the second switching thin film transistor, the first node of the upper cell driving circuit and the first switching thin film transistor. -Luminescence display. The method of claim 24, The mirror thin film transistor receives a current corresponding to the video signal supplied to a lower cell driving circuit among the neighboring cell driving circuits in a second section in which the scan pulse is supplied to the i + 1th gate line from the supply voltage line. And an electro-luminescence display device for supplying the data line. The method of claim 27, The current corresponding to the video signal in the second section is supplied to the data line via the third switching thin film transistor, the first node of the lower cell driving circuit and the first switching thin film transistor. -Luminescence display. The method of claim 15, Each of the control circuits, A mirror thin film transistor having a source terminal connected to the supply voltage line and a drain terminal connected to a gate terminal thereof; A gate terminal is connected to an i-th clock signal supply line to which the second scan pulse is supplied, and a source terminal is connected to a second node between the first switching thin film transistor of an upper cell driving circuit and the data line among the neighboring cell driving circuits. A second switching thin film transistor connected to the drain terminal and connected to a gate terminal of the mirror thin film transistor; A gate terminal is connected to the i + 1 th clock signal supply line, and a source terminal is connected to a second node between the first switching thin film transistor of the lower cell driving circuit and the data line among the neighboring cell driving circuits; And a third switching thin film transistor having a drain terminal connected to a gate terminal of the thin film transistor. The method of claim 29, The mirror thin film transistor includes an upper cell driving circuit among the neighboring cell driving circuits in a first section in which the first scan pulse supplied to the i-th gate line and the second scan pulse supplied to the i-th clock signal supply line overlap each other. And a current corresponding to the video signal supplied to the furnace from the supply voltage line to the data line. The method of claim 20, In the first period, the current corresponding to the video signal is supplied to the data line via the second switching thin film transistor and the second node of the upper cell driving circuit. . The method of claim 29, The mirror thin film transistor may include the neighboring cell driving circuit in a second section in which the first scan pulse supplied to the i + 1 th gate line and the second scan pulse supplied to the i + 1 th clock signal supply line overlap each other. And a current corresponding to the video signal supplied to the lower cell driving circuit from the supply voltage line to the data line. The method of claim 32, In the second period, the current corresponding to the video signal is supplied to the data line via the second node of the third switching thin film transistor and the lower cell driving circuit. . The method of claim 23, Each of the control circuits, A mirror thin film transistor having a source terminal connected to the supply voltage line and a drain terminal connected to a gate terminal thereof; A gate terminal is connected to the i-th gate line, and a source terminal is connected to a second node between the first switching thin film transistor of the upper cell driving circuit and the data line among the neighboring cell driving circuits, and the gate of the mirror thin film transistor. A second switching thin film transistor having a drain terminal connected to the terminal; A gate terminal is connected to the i + 1 th gate line, a source terminal is connected to a second node between the first switching thin film transistor of the lower cell driving circuit and the data line among the neighboring cell driving circuits, and the mirror thin film transistor. And a third switching thin film transistor having a drain terminal connected to the gate terminal of the electroluminescent display device. The method of claim 34, wherein The mirror thin film transistor is configured to receive a current corresponding to the video signal supplied to an upper cell driving circuit among the neighboring cell driving circuits in a first section in which the scan pulse is supplied to the i-th gate line from the supply voltage line. An electro-luminescence display device, characterized in that being supplied in a line. 36. The method of claim 35 wherein In the first period, the current corresponding to the video signal is supplied to the data line via the second switching thin film transistor and the second node of the upper cell driving circuit. . The method of claim 34, wherein The mirror thin film transistor receives a current corresponding to the video signal supplied to a lower cell driving circuit among the neighboring cell driving circuits in a second section in which the scan pulse is supplied to the i + 1th gate line from the supply voltage line. And an electro-luminescence display device for supplying the data line. The method of claim 37, In the second period, the current corresponding to the video signal is supplied to the data line via the second node of the third switching thin film transistor and the lower cell driving circuit. .

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