KR100563735B1 - Method for forming charge storage electrode of semiconductor device - Google Patents

Abstract

The present invention relates to a method of forming a charge storage electrode of a semiconductor device, wherein a portion to be connected to a junction of a silicon substrate is formed of dope amorphous silicon, and a portion to be used as a cylinder wall is formed of undoped amorphous silicon to form silicon when forming a hemispherical polycrystalline silicon. By optimizing the movement of (Si) atoms, it is possible to form hemispherical polycrystalline silicon having uniform grains, thereby maximizing the effective surface area of the charge storage electrode and manufacturing a highly integrated semiconductor memory device having sufficient capacitance using the same. The present invention relates to a method for forming a charge storage electrode of a semiconductor device.

Charge storage electrode, hemispherical polycrystalline silicon

Description

Method of forming a charge storage electrode of a semiconductor device {Method of forming a storage node in a semiconductor device}             

1A to 1D are sectional views of elements for explaining the first embodiment of the present invention.

Figure 2 is a graph for explaining the present invention.

3A to 3C are sectional views of elements for explaining the second embodiment of the present invention.

4A to 4F are sectional views of elements for explaining the third embodiment of the present invention.

<Description of the reference numerals for the main parts of the drawings>

1, 11 and 21: silicon 2, 12 and 22: junction

3 and 13: insulating films 4 and 25: silicon layer

5 and 26: oxide film 6: second silicon spacer

7, 16 and 27: hemispherical polycrystalline silicon

14 and 15: first and second silicon layers

23: first insulating film 24: second insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a charge storage electrode of a semiconductor device, and more particularly, to a method of forming a charge storage electrode of a semiconductor device whose surface is made of hemi-spherical grain-grown silicon.

In general, the degree of integration of semiconductor memory devices, such as DRAM,

Accordingly, the area occupied by memory cells is rapidly reduced. However, a certain amount of capacitance per unit memory cell must be secured for the operation of the device, so that the development of advanced process technologies and devices to minimize the area occupied by the capacitor while maintaining the capacitance required for the operation of the memory cell remain unchanged. It is a big problem to secure reliability.

In order to solve this problem, efforts are being made to increase the effective surface area or to develop dielectrics having improved dielectric properties by forming a charge storage electrode of a capacitor in a three-dimensional structure. As a result of these efforts, materials with high dielectric properties such as Ta ₂ O ₅ and BST have been developed.

It is difficult to apply. Therefore, much research has been made toward maximizing the effective surface area of the charge storage electrode.

Recently, a method of forming a silicon (Si) seed on an amorphous silicon film and heat-treating it in a high vacuum state to selectively form hemispherical polycrystalline silicon (HSG) has been developed. It is applied to a manufacturing process.

Such hemispherical polycrystalline silicon has a surface area determined by its geometric characteristics such as grain size and density, and its geometric characteristics are sensitive to the concentration of the dopant contained in the amorphous silicon thin film on which the hemispherical polycrystalline silicon is to be formed. Is changed.

Thus, when manufacturing a cylinder-type charge storage electrode, amorphous silicon of a portion to be connected to a junction of a silicon substrate and amorphous silicon of a portion to be used as a cylinder wall are formed in-situ. The concentration of phosphorus (P) which is a dopant is adjusted to be 1E20 atoms / cc or less. In this case, however, phosphorus (P) used as a dopant

Since it acts as a diffusion barrier in the process of surface diffusion of self-silicon (Si), the movement of silicon (Si) dn atoms is not induced to an optimal state, resulting in uneven grain size of the hemispherical polycrystalline silicon and the effective surface area of the charge storage electrode. Maximization becomes difficult In addition, the process margin is reduced when the conventional method is applied, and an increase in the production cost by using expensive PH ₃ gas is caused.

Therefore, in the present invention, the portion connected to the junction of the silicon substrate is formed of dope amorphous silicon, and the portion to be used as the cylinder wall is formed of undoped amorphous silicon so that the movement of silicon atoms in the formation of hemispherical polycrystalline silicon is optimized. It is an object of the present invention to provide a method for forming a charge storage electrode of a semiconductor device that can solve the above disadvantages.

According to an aspect of the present invention, there is provided a method of forming a charge storage electrode of a semiconductor device, by forming an insulating film on a silicon substrate yarn having a junction and then forming a contact hole by patterning the insulating layer to expose the junction. Forming a silicon layer on the entire upper surface to be buried, forming an oxide film on the silicon layer from the step, and subsequently patterning the oxide film and the silicon layer using a mask for a charge storage electrode; Forming a silicon spacer on the sidewalls of the silicon layer and the oxide film patterned therefrom, and then removing the oxide film; and removing a natural oxide film grown on the surface from the step, and then depositing a silicon seed on the surface of the silicon layer and the silicon spacer. Forming and heat treating the surface of the silicon layer and the silicon spacer Characterized in that it comprises the step of forming a hemispherical polycrystalline silicon, the method of forming a charge storage electrode of another semiconductor device according to the present invention after forming an insulating film on a silicon substrate formed with a junction portion patterning the insulating layer so that the junction portion is exposed Forming a contact hole and forming a first silicon layer on the entire upper surface so that the contact hole is filled; and forming a second silicon layer on the first silicon layer from the step, and then using a mask for a charge storage electrode. Sequentially patterning the second silicon layer and the first silicon layer, removing the natural oxide film grown on the surface from the step, and then forming a silicon seed on the exposed surfaces of the first and second silicon layers and performing heat treatment. To form hemispherical polycrystalline silicon on the exposed surfaces of the first and second silicon layers. It is characterized by comprising the steps: In addition, according to another embodiment of the present invention, a method of forming a charge storage electrode of a semiconductor device includes forming a contact hole by forming a first insulating film on a silicon substrate on which a junction is formed, and then patterning the first insulating layer to expose the junction. Forming a second insulating film on the entire upper surface such that the contact hole is filled; removing the second insulating film in the portion where the charge storage electrode is to be formed using the mask for the charge storage electrode from the step; Forming a silicon layer on the entire upper surface such that the contact hole is buried, and then forming an oxide film on the silicon layer, and etching the oxide film from the step to the time point at which the silicon layer is exposed, and then Etching the silicon layer, and sequentially removing the second insulating film and the oxide film remaining from the step Characterized in that after removing the natural oxide film grown on the surface from the phase comprising the steps of: to form a silicon oxide on the surface of the silicon layer, and heat-treating the semi-spherical polycrystalline silicon formed on the surface of the silicon layer.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1A to 1D are cross-sectional views of devices for describing the first embodiment of the present invention, which will be described below with reference to FIG. 2.

1A illustrates that after forming the insulating film 3 on the silicon substrate 1 on which the junction part 2 is formed, the insulating film 3 is patterned to expose the junction part 2 to form a contact hole, and the contact hole is buried. The insulating layer 3 is a cross-sectional view of the silicon layer 4 formed on the entire upper surface thereof, and the insulating film 3 may be a dope or thermal oxidized oxide (SiO ₂ ), or a high temperature oxide film (BPSG, BSG, PSG, etc.). And an undoped oxide film such as HTO). In addition, the silicon layer 4 is formed of doped amorphous silicon, the dope amorphous silicon is SiH ₄ or Si ₂ H ₆ as the silicon source gas at a temperature of 300 to 530 ℃, N as the dopant gas ₂ , He is deposited using a PH ₃ diluted in an inert gas such as He, or a PH ₃ gas diluted in a silicon source gas.

FIG. 1B is a cross-sectional view of a state in which the oxide film 5 and the silicon layer 4 are sequentially patterned by a photolithography and an etching process using the mask for charge storage electrodes after the oxide film 5 is formed on the silicon layer 4. As a result, the thickness of the oxide film 5 is adjusted according to the height of the charge storage electrode to be formed.

FIG. 1C is a cross-sectional view illustrating a cylindrical charge storage electrode formed by forming a silicon spacer 6 on sidewalls of the patterned silicon layer 4 and the oxide film 5 and then removing the oxide film 5. The silicon spacer 6 is formed of lightly doped amorphous silicon or undoped amorphous silicon having a concentration of phosphorus (P) of 1E15 to 1E19 atoms / cc. Here, the dope amorphous silicon is SiH ₄ or Si ₂ H ₆ as a silicon source gas at a temperature of 300 to 530 ℃, as a dopant gas diluted in PH ₃ or silicon source gas diluted in an inert gas such as N ₂ , He, etc. Deposited using PH ₃ gas. The undoped amorphous silicon is deposited using SiH ₄ or Si ₂ H ₆ as a silicon source gas at a temperature of 300 to 530 ° C.

FIG. 1D illustrates SiH ₄ in a single type or batch type chamber in a vacuum or high vacuum state in which a pressure of 10 ⁻⁴ Torr or less is maintained after removing a native oxide film grown on a surface using an oxide etching solution. Alternatively, a silicon (Si) seed is formed on the surfaces of the silicon layer 4 and the silicon spacer 6 using Si ₂ H ₆ gas as a source gas, and then heat-treated to form the silicon layer 4 and the silicon spacer 6. A cross-sectional view showing a hemispherical polycrystalline silicon (7) formed on the surface of the silicon, wherein the silicon (Si) atoms of the silicon layer (4) and the silicon spacer (6) moves to the surface during the heat treatment, the hemispherical polycrystal around the seed Silicon is formed.

As described above, after the cylindrical charge storage electrode made of hemispherical polycrystalline silicon is formed, the concentration of dopant in the electron storage electrode is decreased or the dopant is not present, thereby causing a decrease in capacitance due to depletion. Therefore, in order to prevent this, thermal doping is performed at a temperature of 600 to 800 ° C. and a PH ₃ gas atmosphere, or an inert gas such as argon (Ar), helium (He), and neon (Ne) may be used. Plasma doping may be performed.

For reference, curve (A) of FIG. 2 shows the capacitance of the electron storage electrode in which the hemispherical polycrystalline silicon is formed on the surface prepared according to the present invention, and curve (B) shows charge storage in which the hemispherical polycrystalline silicon is not formed on the surface. As shown in the graph, the capacitance of the charge storage electrode in which the hemispherical polycrystalline silicon is formed on the surface is not shown. It can be seen that the capacitance increased by about 2.48 times. As described above, even if the wall portion of the cylinder is formed of undoped amorphous silicon, depletion due to PH ₃ doping can be alleviated, and thus sufficient capacitance can be secured.

3A to 3C are cross-sectional views of devices for describing the second embodiment of the present invention.

3A illustrates that after forming the insulating film 13 on the silicon substrate 11 having the junction part 12 formed thereon, the insulating layer 13 is patterned to expose the junction part 12 to form a contact hole, and the contact hole is buried. A cross-sectional view of a state in which the first silicon layer 14 is formed on the entire upper surface thereof, and then the second silicon layer 15 is formed on the first silicon layer 14, wherein the insulating layer 13 is made of BPSG and BSG. , A dope or thermal oxide film (SiO ₂ ) such as PSG, or an undoped oxide film such as high temperature oxide (HTO). In addition, the first silicon layer 14 is formed of in-situ phosphorus (P) dope amorphous silicon, and the dope amorphous silicon is SiH ₄ or Si ₂ H ₆ as a silicon source gas at a temperature of 300 to 530 ° C. The dopant gas is deposited using PH ₃ diluted in an inert gas such as N ₂ or He or PH ₃ diluted in silicon source gas. The second silicon layer 15 is formed of undoped amorphous silicon, and the undoped amorphous silicon is deposited while the supply of the PH ₃ gas is stopped during deposition.

3B is a cross-sectional view of the second silicon layer 15 and the first silicon layer 14 sequentially patterned by a photolithography and an etching process using a mask for a charge storage electrode.

FIG. 3C shows a source of SiH ₄ or Si ₂ H ₆ gas in a single or batch type chamber in a vacuum or high vacuum state in which a pressure of 10 ⁻⁴ Torr or less is maintained after removal of the native oxide film grown on the surface using an oxide etching solution. Using as a gas to form a silicon (Si) seed on the exposed surfaces of the first and second silicon layers 14 and 15 and then heat treatment to expose the exposed surfaces of the first and second silicon layers 14 and 15. A cross-sectional view showing a hemispherical polycrystalline silicon 16 formed on the substrate, wherein silicon (Si) atoms of the first and second silicon layers 14 and 15 move to the surface during the heat treatment, and the hemispherical polycrystal is formed around the seed. Silicon is formed.

As described above, if the dopant concentration in the charge storage electrode is reduced or the dopant is not present after the charge storage electrode is formed of hemispherical polycrystalline silicon, the capacitance may be reduced due to depletion. After the process, thermal doping may be performed at a temperature of 600 to 800 ° C. and a PH ₃ gas atmosphere, or plasma doping may be performed using an inert gas such as argon (Ar), helium (He), or neon (Ne). .

4A to 4F are cross-sectional views of devices for explaining a third embodiment of the present invention.

4A illustrates that after forming the first insulating film 23 on the silicon substrate 21 on which the junction part 22 is formed, patterning the first insulating layer 23 to expose the junction part 22 to form a contact hole. A cross-sectional view of a state in which the second insulating film 24 is formed on the entire upper surface of the contact hole is filled, wherein the first insulating film 23 is a dope or thermal oxide film (SiO ₂ ) such as BPSG, BSG, PSG, or a high temperature oxide film. The second insulating film 24 is formed of a material that is easily patterned, such as a dope oxide film doped with boron (B) or phosphorus (P), and the thickness thereof. The charge storage electrode to be made is the same height.

4B is a cross-sectional view of a state in which the second insulating layer is removed from a portion where the charge storage electrode is to be formed by a photolithography and an etching process using a mask for the charge storage electrode.

In FIG. 4C, after the silicon layer 25 is formed on the entire upper surface of the contact hole, the oxide layer 26 is formed on the silicon layer 25 and the oxide layer is exposed until the silicon layer 25 is exposed. A cross-sectional view of the back portion 26 etched back, wherein the oxide film remains only at a portion where the charge storage electrode is formed on the contact hole. The silicon layer 25 is formed of lightly doped amorphous silicon or undoped amorphous silicon having a concentration of phosphorus (P) of 1E15 to 1E19 atoms / cc, wherein the dope amorphous silicon is formed at a temperature of 300 to 530 ° C. silicon source gas, and using SiH ₄ or Si ₂ H _6, the dopant gas is N _2, the undoped deposited, using a PH ₃ gas diluted to a PH ₃ or the silicon-source gas diluted with the same inert gas as a He Amorphous silicon is deposited using SiH ₄ or Si ₂ H ₆ as a silicon source gas at a temperature of 300 to 530 ° C. The oxide film 26 is formed of a chemical vapor deposition (CVD) oxide film.

FIG. 4D is a cross-sectional view of the exposed portion of the silicon layer 25, and FIG. 4E is a cross-sectional view of a state in which the remaining second insulating film 24 and the oxide film 26 are sequentially removed.

FIG. 4F shows a source of SiH ₄ or Si ₂ H ₆ gas in a single or batch type chamber in a vacuum or high vacuum state in which a pressure of 10 ⁻⁴ Torr or less is maintained after removal of the native oxide film grown on the surface using an oxide etching solution. A cross-sectional view of a state in which silicon (Si) seeds are formed on a surface of the silicon layer 25 and heat treated to form a hemispherical polycrystalline silicon 27 on the surface of the silicon layer 25 by using a gas. The silicon (Si) atoms of the silicon 25 of the silicon layer 25 move to the surface to form hemispherical polycrystalline silicon around the seed.

As described above, after the charge storage electrode is formed of hemispherical polycrystalline silicon, the dopant concentration in the charge storage electrode is decreased or the dopant is not present. After the process, thermal doping may be performed at a temperature of 600 to 800 ° C. and a PH ₃ gas atmosphere, or plasma doping may be performed using an inert gas such as argon (Ar), helium (He), or neon (Ne).

As described above, according to the present invention, the portion connected to the junction of the silicon substrate is formed of dope amorphous silicon, and the portion to be used as the cylinder wall is formed of undoped amorphous silicon, so that the movement of silicon (Si) atoms in forming hemispherical polycrystalline silicon is prevented. The optimization allows the formation of hemispherical polycrystalline silicon with uniform grains. Therefore, the charge storage electrode can maximize the effective surface area, and can be used to manufacture a highly integrated semiconductor memory device having sufficient capacitance. In addition, the use of the present invention can reduce the production cost by eliminating the use of expensive doping gas, it is possible to obtain an effect that can increase the yield by increasing the process margin.

Claims (26)

Forming an insulating layer on the silicon substrate on which the junction is formed, and then patterning the insulating layer to expose the junction, forming a contact hole, and forming a silicon layer on the entire upper surface to fill the contact hole; Forming an oxide layer on the silicon layer and sequentially patterning the oxide layer and the silicon layer using a mask for a charge storage electrode; Removing the oxide film after forming a silicon spacer on sidewalls of the patterned silicon layer and the oxide film; Removing the natural oxide film grown on the entire structure, and forming a silicon seed on the surface of the silicon layer and the silicon spacer and heat-treating to form hemispherical polycrystalline silicon on the surface of the silicon layer and the silicon spacer; And performing any one of a thermal doping process and a plasma doping process on the entire structure including the hemispherical polycrystalline silicon. The method of claim 1, The insulating film is a method of forming a charge storage electrode of a semiconductor device, characterized in that consisting of any one of BPSG, BSG, PSG, thermal oxide film and high temperature oxide film. The method of claim 1, And the silicon layer is formed of dope amorphous silicon. The method of claim 3, wherein The dope amorphous silicon is deposited at a temperature of 300 to 530 ° C., and any one of SiH ₄ and Si ₂ H ₆ is used as the silicon source gas, and PH ₃ and silicon source diluted in an inert gas are used as the dopant gas. Method for forming a charge storage electrode of a semiconductor device, characterized in that any one of the PH ₃ diluted in the gas is used. The method of claim 1, And the silicon spacer is formed of any one of dope amorphous silicon and undoped amorphous silicon. The method of claim 5, wherein The dope amorphous silicon is deposited at a temperature of 300 to 530 ° C., any one of SiH ₄ and Si ₂ H ₆ is used as the silicon source gas, and PH ₃ and silicon source diluted in an inert gas are used as the dopant gas. A method of forming a charge storage electrode of a semiconductor device, wherein any one of PH ₃ diluted in the gas is used, and the doping concentration is 1E15 to 1E19 atoms / cc. The method of claim 5, wherein The undoped amorphous silicon is deposited at a temperature of 300 to 530 ℃, the silicon source gas during deposition, any one of SiH ₄ and Si ₂ H ₆ gas is formed in the charge storage electrode forming method of the semiconductor device. The method of claim 1, The source gas used to form the silicon seed is any one of SiH ₄ and Si ₂ H ₆ gas, the method of forming a charge storage electrode of a semiconductor device. delete The method of claim 1, The thermal doping process is carried out in a temperature of 600 to 800 ℃ and a PH ₃ gas atmosphere, the plasma doping process is performed using an inert gas, the charge storage electrode forming method of a semiconductor device. Forming an insulating layer on the silicon substrate on which the junction is formed, and then patterning the insulating layer to expose the junction, forming a contact hole, and forming a doped silicon layer on the entire upper surface to fill the contact hole; Forming an undoped silicon layer on the doped silicon layer and sequentially patterning the undoped silicon layer and the doped silicon layer using a mask for a charge storage electrode; After removing the natural oxide film grown on the entire structure to form a silicon seed on the exposed surface of the doped and undoped silicon layer and heat treatment to form a hemispherical polycrystalline silicon on the exposed surface of the doped and undoped silicon layer To do that, And performing any one of a thermal doping process and a plasma doping process on the entire structure including the hemispherical polycrystalline silicon. The method of claim 11, The insulating film is a method of forming a charge storage electrode of a semiconductor device, characterized in that consisting of any one of BPSG, BSG, PSG, thermal oxide film and high temperature oxide film. The method of claim 11, And the doped silicon layer and the undoped silicon layer are formed in an in-situ process. The method of claim 11, The doped silicon is deposited at a temperature of 300 to 530 ° C., and any one of SiH ₄ and Si ₂ H ₆ is used as the silicon source gas, and PH ₃ and silicon source diluted in an inert gas are used as the dopant gas. Method for forming a charge storage electrode of a semiconductor device, characterized in that formed by using any one of the PH ₃ diluted in the gas. The method of claim 11, The source gas used to form the silicon seed is any one of SiH ₄ and Si ₂ H ₆ gas, the method of forming a charge storage electrode of a semiconductor device. delete The method of claim 11, The thermal doping process is carried out in a temperature of 600 to 800 ℃ and a PH ₃ gas atmosphere, the plasma doping process using a inert gas, characterized in that the charge storage electrode forming method of a semiconductor device. In the method of forming a charge storage electrode of a semiconductor device, Forming a first insulating film on the silicon substrate on which the junction is formed, and then patterning the first insulating film to expose the junction, and forming a contact hole and forming a second insulating film on the entire upper surface of the contact hole to be filled; Removing the second insulating film of the portion where the charge storage electrode is to be formed using the mask for the charge storage electrode from the step; Forming an oxide layer on the silicon layer after forming a silicon layer on the entire upper surface such that the contact hole is filled from the step; Etching back the oxide layer from the step to a time point at which the silicon layer is exposed, and then etching the exposed silicon layer; Sequentially removing the second insulating film and the oxide film remaining from the step; Removing the natural oxide film grown on the surface from the step after forming a silicon seed on the surface of the silicon layer and heat treatment to form a hemispherical polycrystalline silicon on the surface of the silicon layer, characterized in that the charge storage of the semiconductor device Electrode formation method. The method of claim 18, And the first insulating film is made of any one of BPSG, BSG, PSG, thermal oxide film and high temperature oxide film, and the second insulating film is formed of a dope oxide film. The method of claim 18, And the silicon layer is formed of any one of dope amorphous silicon and undoped amorphous silicon. The method of claim 20, The dope amorphous silicon is deposited at a temperature of 300 to 530 ° C., and any one of SiH ₄ and Si ₂ H ₆ is used as the silicon source gas, and PH ₃ and silicon source diluted in an inert gas are used as the dopant gas. A method of forming a charge storage electrode of a semiconductor device, wherein any one of PH ₃ diluted in the gas is used, and the doping concentration is 1E15 to 1E19 atoms / cc. The method of claim 20, The undoped amorphous silicon is deposited at a temperature of 300 to 530 ℃, the silicon source gas during deposition, any one of SiH ₄ and Si ₂ H ₆ gas is formed in the charge storage electrode forming method of the semiconductor device. The method of claim 18, The oxide film is a charge storage electrode forming method of a semiconductor device, characterized in that consisting of a chemical vapor deposition oxide film. The method of claim 18, The source gas used to form the silicon seed is any one of SiH ₄ and Si ₂ H ₆ gas, the method of forming a charge storage electrode of a semiconductor device. The method of claim 18, And performing one of a thermal doping process and a plasma doping process from the forming of the hemispherical polycrystalline silicon. The method of claim 25, The thermal doping process is carried out in a temperature of 600 to 800 ℃ and a PH ₃ gas atmosphere, the plasma doping process is performed using an inert gas, the charge storage electrode forming method of a semiconductor device.

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