KR100577777B1 - Method for forming transfer of TFT LCD - Google Patents
Method for forming transfer of TFT LCD Download PDFInfo
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- KR100577777B1 KR100577777B1 KR1019980045761A KR19980045761A KR100577777B1 KR 100577777 B1 KR100577777 B1 KR 100577777B1 KR 1019980045761 A KR1019980045761 A KR 1019980045761A KR 19980045761 A KR19980045761 A KR 19980045761A KR 100577777 B1 KR100577777 B1 KR 100577777B1
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000010408 film Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 21
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 16
- 239000010409 thin film Substances 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 8
- 238000002161 passivation Methods 0.000 claims abstract description 8
- 239000011521 glass Substances 0.000 claims abstract description 7
- 239000007769 metal material Substances 0.000 claims abstract description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 abstract description 8
- 230000035515 penetration Effects 0.000 description 5
- 239000004020 conductor Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 하부기판과 상부기판을 전기적으로 도통시키기 위한 트랜스퍼 형성방법에 관한 것이다. 본 발명의 박막트랜지스터 액정표시소자의 트랜스퍼 형성방법은, 주변에 트랜스퍼 형성 영역을 갖는 액티브영역에 게이트전극이 형성되고 상기 게이트전극을 덮는 게이트절연막이 전면 도포된 유리기판을 제공하는 단계와, 상기 게이트절연막 상에 비정질실리콘층과 소오스/드레인용 금속층을 차례로 증착하는 단계와, 상기 소오스/드레인용 금속층과 비정질실리콘층을 식각하여 게이트전극 상부에 채널영역과 소오스/드레인전극을 형성해서 박막트랜지스터를 형성함과 동시에 상기 트랜스퍼 형성 영역에 비정질실리콘층을 포함한 소오스/드레인용 금속층 패턴을 형성하는 단계와, 상기 결과물의 전면 상에 보호막을 증착하는 단계와, 상기 보호막을 식각해서 박막트랜지스터의 일부를 노출시킴과 동시에 트랜스퍼 형성 영역에 형성된 소오스/드레인용 금속층 패턴을 노출시키는 단계와, 상기 보호막 상에 화소전극용 ITO 금속층을 증착하는 단계와, 상기 ITO 금속층을 식각해서 액티브영역에 박막트랜지스터와 콘택되는 화소전극을 형성함과 아울러 트랜스퍼 형성 영역에 형성된 소오스/드레인용 금속층 패턴의 상부면 중심부만을 노출시키는 단계와, 상기 상부면 중심부가 노출된 소오스/드레인용 금속층 패턴 상에 전도성 금속 물질을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention relates to a transfer forming method for electrically conducting a lower substrate and an upper substrate. According to another aspect of the present invention, there is provided a method of forming a thin film transistor liquid crystal display device, the method including: providing a glass substrate having a gate electrode formed on an active region having a transfer forming region around the gate electrode and having a gate insulating film covering the gate electrode; Sequentially depositing an amorphous silicon layer and a source / drain metal layer on the insulating layer, and etching the source / drain metal layer and the amorphous silicon layer to form a channel region and a source / drain electrode on the gate electrode to form a thin film transistor. And forming a source / drain metal layer pattern including an amorphous silicon layer in the transfer forming region, depositing a protective film on the entire surface of the resultant, and etching the protective film to expose a portion of the thin film transistor. Source / drain formed in the transfer-forming region at the same time Exposing the metal layer pattern for the metal layer; depositing an ITO metal layer for the pixel electrode on the passivation layer; etching the ITO metal layer to form a pixel electrode in contact with the thin film transistor in an active region; Exposing only a central portion of the upper surface of the source / drain metal layer pattern, and forming a conductive metal material on the exposed source / drain metal layer pattern.
Description
본 발명은 박막트랜지스터 액정표시소자에 관한 것으로, 보다 상세하게는, 하부기판과 상부기판을 전기적으로 도통시키기 위한 트랜스퍼의 형성방법에 관한 것이다.The present invention relates to a thin film transistor liquid crystal display device, and more particularly, to a method of forming a transfer for electrically conducting a lower substrate and an upper substrate.
텔레비젼 및 그래픽 디스플레이 등의 표시 장치에 이용되는 액정표시소자(Liquid Crystal Display; 이하, LCD)는 CRT(Cathode-ray tube)를 대신하여 개발되어져 왔다. 특히, 매트릭스 형태로 배열된 각 화소에 스위칭 소자로서 박막트랜지스터(Thin Film Transistor; 이하, TFT)가 구비되는 TFT LCD는 고속 응답 특성을 갖는 잇점과 높은 화소수에 적합하다는 잇점 때문에 CRT에 필적할만한 표시 화면의 고화질화 및 대형화, 컬러화 등을 실현하는데 크게 기여하고 있다.Liquid crystal displays (hereinafter, LCDs) used in display devices such as televisions and graphic displays have been developed in place of the CRT (Cathode-ray tube). In particular, a TFT LCD having a thin film transistor (TFT) as a switching element in each pixel arranged in a matrix form is comparable to a CRT because of the advantages of having high-speed response characteristics and suitable for high pixel count. It is greatly contributing to realizing high screen quality, large size, and color.
이러한 TFT LCD는 일반적으로 매트릭스 형태로 배열된 각 화소에 박막트랜지스터 및 ITO 금속으로된 화소전극이 형성된 하부기판과, 컬러필터와 상대전극이 형성된 상부기판이 실재에 의해 합착되고, 하부기판과 상부기판 사이에는 액정이 충진되어 있는 것을 그 기본 구성으로 하고 있다.In general, a TFT LCD includes a lower substrate on which a pixel electrode made of a thin film transistor and an ITO metal is formed, and an upper substrate on which a color filter and a counter electrode are formed. The liquid crystal is filled between them as the basic structure.
또한, 상기한 구성으로 이루어지는 TFT LCD는 하부기판과 상부기판간을 전기적으로 도통시키기 위하여, 즉, 균일한 전위차가 형성될 수 있도록 하기 위하여 전도성 물질로된 트랜스퍼(Transfer)를 형성하고 있으며, 도 1에 도시된 바와 같이, 트랜스퍼(30)는 하부기판(10)과 상부기판(20)이 합착되어져 구성되는 액정패널의 좌·우(또는, 상·하)에 여러개가 형성되고 있다.In addition, the TFT LCD having the above-described configuration forms a transfer made of a conductive material in order to electrically conduct the lower substrate and the upper substrate, that is, to form a uniform potential difference. As shown in FIG. 3, the transfer 30 is formed on the left and right (or up and down) of the liquid crystal panel formed by the lower substrate 10 and the upper substrate 20 bonded together.
한편, 상기와 같은 TFT LCD의 하부기판은 통상 7개의 식각마스크, 예를 들어, 당업자들에게 주지되어 있는 바와 같이, 게이트 형성을 위한 제1마스크와, 에치 스톱퍼 형성을 위한 제2마스크, 액티브 레이어 형성을 위한 제3마스크, 화소전극 형성을 위한 제4마스크, 채널영역 형성을 위한 제5마스크, 소오스/드레인전극 형성을 위한 제6마스크, 및 보호막 형성을 위한 제7마스크를 사용하여 제작하고 있는데, 이 경우에는 공정 시간 및 비용이 많이 소비되는 문제점이 있다.On the other hand, the lower substrate of the TFT LCD as described above is usually seven etching masks, for example, as is well known to those skilled in the art, the first mask for forming the gate, the second mask for forming the etch stopper, the active layer It is manufactured by using a third mask for forming, a fourth mask for forming a pixel electrode, a fifth mask for forming a channel region, a sixth mask for forming a source / drain electrode, and a seventh mask for forming a protective film. In this case, there is a problem in that process time and cost are consumed a lot.
따라서, 최근에는 5개의 식각마스크, 예를 들어, 게이트 형성을 위한 제1마스크와, 에치스톱퍼 형성을 위한 제2마스크, 소오스/드레인전극 형성을 위한 제3마스크, 드레인전극을 노출시키는 콘택홀 형성을 위한 제4마스크, 및 화소전극 형성을 위한 제5마스크를 사용하여 하부기판을 제작하고 있으며, 이에 따라, 7개의 식각마스크를 사용하는 공정과는 달리, 탑 레이어로서 ITO 금속층을 형성하고 있다.Therefore, recently, five etching masks, for example, a first mask for forming a gate, a second mask for forming an etch stopper, a third mask for forming a source / drain electrode, and a contact hole for exposing a drain electrode are formed. The lower substrate is manufactured by using a fourth mask for forming the fifth electrode and a fifth mask for forming the pixel electrode. Accordingly, unlike the process using seven etching masks, the ITO metal layer is formed as the top layer.
그런데, 상기와 같이 5개의 식각마스크를 사용하여 TFT LCD의 하부기판을 제작하는 경우에는, 도 2에 도시된 바와 같이, 트랜스퍼(30)를 ITO 금속층(8) 상에 형성하게 되는데, 이때, ITO 금속층(8)과 트랜스퍼(30)간의 접촉 저항이 크기 때문에, 전압 손실에 따른 공통신호의 왜곡 현상이 발생하게 되고, 이러한 현상으로 인하여, 결과적으로는 TFT LCD의 화질 저하가 초래되는 문제점이 있었다.By the way, when manufacturing the lower substrate of the TFT LCD using the five etching masks as described above, as shown in Figure 2, the transfer 30 is formed on the ITO metal layer 8, wherein, ITO Since the contact resistance between the metal layer 8 and the transfer 30 is large, distortion of the common signal occurs due to voltage loss, and as a result, there is a problem in that the image quality of the TFT LCD is deteriorated.
도 2에서 미설명된 도면부호 1은 유리기판, 2는 게이트절연막, 3은 비정질실리콘층, 4는 소오스/드레인용 금속층 패턴, 그리고, 6은 보호막을 각각 나타낸다.In FIG. 2, reference numeral 1 denotes a glass substrate, 2 a gate insulating film, 3 an amorphous silicon layer, 4 a source / drain metal layer pattern, and 6 a protective film.
한편, 이러한 문제를 개선하기 위해, 종래에는 트랜스퍼가 형성될 영역에 증착되어 있는 ITO 금속층을 습식식각 공정으로 제거하기도 하였지만, 이 경우에는 ITO 식각액이 소오스/드레인용 금속층의 측면을 따라 하부로 흘러들어감에 의해 하부 막들이 손상됨으로써 추가적인 결함이 발생하게 되는 또 다른 문제점이 있었다.On the other hand, to solve this problem, conventionally, the ITO metal layer deposited in the region where the transfer is to be formed is removed by a wet etching process, but in this case, the ITO etchant flows downward along the side of the source / drain metal layer. There was another problem that additional defects are generated by damaging the underlying films.
따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로서, 전압 손실에 따른 공통 신호의 왜곡 현상을 방지하기 위해 트랜스퍼 형성 영역에 형성된 ITO 금속층을 제거함에 있어서 ITO 식각액 침투로 인한 하부 막들의 손상을 방지할 수 있는 TFT LCD의 트랜스퍼 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and in order to prevent the distortion of the common signal due to voltage loss, the lower layer due to ITO etchant penetration in removing the ITO metal layer formed in the transfer forming region. It is an object of the present invention to provide a method for forming a transfer of a TFT LCD which can prevent damage of the same.
상기와 같은 목적을 달성하기 위한 본 발명의 TFT LCD의 트랜스퍼 형성방법은, 주변에 트랜스퍼 형성 영역을 갖는 액티브영역에 게이트전극이 형성되고 상기 게이트전극을 덮는 게이트절연막이 전면 도포된 유리기판을 제공하는 단계; 상기 게이트절연막 상에 비정질실리콘층과 소오스/드레인용 금속층을 차례로 증착하는 단계; 상기 소오스/드레인용 금속층과 비정질실리콘층을 식각하여 게이트전극 상부에 채널영역과 소오스/드레인전극을 형성해서 TFT를 형성함과 동시에 상기 트랜스퍼 형성 영역에 비정질실리콘층을 포함한 소오스/드레인용 금속층 패턴을 형성하는 단계; 상기 박막트랜지스터가 형성됨과 아울러 트랜스퍼 형성 영역에 비정질실리콘층을 포함한 소오스/드레인용 금속층 패턴이 형성된 기판 결과물의 전면 상에 보호막을 증착하는 단계; 상기 보호막을 식각해서 TFT의 일부를 노출시킴과 동시에 트랜스퍼 형성 영역에 형성된 소오스/드레인용 금속층 패턴을 노출시키는 단계; 상기 보호막 상에 화소전극용 ITO 금속층을 증착하는 단계; 상기 ITO 금속층을 식각해서 액티브영역에 TFT와 콘택되는 화소전극을 형성함과 아울러 트랜스퍼 형성 영역에 형성된 소오스/드레인용 금속층 패턴의 상부면 중심부만을 노출시키는 단계; 및 상기 상부면 중심부가 노츨된 소오스/드레인용 금속층 패턴 상에 전도성 금속 물질을 형성하는 단계;를 포함하는 것을 특징으로 한다.The transfer forming method of the TFT LCD of the present invention for achieving the above object is to provide a glass substrate having a gate electrode formed on the active region having a transfer forming region in the periphery, the entire surface of the gate insulating film is applied to cover the gate electrode step; Sequentially depositing an amorphous silicon layer and a source / drain metal layer on the gate insulating layer; The source / drain metal layer and the amorphous silicon layer are etched to form a channel region and a source / drain electrode on the gate electrode to form a TFT, and a source / drain metal layer pattern including an amorphous silicon layer in the transfer forming region. Forming; Depositing a passivation layer on the entire surface of the substrate resulting from forming the thin film transistor and forming a source / drain metal layer pattern including an amorphous silicon layer in a transfer forming region; Etching the passivation layer to expose a portion of the TFT and simultaneously exposing a source / drain metal layer pattern formed in a transfer formation region; Depositing an ITO metal layer for a pixel electrode on the passivation layer; Etching the ITO metal layer to form a pixel electrode in contact with the TFT in an active region, and exposing only the center of the upper surface of the source / drain metal layer pattern formed in the transfer formation region; And forming a conductive metal material on the source / drain metal layer pattern in which the center of the upper surface is exposed.
본 발명에 따르면, 트랜스퍼가 형성될 영역에서의 소오스/드레인용 금속층 패턴의 상부면 중심부만을 노출시키도록 ITO 금속층을 제거함으로써 ITO 식각액의 하부로의 침투를 방지할 수 있으며, 이에 따라, ITO 식각액에 의한 하부 막들의 손상을 방지할 수 있다.According to the present invention, by removing the ITO metal layer so as to expose only the center of the upper surface of the source / drain metal layer pattern in the region where the transfer is to be formed, it is possible to prevent the penetration of the ITO etchant into the lower portion of the ITO etchant. Damage to the underlying films can be prevented.
(실시예)(Example)
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명의 실시예에 따른 TFT LCD의 트랜스퍼 형성방법을 설명하기 위한 도면으로서, 이를 설명하면 다음과 같다. 여기서, 도2와 동일한 부분은 동일한 도면부호로 표시한다.3 is a view for explaining a transfer forming method of a TFT LCD according to an embodiment of the present invention. Here, the same parts as in Fig. 2 are denoted by the same reference numerals.
도시된 바와 같이, 주변에 트랜스퍼 형성 영역을 갖는 액티브영역에 게이트전극(도시되지 않음)이 형성되고, 상기 게이트전극이 이후에 형성되는 다른 금속층과 콘택되는 것을 방지하기 위해 상기 게이트전극을 덮는 게이트절연막(2)이 전면상에 도포된 유리기판(1)을 마련한다.As shown, a gate electrode (not shown) is formed in an active region having a transfer forming region around it, and a gate insulating film covering the gate electrode to prevent the gate electrode from coming into contact with another metal layer formed later. (2) is provided with a glass substrate 1 coated on the entire surface.
그다음, 상기 게이트절연막(2) 상에 채널영역 및 소오스/드레인전극을 형성하기 위한 a-Si층(4)과 소오스/드레인용 금속층(4)을 차례로 증착한 후, 소오스/드레인 형성용 마스크를 이용한 포토 공정을 수행하여 상기 소오스/드레인용 금속층과 그 하부의 a-Si층을 식각하여 트랜스퍼가 형성될 영역에 a-Si층(4)을 포함한 소오스/드레인용 금속층 패턴(4)을 형성한다. 여기서, 도시하지는 않았으나, 상기 포토 공정에 의해 액티브영역에서의 게이트전극 상부에는 채널영역과 소오스/드레인 전극이 형성되어 TFT가 형성된다.Next, an a-Si layer 4 and a source / drain metal layer 4 for forming a channel region and a source / drain electrode are sequentially deposited on the gate insulating film 2, and then a source / drain forming mask is deposited. The photo-process is used to etch the source / drain metal layer and the lower a-Si layer to form a source / drain metal layer pattern 4 including an a-Si layer 4 in the region where the transfer is to be formed. . Although not shown, a channel region and a source / drain electrode are formed on the gate electrode in the active region by the photo process to form a TFT.
다음으로, 액티브영역에 형성되어진 TFT를 보호하기 위하여 유리기판(1)의 전면 상에, 예를 들어, 실리콘질화막으로된 보호막(6)을 형성하고, 이어서, 식각 공정을 통해 트랜스퍼가 형성될 부분에 형성되어 있는 보호막 부분을 제거한다. 여기서, 상기 트랜스퍼가 형성될 영역 상의 보호막 부분을 제거하는 식각 공정은 액티브영역에서의 TFT의 드레인전극을 노출시키기 위한 콘택홀 형성시에 식각 공정과함께 수행한다.Next, in order to protect the TFT formed in the active region, a protective film 6 made of, for example, a silicon nitride film is formed on the entire surface of the glass substrate 1, and then the portion where the transfer is to be formed through an etching process. Remove the protective film portion formed in the. Here, the etching process of removing the protective film portion on the region where the transfer is to be formed is performed together with the etching process at the time of forming the contact hole for exposing the drain electrode of the TFT in the active region.
그다음, 상기 보호막(6) 상에 탑 레이어로서 ITO 금속층을 증착한 후, 상기 ITO 금속층을 식각하여 액티브영역에서 노출된 TFT의 드레인전극과 콘택되는 화소전극을 형성함과 아울러 트랜스퍼가 형성될 부분에 증착되어진 ITO 금속층 부분을 제거해서 ITO 금속층 패턴(8a)을 형성한다.Thereafter, an ITO metal layer is deposited on the passivation layer 6 as a top layer, and then the ITO metal layer is etched to form a pixel electrode in contact with the drain electrode of the TFT exposed in the active region, and at the portion where the transfer is to be formed. The deposited ITO metal layer portion is removed to form the ITO metal layer pattern 8a.
이때, 상기 식각 공정은 별도의 마스크를 제작하여 사용하며, 특히, 트랜스퍼가 형성될 영역에 증착되어 있는 ITO 금속층을 전부 제거하지 않는 것이 아니라, 소오스/드레인용 금속층 패턴(4)의 중심부 상에 증착되어 있는 ITO 금속층 부분만을 제거하도록 진행한다.At this time, the etching process is used to produce a separate mask, in particular, not to remove all the ITO metal layer deposited in the region where the transfer is to be formed, is deposited on the center of the source / drain metal layer pattern (4) Proceed to remove only the portion of the ITO metal layer.
이러한 식각 공정은 마스크 제작에 어려움은 있으나, 반면에, 소오스/드레인용 금속층(4)의 상부면 중심부만을 노출시키도록 진행되는 것으로 인해 ITO 금속층의 식각시에 사용되는 식각액이 상기 소오스/드레인용 금속층 패턴(4)의 측면을 따라 하부로 침투되는 현상은 방지되며, 그래서, 하무 막들의 ITO 식각에 의한 손상 발생을 방지할 수 있게 된다.This etching process is difficult to fabricate the mask, on the other hand, the etching liquid used during the etching of the ITO metal layer due to the process proceeds to expose only the center of the upper surface of the source / drain metal layer 4, the source / drain metal layer The phenomenon of infiltration to the lower side along the side of the pattern 4 is prevented, so that the occurrence of damage due to ITO etching of the bottom films can be prevented.
즉, 트랜스퍼가 형성될 영역에 증착되어 있는 ITO 금속층을 전부 식각할 경우에는 종래와 같이 ITO 금속층을 제거하기 위한 식각액이 소오스/드레인용 금속층의 측면을 따라 하부로 침투되어 하부 막들의 측면 부분이 손상되지만, 본 발명에서와 같이 소오스/드레인용 금속층의 상부면 중심부 상에 증착되어 있는 ITO 금속층 부분만을 제거하는 경우에는 하부로의 ITO 식각액의 침투를 차단할 수 있어서 상기 ITO 식각액에 의해 하부 막들의 손상 발생은 거의 없게 된다.That is, in the case where all the ITO metal layers deposited in the region where the transfer is to be formed are etched, the etchant for removing the ITO metal layer is penetrated downward along the side of the source / drain metal layer as in the prior art, thereby damaging the side portions of the lower layers. However, in the case of removing only the portion of the ITO metal layer deposited on the center of the upper surface of the source / drain metal layer as in the present invention, it is possible to block the penetration of the ITO etchant into the lower portion, thereby causing damage to the underlying films by the ITO etchant. Will almost never be.
계속해서, 상기한 식각 공정을 통해 노출되어진 트랜스퍼가 형성될 영역, 바람직하게는, 소오스/드레인용 금속층 패턴(4) 상에 전도성 물질로된 트랜스퍼(30)를 형성한다.Subsequently, a transfer 30 made of a conductive material is formed on the region where the transfer is exposed through the above etching process, preferably, the metal layer pattern 4 for source / drain.
상기와 같은 방법으로 트랜스퍼를 형성할 경우에는, 상기 트랜스퍼가 ITO 금속층이 아닌 전도성이 우수한 소오스/드레인용 금속층 상에 직접 형성되기 때문에, 상기 소오스/드레인용 금속층과 트랜스퍼간의 접촉 저항이 증가되는 것이 방지되고, 이에 따라, 접촉 저항의 증가에 따른 전압 손실을 방지할 수 있게 됨으로써, 결과적으로는, 공통 신호의 왜곡이 방지되어 TFT LCD의 화질 저하를 방지할 수 있게 된다.When the transfer is formed in the above manner, since the transfer is directly formed on the source / drain metal layer having excellent conductivity rather than the ITO metal layer, the contact resistance between the source / drain metal layer and the transfer is prevented from increasing. As a result, the voltage loss caused by the increase in the contact resistance can be prevented, and as a result, the distortion of the common signal can be prevented and the deterioration of the image quality of the TFT LCD can be prevented.
또한, ITO 금속층의 일부분만을 식각 제거함으로써, 상기 ITO 식각액의 침투로 인해 하부 막들이 손상되는 것도 방지할 수 있다.In addition, by etching away only a part of the ITO metal layer, it is possible to prevent the underlying films from being damaged due to penetration of the ITO etchant.
이상에서 설명된 바와 같이, 본 발명은 탑 레이어로서 ITO 금속층을 형성하는 5 마스크 공정을 이용한 TFT LCD의 제조 공정에서, 트랜스퍼 형성 영역 상에 형성된 ITO 금속층의 제거시 소오스/드레인용 금속층 패턴의 중심부 상에 증착되어 있는 ITO 금속층 부분만을 선택적으로 제거해 냄으로써 상기 소오스/드레인용 금속층 패턴의 측면을 통한 ITO 식각액의 하부로의 침투를 방지할 수 있으며, 이에 따라, ITO 식각액에 의한 하부 막들의 손상을 방지할 수 있다.As described above, the present invention provides a method for manufacturing a TFT LCD using a five-mask process for forming an ITO metal layer as a top layer. By selectively removing only the portion of the ITO metal layer deposited on the substrate, it is possible to prevent the penetration of the lower portion of the ITO etchant through the side of the source / drain metal layer pattern, thereby preventing damage to the underlying films by the ITO etchant. Can be.
또한, 본 발명은 이와 같은 방법을 통해 하부기판과 상부기판간을 전기적으로 도통시키기 위한 트랜스퍼를 ITO 금속층이 아닌 소오스/드레인용 금속층 상에 형성되도록 함으로써 접촉 저항의 증가에 의해 전압 손실이 발생되는 것을 방지할 수 있으며, 이에 따라, TFT LCD의 화질 저하를 방지할 수 있는 것에 기인하여 그 신뢰성을 향상시킬 수 있다.In addition, according to the present invention, a voltage loss is caused by an increase in contact resistance by forming a transfer for electrically conducting an electrical connection between the lower substrate and the upper substrate on the source / drain metal layer instead of the ITO metal layer. This can be prevented, and therefore, the reliability thereof can be improved due to being able to prevent the deterioration of the image quality of the TFT LCD.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
도 1은 트랜스퍼가 형성된 액정 패널을 개략적으로 도시한 도면.1 is a view schematically showing a liquid crystal panel on which a transfer is formed.
도 2는 종래 문제점을 설명하기 위한 도 1의 A부분에 대한 상세도.Figure 2 is a detailed view of the portion A of Figure 1 for explaining the conventional problem.
도 3은 본 발명의 실시예에 따른 박막트랜지스터 액정표시소자의 트랜스퍼 형성방법을 설명하기 위한 도면.3 is a view for explaining a transfer forming method of a thin film transistor liquid crystal display device according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
1 : 유리기판 2 : 게이트 절연막1 glass substrate 2 gate insulating film
3 : 비정질실리콘층 4 : 소오스/드레인용 금속층3: amorphous silicon layer 4: source / drain metal layer
6 : 보호막 8a : ITO 금속층6: protective film 8a: ITO metal layer
30 : 트랜스퍼30: transfer
Claims (1)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980045761A KR100577777B1 (en) | 1998-10-29 | 1998-10-29 | Method for forming transfer of TFT LCD |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980045761A KR100577777B1 (en) | 1998-10-29 | 1998-10-29 | Method for forming transfer of TFT LCD |
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| KR20000027744A KR20000027744A (en) | 2000-05-15 |
| KR100577777B1 true KR100577777B1 (en) | 2006-08-18 |
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| KR1019980045761A Expired - Lifetime KR100577777B1 (en) | 1998-10-29 | 1998-10-29 | Method for forming transfer of TFT LCD |
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| KR101303940B1 (en) | 2006-10-16 | 2013-09-05 | 삼성디스플레이 주식회사 | Dispaly panel |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05224225A (en) * | 1992-02-07 | 1993-09-03 | Nippondenso Co Ltd | Liquid crystal display device |
| KR980010561A (en) * | 1996-07-22 | 1998-04-30 | 구자홍 | Liquid crystal display (TFT-LCD) |
| JPH10253992A (en) * | 1997-03-03 | 1998-09-25 | Lg Electron Inc | Liquid crystal display device and method of manufacturing the same |
| JPH10282515A (en) * | 1997-04-08 | 1998-10-23 | Sanyo Electric Co Ltd | Liquid crystal display device |
| KR100229610B1 (en) * | 1996-12-20 | 1999-11-15 | 구자홍 | LCD and its manufacturing method |
-
1998
- 1998-10-29 KR KR1019980045761A patent/KR100577777B1/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05224225A (en) * | 1992-02-07 | 1993-09-03 | Nippondenso Co Ltd | Liquid crystal display device |
| KR980010561A (en) * | 1996-07-22 | 1998-04-30 | 구자홍 | Liquid crystal display (TFT-LCD) |
| KR100229610B1 (en) * | 1996-12-20 | 1999-11-15 | 구자홍 | LCD and its manufacturing method |
| JPH10253992A (en) * | 1997-03-03 | 1998-09-25 | Lg Electron Inc | Liquid crystal display device and method of manufacturing the same |
| JPH10282515A (en) * | 1997-04-08 | 1998-10-23 | Sanyo Electric Co Ltd | Liquid crystal display device |
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| KR20000027744A (en) | 2000-05-15 |
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