KR100596508B1 - Manufacturing method of フ ｉｎＦＥＴ and fin channel - Google Patents

Abstract

The present invention relates to a fin channel and a fin channel manufacturing method of a fin FET including a silicon substrate and a fin channel, a gate insulating film, a gate and a source / drain electrode formed on the silicon substrate, wherein the fin channel is formed on the silicon substrate. It is formed on the inclined SiGe layer, which is a buffer layer to be formed, a relaxed SiGe layer epitaxially grown on the inclined SiGe layer and is patterned in at least one region, and is formed on at least the Fin on the relaxed SiGe layer. A silicon fin including a strained silicon layer or patterned on at least one region of the silicon substrate, a strained SiGe layer epitaxially grown on the silicon fin, and an epitaxial silicon layer on the strained SiGe layer To be configured. Through such a configuration, it is possible to greatly improve the performance of the device than the conventional silicon FinFET.

Nano, Fin, MOSFET, FinFET, Strained Si, Strained SiGe, Gate Insulator

Description

 FinFET and Fabricating Method Of Fin Channel}

1 is a perspective view of a FinFET according to an embodiment of the present invention.

2A to 2N are process charts illustrating a method of manufacturing a FinFET according to an exemplary embodiment of the present invention. The left figure of each drawing is a process chart illustrating a method of manufacturing a FinFET based on the line AA ′ of FIG. 1. The right figure of each figure is a process chart which shows the method of manufacturing a FinFET based on the B-B 'line | wire of FIG.

3 is a perspective view of a FinFET according to another embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

1: Silicon Substrate 2: Inclined SiGe Layer

3: relaxed SiGe layer 4: strained Si layer

5: strained SiGe layer 6: Si layer

10: gate insulating film

20: buffer oxide film 21: nitride film

22: oxide film 30: gate

40: source region 41: drain region

50: buffer oxide film 51: nitride film

60: gate electrode 61: source electrode

62: drain electrode 100: photoresist

The present invention relates to a FinFET and a Fin channel manufacturing method, and more particularly, to a FinFET and a Fin channel manufacturing method that can greatly improve the characteristics of the device by forming a Fin channel having a strained silicon or strained SiGe layer, etc. will be.

Recently, various methods are used to improve the performance and integration of bulk MOSFETs, and one of the methods is to reduce the size of the device. However, when the device size is reduced to improve the performance and integration of the MOSFET, the channel length of the MOSFET is reduced to several tens of nanometers or less, resulting in short channel effects and subthreshold slopes. As the subthreshold slope increases, the leakage current of the device increases, and the operating voltage of the device decreases, thereby reducing the threshold voltage. As a result, the driving current of the device decreases. In addition, when the channel length of the MOSFET is drastically reduced, a method of increasing the channel concentration may be used to suppress the short channel effect of the bulk MOSFET. In this case, the concentration of impurities may be increased to increase the nonuniformity of the impurities. The electrical characteristics of the device may be severely changed.

Accordingly, in order to solve the above problems, FinFET devices having a double gate structure different from MOSFET devices have been developed. FinFETs are more complex to fabricate than bulk MOSFETs, but have the advantage of significantly improving device characteristics.
FinFET can control short effect of device by using fin thickness and channel length without considering the nonuniformity problem due to impurity concentration because fin channel can show shorter channel effect than ratio of impurity injected into channel. can do.

In addition, FinFETs can control channel effects that are shorter than the impurity concentration of the channel, resulting in significantly lower channel region concentrations than MOSFETs, resulting in significantly lower subthreshold slopes than bulk MOSFETs. have. Moreover, FinFETs can lower threshold voltages than bulk MOSFETs, significantly reduce leakage current between the source and drain of the device, and increase drive currents over conventional bulk MOSFETs.

According to the above, the existing FinFET has a number of advantages over the MOSFET, but the development of better FinFET is progressing according to the desire of users and the development effort to obtain a further improved device.

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Accordingly, the present invention has been made to improve the performance of the existing FinFET, an object of the present invention is to provide a FinFET and Fin channel manufacturing method for improving the driving ability of the device by improving the mobility of the carrier (Carrier). .

In addition, another object of the present invention is to provide a FinFET and Fin channel manufacturing method that can improve the characteristics of the device while ensuring compatibility with the existing MOSFET manufacturing process in the manufacture of FinFET.

As a technical means for achieving the above object, the first aspect of the present invention relates to a FinFET comprising a silicon substrate and a fin channel, a gate insulating film, a gate and a source / drain electrode formed on the silicon substrate, The channel is formed on an inclined SiGe layer, which is a buffer layer formed on the silicon substrate, and is epitaxially grown on the inclined SiGe layer and has a relaxed SiGe layer having fins patterned in at least one region, and the relaxed SiGe layer. At least the strained silicon layer formed on the Fin.

A second aspect of the invention relates to a FinFET comprising a silicon substrate, a fin channel formed on the silicon substrate, a gate insulating film, a gate and a source / drain electrode, wherein the fin channel is patterned on at least one region of the silicon substrate. Silicon fin, a strained SiGe layer epitaxially grown on the silicon fin, and an epitaxial silicon layer on the strained SiGe layer.

A third aspect of the present invention relates to a method for manufacturing the Fin channel of the FinFET comprising a Fin channel, a gate insulating film, a gate and a source / drain electrode formed on a silicon substrate, wherein the method for manufacturing the Fin channel is (a) the Epitaxially growing on the silicon substrate to form a gradient SiGe layer that is a buffer layer; (b) epitaxially growing on the SiGe layer to form a relaxed SiGe layer; (c) patterning a region of the relaxed SiGe layer to form SiGe Fin; And (d) epitaxially growing on the SiGe Fin to form a strained silicon layer.

A fourth aspect of the present invention relates to a method of manufacturing the Fin channel of a FinFET comprising a silicon substrate, a fin channel formed on the silicon substrate, a gate insulating film, a gate and a source / drain electrode. (A) patterning at least one region of the silicon substrate on the silicon substrate to form silicon fin; (b) epitaxially growing on the silicon fin to form a strained SiGe layer; (c) epitaxially growing silicon on the strained SiGe layer to surround the strained SiGe layer to form an epitaxial silicon layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following embodiments are provided to those skilled in the art to fully understand the present invention, and may be modified in various forms, and the scope of the present invention is limited to the embodiments described below. It is not.

1 is a perspective view of a FinFET according to an embodiment of the present invention.

Referring to FIG. 1, the FinFET 200 according to an exemplary embodiment of the present invention may include a silicon substrate 1, a fin channel I formed on the silicon substrate 1, a gate insulating layer 10, and a gate electrode 30. ) And source / drain regions 40 and 41.

Specifically, the fin channel I is formed on the silicon substrate 1 to form a gradient inclined SiGe layer 2 serving as a buffer layer, and a relaxed SiGe layer epitaxially grown on the SiGe layer 2. ), And a strained silicon layer 4 formed in one region on the relaxed SiGe layer 3. The thermal oxide film 20, the nitride film 21, and the oxide film 22 are formed on the relaxed SiGe layer 3, and the gate electrode 30 and the source / drain regions 40 and 41 are formed on the oxide film 22. Is formed.
Hereinafter, a method of manufacturing a FinFET according to an exemplary embodiment of FIG. 1 will be described in detail with reference to the accompanying drawings.

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2A to 2N are process charts illustrating a method of manufacturing a Fin FET according to an embodiment of the present invention. The left figure of each figure is a process chart showing a manufacturing method based on line A-A 'of FIG. The right figure of the figure is a process chart which shows the manufacturing method based on the B-B 'line | wire of FIG.

Referring to FIG. 2A, a graded SiGe layer 2 is formed on the silicon substrate 1 into which n-type (or p-type) impurities are introduced. After the inclined SiGe (Si _1-x Ge _x ) layer 2 washes the surface of the silicon substrate 1, the process temperature is 400 ~ 700 ℃, the process pressure is normal pressure (760Torr), low pressure (50 ~ 500mTorr ) And ultra-high vacuum (0.1 ~ 10mTorr) by using the chemical vapor deposition method using the Si and Ge source by increasing the content of Ge gradually from 0% to 15 ~ 35% to grow to 0.1 ~ 2μm thick.
Then, a relaxed SiGe layer 3 is formed on the graded SiGe layer 2, wherein the relaxed SiGe (e.g., Si _0.8 Ge _0.2 ) layer 3 is subjected to the process conditions and process described above. It grows to 0.1-5 micrometer thickness, keeping Ge content constant at 15 to 35% using. After the relaxed SiGe layer 3 is formed, the buffer oxide film 50 having a thickness of 5 to 100 nm is formed, and after forming the first nitride film 51 having a thickness of 10 nm to 300 nm, one region of the first nitride film 51 is formed. After forming a photoresist film, a fin pattern 100 having a width of 5 to 500 nm is formed by a photolithography method using a fin mask.

Referring to FIG. 2B, the first nitride layer 51 and the buffer oxide layer 50 are etched by anisotropic dry etching, and the SiGe layer 3 relaxed by anisotropic dry etching is etched to a depth of 10 to 500 nm. (3a) is formed.

Referring to FIG. 2C, a first oxide film 20 having a thickness of 5 to 100 nm is formed on the entire structure. The first oxide film 20 is formed through a thermal oxidation process by heat treatment in an oxygen atmosphere. After the first oxide film 20 is formed, a second nitride film 21 having a thickness of 10 to 300 nm is formed by chemical vapor deposition. The second oxide film 22 having a thickness of 20 to 1000 nm is deposited on the second nitride film 21 by chemical vapor deposition. In the thermal oxide film process, the exposed silicon region may be formed of a silicon oxide film to generate a structure as illustrated in FIG. 2C.

Referring to FIG. 2D, the second oxide film 22 is planarized to the upper end of the second nitride film 21 using the CMP process. In this case, the first nitride film 21 serves as an etch stopper.

Referring to FIG. 2E, the second oxide layer 22 is etched by wet or dry etching, leaving only the oxide layer having a thickness of about 5 nm or more and removing the remaining oxide layer.

Referring to FIG. 2F, the second nitride film 21 and the first nitride film 51 exposed by the wet etching method are removed. Only the nitride layer may be wet-etched using the selectivity ratio between the nitride layer and the oxide layer.

Referring to FIG. 2G, the first oxide film 20 and the buffer oxide film 50 may be removed by isotropic etching, and if necessary, a process of reducing the width of the SiGe Fin may be performed. 2G illustrates the case where the width of the SiGe Fin is reduced by a predetermined width.

Referring to FIG. 2H, a strained silicon layer 4 is formed by growing a silicon epitaxial layer having a thickness of 1 to 100 nm in the exposed SiGe Fin 3a, which is a region where a channel of the Fin FET is formed. Strained silicon layer (4) after cleaning the surface in Figure 2g after the process temperature is 400 ~ 700 ℃, the process pressure is chemical vapor deposition at normal pressure (760 Torr), low pressure (50 ~ 500 mTorr), ultra-high vacuum (0.1 ~ 10 mTorr), etc. An Si source is epitaxially grown on a relaxed SiGe Fin (3a) with exposed surface using a Si source.

Referring to FIG. 2I, a gate insulating film 10 having a thickness of 0.1 to 100 nm is formed on the strained silicon layer 4, and then polycrystalline silicon 30 ′ is formed and impurities are implanted.

Referring to FIG. 2J, the polysilicon 30 ′ is planarized by a CMP method for a subsequent process.

Referring to FIG. 2K, the photoresist film 100 is formed on the entire structure, and the gate pattern is formed by a photolithography method using a gate mask, and then the polysilicon 30 ′ is etched by anisotropic dry etching to form a gate of the FinFET. The electrode 30 is formed.

Referring to FIG. 2L, the remaining photoresist film 100 is removed.

Referring to FIG. 2M, n-type (As, P, etc.) and p-type (B, BF ₂ , etc.) are formed in the source region 40 and the drain region 41 using a photolithography method using a source / drain mask and an impurity introducer. ) Impurities are introduced into the ion implanter and heat treated to form source and drain electrodes.

Referring to FIG. 2N, after the contact region is defined on the structure by using a contact mask and a photolithography method, the insulating layer 23 is etched to form a portion where a contact is to be formed. Subsequently, the metal is deposited, the wiring portions 60, 61, and 62 are defined by an electrode mask and a photolithography method, and the metal is etched by anisotropic etching to form a source electrode, a gate electrode, and a drain electrode, followed by heat treatment. This process completes the FinFET.

3 is a perspective view of a FinFET according to another embodiment of the present invention. For convenience of explanation, the description will be made based on differences from the manufacturing method of the FinFET of FIG. 1.

In the manufacturing of the FinFET of FIG. 1, the inclined SiGe layer 2 and the relaxed SiGe layer 3 are used in the Fin channel I, while in the manufacturing of the FinFET of FIG. 3, the inclined SiGe layer 2 and the relaxed SiGe are The process of FIGS. 2A-2G is performed using the silicon substrate 1 without using the layer 3. Then, an epitaxially grown strained SiGe (5) layer having a thickness of 1 to 100 nm is epitaxially grown on the formed Si Fin 1a, and an Si layer 6 having a thickness of 0.5 to 50 nm is epitaxially grown again. Subsequent processes go through a process similar to that of FIGS. 2I-2N. Specifically, after the silicon surface is cleaned, the process temperature is 400 ~ 700 ℃ and the process pressure is Si and Ge by chemical vapor deposition at normal pressure (760Torr), low pressure (50 ~ 500mTorr), ultra-high vacuum (0.1 ~ 10mTorr), etc. Strained SiGe layer 5 is grown by growing a 1-100 nm thick SiGe (eg Si _0.8 Ge _0.2 ) layer while maintaining a constant Ge content of 10-40% using a source. After that, the process temperature is 400 ~ 700 ℃ and the process pressure is 0.5 ~ 50nm thick Si layer using only Si source by chemical vapor deposition at normal pressure (760Torr), low pressure (50 ~ 500mTorr), ultra high vacuum (0.1 ~ 10mTorr), etc. 6) This epitaxial growth to complete the strained SiGe Fin.

As mentioned above, although preferred embodiment of this invention was described in detail, this invention is not limited to the said embodiment, A various deformation | transformation by a person of ordinary skill in the art within the scope of the technical idea of this invention is carried out. This is possible.

The strained Si or strained SiGe FinFET fabricated by the present invention as described above has greater carrier mobility in the strained Si or strained SiGe channel region than the conventional Si channel. It can greatly improve performance.

Claims (12)

A FinFET comprising a silicon substrate and a fin channel, a gate insulating film, a gate, and a source / drain electrode formed on the silicon substrate, The fin channel is formed on an inclined SiGe layer, which is a buffer layer formed on the silicon substrate, A relaxed SiGe layer epitaxially grown on the inclined SiGe layer and having at least one patterned Fin; A strained silicon layer formed on at least the Fin on the relaxed SiGe layer FinFET comprising a. The method of claim 1, The strained silicon layer is a FinFET having a thickness of 1 ~ 100nm. A FinFET comprising a silicon substrate, a fin channel formed on the silicon substrate, a gate insulating film, a gate, and a source / drain electrode, The Fin channel, Silicon Fin formed by patterning at least one region on the silicon substrate; A strained SiGe layer epitaxially grown on the patterned silicon Fin; And An epitaxial silicon layer epitaxially grown on the strained SiGe layer FinFET comprising a. The method of claim 4, wherein The strained SiGe layer has a thickness of 1 to 100 nm, and the epitaxial silicon layer has a thickness of 0.5 to 50 nm. The method according to any one of claims 1 to 4, The Fin channel is a FinFET consisting of 5 ~ 500nm width. A method of manufacturing the Fin channel of a FinFET comprising a Fin channel formed on a silicon substrate, a gate insulating film, a gate and a source / drain electrode, (a) epitaxially growing on the silicon substrate to form a gradient SiGe layer as a buffer layer; (b) epitaxially growing on the SiGe layer to form a relaxed SiGe layer; (c) patterning a region of the relaxed SiGe layer to form SiGe Fin; And (d) epitaxially growing on the SiGe Fin to form a strained silicon layer Fin channel manufacturing method of the FinFET comprising a. The method of claim 6, Forming the inclined SiGe layer, Cleaning the surface of the silicon substrate; Step of epitaxially growing to 0.1 ~ 2μm thickness by gradually increasing Ge content from initial 0% to final 15 ~ 35% using Si and Ge sources by chemical vapor deposition at a predetermined pressure and process temperature of 400 ~ 700 ℃. Fin channel manufacturing method of the FinFET further comprising. The method of claim 6, In the step of forming the relaxed SiGe layer Fin channel manufacturing method of the FinFET to grow the relaxed SiGe layer to 0.1 ~ 5μm thickness while maintaining the content of Ge constant 15 to 35%. The method of claim 6, The forming of the strained silicon layer is a Fin channel manufacturing method of a FinFET to epitaxially grow a Si layer of 1 ~ 100nm thickness using a Si source on the SiGe Fin. A method for manufacturing the Fin channel of a FinFET comprising a silicon substrate, a fin channel formed on the silicon substrate, a gate insulating film, a gate and a source / drain electrode, (a) patterning at least one region of the silicon substrate on the silicon substrate to form a silicon fin; (b) epitaxially growing on the silicon fin to form a strained SiGe layer; (c) epitaxially growing silicon on the strained SiGe layer to surround the strained SiGe layer to form an epitaxial silicon layer Fin channel manufacturing method of the FinFET comprising a. The method of claim 10, wherein forming the strained SiGe layer is Method for manufacturing Fin channel of FinFET by growing SiGe layer with thickness of 1-100nm while maintaining Ge content at 10 ~ 40% by using Si and Ge source by chemical vapor deposition. The method of claim 10, Forming the epitaxial silicon layer, Method for producing a Fin channel of the FinFET formed using a Si source by chemical vapor deposition at a predetermined pressure, 400 ~ 700 ℃ temperature.

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