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KR100609647B1 - Method for manufacturing bio seed substrate with unplated pattern by dual image process - Google Patents

Method for manufacturing bio seed substrate with unplated pattern by dual image process Download PDF

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KR100609647B1
KR100609647B1 KR1020040098128A KR20040098128A KR100609647B1 KR 100609647 B1 KR100609647 B1 KR 100609647B1 KR 1020040098128 A KR1020040098128 A KR 1020040098128A KR 20040098128 A KR20040098128 A KR 20040098128A KR 100609647 B1 KR100609647 B1 KR 100609647B1
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nickel
plating
imaging
pattern
conductive layer
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KR20060059030A (en
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유문상
차상석
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주식회사 심텍
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0073—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
    • H05K3/0082—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the exposure method of radiation-sensitive masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

본 발명은 제1이미징 단계, 제1에칭단계, 전도층형성단계, 제2이미징 단계, 제2에칭단계, 제3이미징단계, 니켈/금 도금단계, 제3에칭단계, 솔더레지스트 도포단계, 라우팅 단계로 구성되는 본 출원인의 기 출원된 발명(특허 제2004-0079346호)에 있어서, 상기 제3이미징단계에서 니켈/금도금 될 부분을 외부로 노출시키기 위한 감광성 물질의 이미지 경계면이 전도층을 외부로 노출시키기 위한 드라이필름의 이미지 경계면 바깥쪽으로 덮이는 것을 특징으로 하는 이중 이미지 공정에 의한 무도금 패턴을 갖는 비오씨 기판의 제조방법에 관한 것으로, 와이어본딩용 전기 도금을 위한 도금패턴을 별도로 형성하지 않고, 필요한 패턴에만 니켈/금도금하여 불필요한 도금패턴으로 인한 전기적 잡음을 감소시킨 이중 이미지 공정에 의한 무도금 패턴을 갖는 비오씨 기판의 제조방법에 관한 것으로서 제3이미지 공정의 디자인으로 금도금에서 회로가 단락되는 문제점을 해결하였다.The present invention is the first imaging step, the first etching step, the conductive layer forming step, the second imaging step, the second etching step, the third imaging step, nickel / gold plating step, the third etching step, solder resist coating step, routing In the applicant's previously filed invention (patent no. 2004-0079346) consisting of a step, an image boundary surface of a photosensitive material for exposing a portion to be nickel / gold plated to the outside in the third imaging step is the conductive layer to the outside. The present invention relates to a method of manufacturing a BOS substrate having a non-plating pattern by a double image process, characterized by covering the outer surface of the image of the dry film for exposure, and does not separately form a plating pattern for electroplating for wire bonding. BOS with a non-plating pattern by dual image process to reduce electrical noise due to unnecessary plating pattern by nickel / gold plating only necessary pattern A first problem that a short circuit in the gold plating to the design of the third image processing relates to a method of manufacturing the plate was resolved.

드라이필름, 본딩핑거, 니켈/금 도금층, 회로패턴, 감광성 물질 Dry film, bonding finger, nickel / gold plated layer, circuit pattern, photosensitive material

Description

이중 이미지 공정에 의한 무도금 패턴을 갖는 비오씨 기판의 제조방법{The fabrication method for BOC substrate having non-plate pattern by double image process} The fabrication method for BOC substrate having non-plate pattern by double image process             

도 1은 종래의 반도체 패키지용 인쇄회로기판의 제조과정을 나타내는 흐름도이다. 1 is a flowchart illustrating a manufacturing process of a conventional printed circuit board for a semiconductor package.

도 2a 내지 도 2f는 종래의 반도체 패키지용 인쇄회로기판의 제조과정을 나타내는 단면도이다. 2A through 2F are cross-sectional views illustrating a manufacturing process of a conventional printed circuit board for semiconductor packages.

도 3은 종래의 반도체 패키지용 인쇄회로기판의 제조과정에 의해 회로 패턴이 형성된 상태를 나타내는 인쇄회로기판의 평면도이다. 3 is a plan view of a printed circuit board showing a state in which a circuit pattern is formed by a manufacturing process of a conventional printed circuit board for semiconductor packages.

도 4는 본 발명에 의한 기판의 제조과정을 나타내는 흐름도이다. 4 is a flowchart illustrating a manufacturing process of a substrate according to the present invention.

도 5a 내지 도 5i는 본 발명에 의한 기판의 형성과정을 나타내는 단면도이다.5A to 5I are cross-sectional views illustrating a process of forming a substrate according to the present invention.

도 6은 본 발명에 의한 인쇄회로기판의 완성된 상태를 나타내는 평면도이다. 6 is a plan view showing a completed state of the printed circuit board according to the present invention.

<도면의 주요부분에 대한 부호의 설명> <Description of the symbols for the main parts of the drawings>

11, 21 : 기판                   12, 22 : 동 11, 21: substrate # 12, 22: copper

13, 23, 26 : 드라이필름         14, 24 : 회로패턴 13, 23, 26: dry film # 14, 24: circuit pattern

15, 29 : 솔더레지스트           16, 27 : 본딩핑거 15, 29: solder resist 16, 27: bonding finger

17, 28 : 솔더볼패드             25 : 전도층 17, 28: solder ball pad # 25: conductive layer

18 : 도금용 리드선 20, 30 : 슬롯18: plating lead wire 20, 30: slot

31 : 감광성 물질31 photosensitive material

본 발명은 반도체 패키지 기판의 제조방법에 관한 것으로, 상세하게는 와이어본딩용 전기도금을 위한 도금패턴을 별도로 형성하지 않고, 필요한 패턴에만 니켈/금도금하여 불필요한 도금패턴으로 인한 전기적 잡음을 감소시킨 이중 이미지 공정에 의한 무도금 패턴을 갖는 비오씨 기판의 제조방법에 관한 것으로서 제3이미징 공정의 디자인으로 금도금에서 회로가 단락되는 문제점을 해결하였다.The present invention relates to a method for manufacturing a semiconductor package substrate, and in particular, without forming a plating pattern for electroplating for wire bonding, nickel / gold plating only necessary pattern to reduce the electrical noise due to unnecessary plating pattern The present invention relates to a method of manufacturing a BOC substrate having a non-plating pattern by a process, and solves a short circuit problem in gold plating by designing a third imaging process.

일반적으로 종래의 인쇄회로기판 제조방법은 도 1 내지 도 3에 도시되어 있는바와 같이, 이미징 단계에서 양면에 동(12)이 입혀진 기판(11)의 양면 상에 드라이필름(13)을 도포하고, 도 2b와 같이 회로패턴 및 도금용 리드선이 형성될 부분을 제외한 부분의 동(12)을 외부로 노출시킨다. In general, a conventional printed circuit board manufacturing method, as shown in Figures 1 to 3, by applying a dry film 13 on both sides of the substrate 11 is coated with copper 12 on both sides in the imaging step, As shown in FIG. 2B, the copper 12 of the portion except for the portion where the circuit pattern and the plating lead wire are to be formed is exposed to the outside.

그 후, 에칭단계에서는 도 2c와 같이 상기 외부로 노출된 동(12)을 제거하고, 스트립 단계에서는 도 2d와 같이 회로패턴 및 도금용 리드선을 덮고 있는 드라이필름(13)을 제거하여 원하는 패턴을 얻는다. Then, in the etching step, the copper 12 exposed to the outside is removed as shown in FIG. 2C, and in the stripping step, as shown in FIG. 2D, the dry film 13 covering the circuit pattern and the plating lead wire is removed to remove the desired pattern. Get

또한, 솔더마스킹단계에서는 도 2e와 같이 전면을 솔더레지스트로 도포한 후 금도금 영역을 열어 놓는다. In addition, in the solder masking step, the entire surface is coated with a solder resist as shown in FIG. 2E and then the gold plating region is opened.

다음으로, 니켈/금도금 단계에서는 도 2f와 같이 솔더레지스트(15)가 덮여지지 않은 본딩핑거(16) 및 솔더볼패드(17), 그리고 도금선(18) 상에 전기 도금을 수행하여 니켈/금도금층(16, 17) 을 형성시킨다. Next, in the nickel / gold plating step, as shown in FIG. 2F, electroplating is performed on the bonding finger 16, the solder ball pad 17, and the plating line 18 which are not covered with the solder resist 15 to form the nickel / gold plating layer. (16, 17) are formed.

마지막으로 도 3과 같이 슬롯(20)을 가공하여 인쇄회로기판을 완성시킨다.Finally, the slot 20 is processed as shown in FIG. 3 to complete the printed circuit board.

상기와 같이 종래에는 인쇄회로기판 상에 단일 이미징 공정에 의해 회로패턴과 본딩핑거를 함께 형성시키고, 상기 본딩핑거 상에 니켈/금도금을 하기 위한 금도금선이 필요하였고, 제2차에칭 후 도금하게 되면 현상된 드라이필름 주위에 전도층이 외부로부터 열려있어서 금도금되어 회로가 단락되는 문제점이 있었다.As described above, in the related art, a circuit pattern and a bonding finger are formed together on a printed circuit board by a single imaging process, and a gold plating wire for nickel / gold plating is required on the bonding finger. There was a problem in that the conductive layer was opened from the outside around the developed dry film, and the circuit was shorted due to gold plating.

상기의 문제점을 해결하기 위해 안출된 본 발명은 무도금 패턴을 갖는 BOC(Board On Chip) 기판 제조에 있어서 제2차에칭 후 도금하게 되면 현상된 드라이필름 주위에 전도층이 외부로부터 열려있어서 금도금되어 회로가 단락되는 것을 방지하기 위하여 제3차 이미지 공정단계에서 금속표면을 중첩하여 금도금되는 현상 을 원천적으로 방지하는 이중 이미지 공정에 의한 무도금 패턴을 갖는 비오씨 기판의 제조방법을 제공하는데 목적이 있다.
The present invention devised to solve the above problems is plated after the secondary etching in the manufacturing of BOC (Board On Chip) substrate having a non-plating pattern, the conductive layer around the developed dry film is opened from the outside and gold-plated It is an object of the present invention to provide a method of manufacturing a BOS substrate having a non-plating pattern by a dual image process that prevents a short circuit of gold plating by overlapping a metal surface in a third image processing step to prevent a short circuit. .

상기의 목적으로 구성되는 본 발명은 도 4 내지 도 6과 같이 동(22)이 양면으로 부착된 기판(21)의 양면에 드라이필름(23)을 압착하여 회로가 형성될 부분 이외의 동(22)을 외부로 노출시키는 제1이미징 단계(S410)와, 상기 외부로 노출된 동(22)을 제거하는 제1에칭 단계(S420)와, 상기 제1에칭한 기판(21)의 양면에 화학 동 도금 또는 전도층(25)으로 증착하는 전도층 형성단계(S430)와, 상기 박막을 형성한 후 액상 또는 드라이필름(26)을 이용하여 본딩핑거(27)와 솔더볼패드(28)가 형성될 부분의 증착된 전도층(25)을 외부로 노출시키는 제2이미징 단계(S440)와, 상기 전도층(25)을 제거하는 제2에칭단계(S450)와, 상기 제2에칭한 기판(21)의 양면에 감광성 물질(31)을 이용하여　니켈/금도금 될 부분인 본딩핑거(27) 및 솔더볼패드(28) 부분을 외부로 노출시키는 제3이미징 단계(S460)와, 상기 노출된 본딩핑거(27) 및 솔더볼패드(28)에 전기도금을 수행하여 니켈/금도금층을 형성시키는 니켈/금도금단계(S470)와, 상기 감광성 물질(31)인 드라이필름(26)을 제거하고, 니켈/금도금되지 않은 패턴 부분의 전도층(25)을 제거하는 제3에칭단계(S480)와, 상기 본딩핑거(27)와 솔더볼패드(28)를 제외한 영역에 솔더레지스트(29)를 도포하여 회로를 외부로부터 절연시키는 솔더레지스트 도포단계(S490)와, 상기 기판(21)의 외형 및 슬롯을 가공 형성하는 라우팅 단계(S500)에 있어서, 상기 제3이미징 단계(S460)에서 니켈/금도금 될 부분을 외부로 노출시키기 위한 감광성 물질(31)의 이미지 경계면은 상기 제2이미징 단계(S440)의 전도층(25)을 외부로 노출시키기 위한 드라이필름(26)의 이미지 경계면 바깥쪽으로 덮이는 것을 특징으로 하는 이중 이미지 공정에 의한 무도금 패턴을 갖는 비오씨 기판의 제조방법을 제공한다. The present invention constituted for the above purpose, as shown in Figures 4 to 6, the copper 22 other than the portion where the circuit will be formed by pressing the dry film 23 on both sides of the substrate 21 to which the copper 22 is attached on both sides. ) Is first exposed to the outside (S410), the first etching step (S420) for removing the externally exposed copper 22, and the chemical copper on both sides of the first etched substrate 21 A conductive layer forming step (S430) of depositing a plating or conductive layer 25 and a portion where the bonding finger 27 and the solder ball pad 28 are to be formed using a liquid or dry film 26 after forming the thin film. The second imaging step (S440) of exposing the deposited conductive layer 25 to the outside, the second etching step (S450) of removing the conductive layer 25, and the second etching of the substrate 21 A third imaging step (S4) exposing the bonding finger 27 and the solder ball pad 28, which are to be nickel / gold plated, to the outside by using the photosensitive material 31 on both sides (S4). 60), a nickel / gold plating step (S470) of forming a nickel / gold plating layer by performing electroplating on the exposed bonding finger 27 and the solder ball pad 28, and a dry film as the photosensitive material 31 And removing the conductive layer 25 of the non-nickel / gold plated pattern portion 26 and removing the bonding finger 27 and the solder ball pad 28. 29) in the step of applying a solder resist to insulate the circuit from the outside (S490) and the routing step (S500) of forming the shape and slot of the substrate 21, in the third imaging step (S460) The image interface of the photosensitive material 31 for exposing the portion to be nickel / gold plated to the outside is outside the image interface of the dry film 26 for exposing the conductive layer 25 of the second imaging step S440 to the outside. Due to the dual image process It provides a process for the production of non-Oh substrate having a copper-free pattern.

이하, 본 발명에 의한 이중 이미지 공정에 의한 무도금 패턴을 갖는 비오씨 기판의 제조방법을 도면에 도시한 실시 예를 참고하여 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a BOC substrate having a non-plating pattern by a dual image process according to the present invention will be described in detail with reference to the embodiment shown in the drawings.

도 4는 본 발명에 의한 기판의 제조과정을 나타내는 흐름도이고, 도 5a 내지 도 5i는 본 발명에 의한 기판의 형성과정을 나타내는 단면도이다. 4 is a flowchart illustrating a process of manufacturing a substrate according to the present invention, and FIGS. 5A to 5I are cross-sectional views illustrating a process of forming a substrate according to the present invention.

상기 제1이미징 단계(S410)는 도 5a 및 도 5b에 도시한 바와 같이, 양면에 동(22)이 입혀진 기판(21)의 양면에 드라이필름(23)을 압착하고, 노광 및 현상을 통해 회로가 형성될 부분 이외의 동(22)만을 외부로 노출시키고, 5A and 5B, the first imaging step S410 is performed by compressing the dry film 23 on both sides of the substrate 21 on which copper 22 is coated on both sides, and exposing and developing the circuit. Expose only the copper 22 other than the portion to be formed to the outside,

상기 제1에칭 단계(S420)는 도 5c 및 도 5d에 도시한 바와 같이, 상기 제1이미징 단계(S410)에서 외부로 노출된 동(22)을 제거하여 회로패턴(24)을 형성한다.In the first etching step S420, as illustrated in FIGS. 5C and 5D, the copper pattern 22 exposed to the outside in the first imaging step S410 is removed to form a circuit pattern 24.

상기 전도층 형성 단계(S430)는 도 5e에 도시한 바와같이 동도금 또는 증착에 의하여 박막을 형성하고, 일시적인 니켈/금도금을 위한 전도층(25)을 형성한다.The conductive layer forming step (S430) forms a thin film by copper plating or evaporation as shown in FIG. 5E, and forms a conductive layer 25 for temporary nickel / gold plating.

상기 제2이미징 단계(S440) 에서는 도 5f에 도시한 바와 같이, 양면에 드라이필름(26)을 재 압착한 뒤, 노광 및 현상을 통해 니켈/금도금 될 부분의 전도층(25)을 외부로 노출시키며, In the second imaging step (S440), as shown in FIG. 5F, the dry film 26 is recompressed on both surfaces, and the exposed conductive layer 25 of the nickel / gold plated portion is exposed to the outside through exposure and development. And

상기 제2에칭 단계(S450)는 상기 외부로 노출된 전도층(25)을 제거한다. In the second etching step S450, the conductive layer 25 exposed to the outside is removed.

상기 제3이미징 단계(S460)는 상기 전도층(25)이 제거된 기판(22)의 양면에 감광성 물질(31)을 도포하고, 상기 감광성 물질(31)을 이용하여 니켈/금도금될 부분을 노광 및 현상을 통해 외부로 노출시킨다.In the third imaging step S460, the photosensitive material 31 is coated on both surfaces of the substrate 22 from which the conductive layer 25 is removed, and the portion to be nickel / gold plated is exposed using the photosensitive material 31. And exposed to the outside through development.

상기 니켈/금도금 단계(S470)는 도 5g에 도시한 바와 같이, 상기 외부로 노출된 본딩핑거(27)와 솔더볼패드(28)가 형성될 부분의 동(22) 표면에 전기적으로 니켈/금도금을 수행하여, 니켈/금도금층(27, 28)을 형성하고, 상기 니켈/금도금층은 본딩핑거(27)와 솔더볼패드(28)의 상부 및 측면까지 형성되는 것을 특징으로 한다.In the nickel / gold plating step S470, as shown in FIG. 5G, nickel / gold plating is electrically performed on the copper 22 surface of the portion where the bonding finger 27 and the solder ball pad 28 are formed to be exposed to the outside. The nickel / gold plating layers 27 and 28 are formed, and the nickel / gold plating layers are formed to the upper and side surfaces of the bonding finger 27 and the solder ball pad 28.

이때, 상기 제3이미징 단계(S460)에서 니켈/금도금 될 부분을 외부로 노출시키기 위한 감광성 물질(31)의 이미지 경계면은 상기 제2이미징 단계(S440)에서 전도층(25)을 외부로 노출시키기 위해 압착한 제2이미징의 드라이필름(26)을 포함하여 도포하도록 하여, 상기 드라이필름(26) 이미지 경계면 보다 바깥쪽으로 형성되는 것을 특징으로 한다. In this case, an image boundary surface of the photosensitive material 31 for exposing the portion to be nickel / gold plated to the outside in the third imaging step S460 may expose the conductive layer 25 to the outside in the second imaging step S440. In order to include the dry film 26 of the second imaging to be applied, it is characterized in that the dry film 26 is formed outward from the image boundary surface.

상기 제3에칭 단계(S480)는 도 5h에 도시한 바와 같이, 상기 감광성 물질(31)인 드라이필름(26)을 박리한 후 박막의 전도층(25)이 여전히 남아있는 패턴영역으로부터 전도층(25)을 완전히 제거한다. As shown in FIG. 5H, the third etching step S480 is performed after the peeling of the dry film 26, which is the photosensitive material 31, from the pattern region in which the conductive layer 25 of the thin film remains. 25) Remove completely.

상기 솔더레지스트 도포단계(S490)에서는 솔더레지스트(29)를 인쇄하여 노광 후, 상기 본드핑거(27)와 솔더볼패드(28)를 제외한 모든 영역에 상기 솔더레지스트(29)를 도포하여 회로를 외부로부터 절연시킨다. In the soldering resist coating step (S490), after printing and printing the solder resist 29, the solder resist 29 is applied to all areas except the bond finger 27 and the solder ball pad 28, the circuit from outside Insulate.

상기 라우팅 단계(S500)는 기판(21)의 외형 및 슬롯(30)을 가공하여 완제품을 형성한다.The routing step S500 processes the outer shape and the slot 30 of the substrate 21 to form a finished product.

상기와 같이 본 발명은 도금선(18) 없이도 전기적인 방법으로 금도금이 가능하여 별도의 도금선을 형성할 필요가 없는 효과가 있다. As described above, the present invention has the effect that it is possible to gold-plated by an electrical method without the plating line 18, and there is no need to form a separate plating line.

이상은 본 발명의 실시 예를 설명한 것이지만 본 발명은 상기의 실시 예에 한정되지 않으며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 본 발명의 기술사상과 아래에 기재된 청구범위의 범위 내에서 다양한 수정 및 변형이 가능하다. Although the above has described embodiments of the present invention, the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains the technical idea of the present invention and the claims described below. Various modifications and variations are possible within.

상기와 같이 구성되는 본 발명은 양면에 동이 덮인 기판상에 제1이미징 및 에칭에 의해 패턴을 먼저 형성하고 제3이미징으로 전기도금에 의해 본딩핑거와 솔더볼패드에 니켈/금도금하면서, 니켈/금도금되지 않은 전도층을 제거하여, 도금용 리드선 없이도 필요한 패턴만을 형성하도록 함으로써 디자인의 완벽성과 높은 신뢰성으로 와이어 본딩이 가능하고, BOC/FBGA((Board On Chip/Fine pitch Ball Grid Array)의 구조적인 슬롯 가공시 버를 근본적으로 제거한 효과가 있다. The present invention configured as described above forms a pattern on the substrate covered with copper on both sides by first imaging and etching, and then nickel / gold plated on the bonding finger and the solder ball pad by electroplating with the third imaging. By removing the non-conductive layer, only the necessary pattern is formed without the plating lead wire, so that wire bonding is possible with perfection of design and high reliability, and structural slotting of BOC / FBGA (Board On Chip / Fine pitch Ball Grid Array) It has the effect of removing the shiver fundamentally.

Claims (4)

동이 양면으로 부착된 기판의 양면에 드라이필름을 압착하여 본딩핑거가 형성될 부분 이외의 동을 외부로 노출시키는 제1이미징 단계와; A first imaging step of compressing the dry film on both sides of the substrate on which the copper is attached to both sides to expose the copper to the outside except the portion where the bonding finger is to be formed; 상기 외부로 노출된 동을 제거하여 회로를 형성하는 제1에칭 단계와; A first etching step of forming a circuit by removing the copper exposed to the outside; 상기 제1에칭한 기판의 양면에 화학 동 도금 또는 전도층으로 증착하여 박막을 형성한 후 액상 또는 드라이필름을 재 압착하여 노광 및 현상을 통해 니켈/금도금 될 부분의 전도층(25)을 외부로 노출시키는 제2이미징 단계와; After forming a thin film by chemical copper plating or conductive layer on both sides of the first etched substrate, the liquid or dry film is recompressed to expose the conductive layer 25 of the portion to be nickel / gold plated through exposure and development. Exposing a second imaging step; 상기 전도층을 제거하는 제2에칭 단계와;A second etching step of removing the conductive layer; 상기 전도층을 제거한 기판의 양면에 감광성 물질을 이용하여 니켈/금도금 될 부분인 본딩핑거 및 솔더볼패드 부분을 외부로 노출시키는 제3이미징 단계와;A third imaging step of exposing the bonding finger and the solder ball pad portions, which are portions to be nickel / gold plated, to the outside using photosensitive materials on both surfaces of the substrate from which the conductive layer is removed; 상기 노출된 본딩핑거 및 솔더볼패드에 전기도금을 수행하여 니켈/금도금층을 형성시키는 니켈/금도금 단계와;A nickel / gold plating step of electroplating the exposed bonding finger and the solder ball pad to form a nickel / gold plating layer; 상기 감광성 물질인 드라이필름을 제거하고, 니켈/금도금되지 않은 패턴 부분의 전도층을 제거하는 제3에칭 단계와;A third etching step of removing the dry film of the photosensitive material and removing the conductive layer of the nickel / gold plated pattern portion; 상기 본드핑거와 솔더볼패드를 제외한 영역에 솔더레지스트를 도포하여 회로를 외부로부터 절연시키는 솔더레지스트 도포단계와;A solder resist coating step of insulating the circuit from the outside by applying solder resist to areas other than the bond finger and the solder ball pad; 상기 기판의 외형 및 슬롯을 가공 형성하는 라우팅 단계; 에 있어서,Routing step of forming the shape and the slot of the substrate; To 상기 제3이미징 단계의 감광성 물질의 이미지 경계면은 상기 제2이미징 단계의 드라이필름의 이미지 경계면 보다 바깥쪽으로 덮이는 것을 특징으로 하는 이중 이미지 공정에 의한 무도금 패턴을 갖는 비오씨 기판의 제조방법.The image interface of the photosensitive material of the third imaging step is covered with the outer surface than the image interface of the dry film of the second imaging step, characterized in that the manufacturing method of the BOC substrate having a non-plating pattern by a dual imaging process. 제1항에 있어서, The method of claim 1, 상기 제2이미징 단계의 박막은 전도층을 형성하는 것을 특징으로 하는 이중 이미지 공정에 의한 무도금 패턴을 갖는 비오씨 기판의 제조방법.The thin film of the second imaging step is a method of manufacturing a BOC substrate having a non-plating pattern by a dual imaging process, characterized in that to form a conductive layer. 제1항에 있어서, The method of claim 1, 상기 제1이미징, 제2이미징, 제3이미징 단계의 외부 노출은 노광 및 현상을 이용하는 것을 특징으로 하는 이중 이미지 공정에 의한 무도금 패턴을 갖는 비오씨 기판의 제조방법.The external exposure of the first imaging, the second imaging, and the third imaging step uses exposure and development. 제1항에 있어서, The method of claim 1, 상기 니켈/금도금 단계의 니켈/금도금층은 상기 본딩핑거의 상부 및 측면에 형성되는 것을 특징으로 하는 이중 이미지 공정에 의한 무도금 패턴을 갖는 비오씨 기판의 제조방법.The nickel / gold plating step of the nickel / gold plating step is a method of manufacturing a BOC substrate having a non-plating pattern by a dual image process, characterized in that formed on the upper and side of the bonding finger.
KR1020040098128A 2004-11-26 2004-11-26 Method for manufacturing bio seed substrate with unplated pattern by dual image process Expired - Lifetime KR100609647B1 (en)

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