KR100600048B1 - Static electricity protection circuit of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection circuit of a semiconductor device. In particular, when a transistor having a gate coupled with an input / output pad is used as an electrostatic protection circuit, the invention enables fast electrostatic discharge without increasing the area of the circuit. to be. In accordance with an aspect of the present invention, an electrostatic protection circuit including a MOS transistor includes: a ground power supply line; A signal line connected between the input pad and the internal circuit; A plurality of MOS transistors connected in parallel between the signal line and the ground power supply line; A plurality of resistors connected in series between a gate terminal of the first MOS transistor adjacent to the input pad and a gate terminal of the last MOS transistor, and each connection node connected to a gate terminal of the corresponding MOS transistor; And a first resistor connected between the gate terminal of the last MOS transistor and the ground power line.

Electrostatic Discharge, ESD, Parasitic Capacitance, Bipolar, Area

Description

Electrostatic protection circuit of semiconductor device {ELECTRO STATIC DISCHARGE CIRCUIT IN SEMICONDUCTOR DEVICE}             

1 is a circuit diagram showing a gate couple NMOS transistor and a resistor used as an electrostatic protection circuit according to the prior art;

FIG. 1B is a circuit diagram showing a gate coupled n-mode transistor and a resistor for an electrostatic protection circuit using parasitic capacitance according to another prior art; FIG.

Figure 2a is a plan view showing a static electricity protection circuit according to an embodiment of the present invention,

Figure 2b is a circuit diagram showing a static electricity protection circuit according to an embodiment of the present invention;

3A is a plan view showing a static electricity protection circuit according to another embodiment of the present invention;

3B is a circuit diagram illustrating a static electricity protection circuit according to another embodiment of the present invention;

* Description of the symbols for the main parts of the drawings *

11: Input Pad 12: Gate Couple NMOS

13 capacitor 14 resistance

15: internal circuit 21: substrate

22 device isolation layer 23 gate electrode

100: input pad 101: internal circuit

103: parasitic capacitor 104: resistance

delete

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection circuit. In particular, when a MOS transistor having a gate coupled to an input pad is applied to an electrostatic protection circuit, the area of the device can be reduced, but the fast operation of the electrostatic protection circuit is possible. It is about invention.

Static electricity refers to a phenomenon in which current flows instantaneously due to a very large voltage difference between two objects when two insulated objects come into contact with each other. Therefore, if a current caused by static electricity flows through a semiconductor internal circuit, which is usually designed to have a power supply voltage of 5 V or less, there is a risk of fatal damage of each circuit element.

The electrostatic discharge can be divided into two types, one of which is when the potential of the external object is higher than the potential of the semiconductor chip, and the other is when the potential of the external object is lower than the potential of the semiconductor chip.

In the former case, the current due to the electrostatic discharge flows from the external object to the semiconductor chip, and in the latter case, the current due to the electrostatic discharge flows from the semiconductor chip to the external object.

In general, since the electrostatic discharge current caused by the former significantly degrades the circuit elements in the semiconductor chip, as compared with the latter, the electrostatic protection circuit of the semiconductor device needs to be designed to stably discharge the accumulated charge.

The following describes the internal circuit damage caused by electrostatic discharge (ESD). First, when an electrostatic current is applied through an input terminal by an ESD pulse, the applied electrostatic current finally exits another terminal through an internal circuit. At this time, due to the joule heat generated by the electrostatic current, junction spiking or oxide film cracking occurs in a weak place, thereby damaging the device.

Therefore, most semiconductor integrated circuits have an electrostatic discharge protection circuit between the input / output pad and the internal circuit to protect the main circuit from such damage, and the input / output buffers also often have an electrostatic protection function.

The operation of the static electricity protection circuit is described in detail in "A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, 2nd Edition, Wiley (2002)".

Conventionally, a Bipolar Junction Transistor (BJT) or a diode is widely used as an electrostatic protection device. Recently, a gated NMOS transistor (GGNMOS) is used.

The GGNMOS transistor is a transistor whose gate is grounded. Like the conventional MOS transistor, the GGNMOS transistor is not turned on and operated by channel formation, but the npn structure of the NMOS transistor is caused by a breakdown phenomenon. It is a device designed to discharge a large amount of current by operating like a junction transistor (also called a parasitic bipolar operation).

On the other hand, with the development of semiconductor technology, the thickness of the gate oxide film becomes thinner, and thus, the gate oxide film is more easily damaged by the ESD pulse.

That is, when the thickness of the gate oxide film is reduced, the voltage level at which the gate oxide film is damaged is also lowered. When the conventional method is used as it is, the gate oxide film is frequently damaged by an electrostatic pulse.

Therefore, various methods have been proposed to solve this problem, among which the following methods have been proposed.

This method is such that as the gate oxide film becomes thinner, the time for the gate oxide film to reach the damaged voltage is shortened, so that the electrostatic protection circuit also operates quickly.

That is, the parasitic bipolar operation of the MOS transistor used as the electrostatic protection circuit is performed quickly, and the electrostatic pulse is discharged before the gate oxide film is damaged.

On the other hand, since the parasitic bipolar operation time of the electrostatic protection circuit is activated in proportion to the junction breakdown voltage, in this method, a method of controlling the impurity concentration in the junction region is applied to reduce the junction breakdown voltage.

However, the method of controlling the impurity concentration in the junction region requires not only a separate optimization task for the bonding characteristics, but also increases the leakage current in normal operation, which increases the possibility of malfunction.

Next, another method for preventing damage to the internal circuit due to electrostatic discharge will be described with reference to Figure 1a.

In this method, while using an NMOS transistor as an electrostatic protection device, a method of coupling a gate and an input pad so that the gate of the NMOS transistor turns on quickly when an ESD pulse is applied is applied.

Referring to FIG. 1A, an input pad 11 and an internal circuit 15 are illustrated, and the input pad and the internal circuit are connected by wires. In addition, a capacitor 13 and a resistor 14 are connected in series between the input pad and the ground.

In addition, an NMOS transistor 12 is connected between the input pad 11 and the ground terminal. A drain of the NMOS transistor is connected to the input pad, a source is connected to the ground terminal, and a gate is connected to the capacitor 13. The resistor 14 is connected to a node connected in series.

The operation of the electrostatic protection circuit configured as described above is as follows. First, when a high frequency ESD pulse is applied to the input pad 11, the current caused by the ESD pulse is discharged to the ground terminal through the capacitor 13 and the resistor (14).

At this time, the voltage drop is generated by the current passing through the resistor 14, and thus the gate voltage is increased. That is, when the gate voltage which is normally grounded rises by the voltage drop, the NMOS transistor 12 is turned on so that an electrostatic current flows through the channel of the NMOS transistor 12. By this method, the parasitic bipolar operation of the NMOS transistor can be performed quickly.

For reference, in the parasitic bipolar operation, the substrate (substrate or well) corresponds to the base of the bipolar transistor, the source region of the NMOS transistor corresponds to the emitter, and the drain region of the NMOS transistor is the collector. Corresponds to (collector).

At this time, there is a study proposed that the voltage drop through the resistor 14 is 1 volt or more. (J. Chen, Amerasekera and C. Duvvury, Design Methology for optimizing Gate Driven ESD Protection Circuti in Submicron CMOS Processes, in Proc 19th EOS / ESD Symposium, pp. 230-239 (1997))

Also, instead of using a separate capacitor 13 as shown in FIG. 1A, a method of using parasitic capacitance has been proposed.

This method is described with reference to FIG. 1B. FIG. 1B is a method of using parasitic capacitance instead of using an additional capacitor, in which a gate-drain fringing capacitance (part denoted by A in FIG. 1B) and a gate-drain overlap capacitance are shown. capacitance) (part denoted by B in FIG. 1B) was used as the parasitic capacitance. Since the operation of the circuit shown in FIG. 1B is similar to the circuit shown in FIG. 1A, description thereof will be omitted.

However, when the circuit shown in FIG. 1A or 1B is used as an electrostatic protection circuit, the following problem occurs.

First, as described above, in order for the electrostatic protection circuit shown in FIG. 1A or 1B to operate quickly, a voltage drop of 1 volt or more at the resistor 14 is required so that the gate is turned on.

However, in order to enable voltage drops of more than 1 volt, more than a few kΩ resistors are required, and moreover, if several ESD transistors 12 are arranged in parallel for efficient electrostatic discharge, each resistor requires a respective resistor. As a result, the area is greatly increased. As a result, the size of the chip is also increased, and the manufacturing cost of the chip is also increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object thereof is to provide an electrostatic protection circuit capable of fast operation while reducing an area.

In order to achieve the above object, the present invention provides an electrostatic protection circuit including a MOS transistor, comprising: a ground power supply line; A signal line connected between the input pad and the internal circuit; A plurality of MOS transistors connected in parallel between the signal line and the ground power supply line; A plurality of resistors connected in series between a gate terminal of the first MOS transistor adjacent to the input pad and a gate terminal of the last MOS transistor, and each connection node connected to a gate terminal of the corresponding MOS transistor; And a first resistor connected between the gate terminal of the last MOS transistor and the ground power line.

In the present invention, a gate-coupled MOS transistor (GCMOS) is used as an electrostatic protection device. In the case where a plurality of MOS transistors are connected in parallel between an input pad and a ground terminal, a rapid electrostatic discharge operation is performed. In addition, the present invention reduces the area of the chip compared to the prior art by reducing the area of the resistor connecting the gate and the ground terminal of the MOS transistor. In the present invention, the parasitic bipolar operation time of each MOS transistor having an electrostatic protection function can be made uniform.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

2A and 2B are diagrams illustrating an electrostatic protection circuit according to an embodiment of the present invention, and FIG. 2A is a plan view showing a state in which an electrostatic protection circuit according to an embodiment of the present invention is implemented on a semiconductor substrate. 2B is a circuit diagram schematically illustrating an electrostatic protection circuit according to an embodiment of the present invention.

Before describing this, in the embodiment of the present invention, a gate-coupled MOS transistor (GCMOS) coupled with an input pad is used as an electrostatic protection device, and among them, an NMOS transistor is used. And instead of an additional capacitor as shown in Fig. 1A, a parasitic capacitor as shown in Fig. 1B was used.

An embodiment of the present invention will be described with reference to such a point, but with reference to FIG. 2B.

In FIG. 2B, the input pad 100 and the internal circuit 101 are illustrated, and the input pad 100 and the internal circuit 101 are connected by wires.

N gate-coupled NMOS transistors GCNMOS TrN to Tr1 are connected in parallel between the input pad 100 and the ground terminal.

Hereinafter, TrN, the N-th gate couple NMOS transistor, will be referred to as an N-th transistor, and Tr1, the first gate-coupled NMOS transistor, will be referred to as a first transistor.

Here, each transistor has the following connection. First, a source of a transistor is connected to the ground terminal, and a drain of the transistor is connected to the input pad 100.

The gate of the transistor is connected to a node in which the parasitic capacitor 103 and the resistor 104 are connected in series. Here, the parasitic capacitor 103 uses a gate-drain fringe capacitance and a gate-drain overlap capacitance, and the parasitic capacitor 103 is connected between the input pad 100 and the gate of the transistor.

Next, the connection relationship of the resistor 104 will be described. First, one resistor is provided corresponding to each transistor, and one side of each resistor is connected to the gate and parasitic capacitor 103 of each transistor.

The other side of each resistor is connected in series with a resistor connected to a gate of an adjacent transistor.

The connection of such a resistor will be described with reference to the Nth transistor, the N-1 transistor, the second transistor, and the first transistor as follows.

First, a resistor 104 is connected to the gate of the N-th transistor, and another node of the resistor is connected in series with another resistor connected to the gate of the N-th transistor.

In the case of the first transistor Tr1 provided at the far end, the resistor 104a connected to the gate Tr1 of the first transistor is connected in series with the resistor 104 connected to the gate of the second transistor Tr2. The other node of the resistor 104a connected to the gate of the first transistor Tr1 is connected to the ground terminal.

That is, N resistors are connected in series between the gate and the ground terminal of the N-th transistor TrN, and N-1 resistors are connected between the gate and the ground terminal of the N-th transistor TrN-1. It becomes the connected configuration.

In the case of the first transistor Tr1, one resistor 104a is connected between the gate and the ground terminal of the first transistor Tr1. For reference, the structure in which the resistor 104a is connected between the first transistor Tr1 and the ground terminal is the same as the structure in which the resistor is connected between the gate and the ground terminal of the transistor illustrated in FIGS. 1A to 1B. .

In addition, as will be described later, the resistor 104a (the resistor closest to the ground terminal) connected between the first transistor Tr1 and the ground terminal is preferably implemented as a variable resistor.

2A is a plan view showing an implementation of an electrostatic protection circuit on a semiconductor substrate according to an embodiment of the present invention. Referring to this, first, a plurality of transistors arranged in a line is illustrated.

A contact is formed in the drain region and the source region of each transistor. Although not shown in FIG. 2A, the drain region is connected to the input pad through the contact, and the source region is connected to the ground terminal through the contact.

For reference, since the NMOS transistor is used in one embodiment of the present invention, it can be seen that the source / drain region of the transistor is composed of a highly doped n-type ion implantation region.

In addition, it can be seen that a resistor made of a conductive material is connected in series to the gate of each transistor. In one embodiment of the present invention, the conductive material used as the resistor may use the same material as the gate electrode (for example, polysilicon), or a conductive material used as wiring in a circuit. Alternatively, a semiconductor substrate doped with impurities may be used as a resistor.

Finally, referring to the rightmost first transistor Tr1, a resistor 104a is connected to a gate of the first transistor Tr1, and the resistor 104a is connected to a ground terminal through a contact. As described above, the resistor 104a connected to the gate of the first transistor Tr1 is preferably a variable resistor.

In one embodiment of the present invention, a plurality of gate MOS transistors connected to resistors and parasitic capacitors are provided in this manner and are connected in parallel between the input pad and the ground terminal.

Next, the operation of the static electricity protection circuit according to an embodiment of the present invention shown in Figures 2a to 2b will be described.

First, when an electrostatic pulse is applied to the input pad, the Nth transistor first starts parasitic bipolar operation. This is because in the case of the Nth transistor, since the largest resistance is connected to the gate (N resistors are connected in series), the voltage drop due to this resistance is also the largest, so that a large voltage is applied to the gate.

Therefore, since the channel current of the transistor in which the Nth transistor is turned on also flows in proportion to the voltage applied to the gate, the channel current accelerates the parasitic bipolar operation time of the Nth transistor.

As such, when the Nth transistor starts the parasitic bipolar operation, the overall potential of the substrate or the well (which serves as the base of the parasitic bipolar transistor) rises, so that the remaining transistors in turn start the parasitic bipolar operation to restore the electrostatic current. Flow it to ground.

That is, in one embodiment of the present invention, the parasitic bipolar operation can be made faster by the N-th transistor having the largest resistance connected to the gate when the ESD pulse is applied.

In addition, in one embodiment of the present invention, since a resistor is connected in series to the gates of a plurality of transistors arranged in a line as shown in FIG. The area of can be greatly reduced.

When the resistor 104a closest to the ground terminal shown in Figs. 2A to 2B is formed of a variable resistor, by adjusting this resistance value, it is possible to adjust the voltage applied to the gate of the transistor during the application of an ESD pulse. There is an advantage.

Next, another embodiment of the present invention will be described with reference to FIGS. 3A to 3B. In another embodiment of the present invention, the parasitic bipolar operation time of the electrostatic protection circuit can be made more uniform in consideration of the resistance of the substrate or the resistance of the well. Hereinafter, wells will also be referred to as substrates.

In other words, the substrate is a highly doped region, and has a large resistance value per unit sheet (hundreds to thousands of square micrometers / square). By taking advantage of this, if the compensation for raising the base voltage is performed for the transistors having a late parasitic bipolar operating point, the parasitic bipolar operating point of each transistor can be made more uniform.

That is, when an electrostatic pulse is applied to the input pad, the potential of the substrate is increased by the voltage drop caused by the substrate resistance of the NMOS transistor. This corresponds to raising the base voltage of the parasitic bipolar transistor, thereby enabling the parasitic bipolar operation of the NMOS transistor to be quickly activated.

In another embodiment of the present invention, a gate-coupled MOS transistor (GCMOS), in which a gate is coupled to an input pad, is also used as an electrostatic protection device. Among them, an NMOS transistor is used (GCNMOS). The parasitic capacitor shown in FIG. 1B was used instead of the additional capacitor as shown.

First, another embodiment of the present invention will be described with reference to FIG. 3A.

3A is a plan view illustrating a state in which an electrostatic protection circuit according to another embodiment of the present invention is implemented on a semiconductor substrate. Comparing the structure shown in FIG. 2A, most of the components are composed of the same components, and most have the same connection relationship, except that a substrate pick-up region connected to the substrate and the ground terminal is formed on the N-th transistor side. Is the point.

That is, from the standpoint of the Nth transistor, since the substrate pickup region to which the substrate and the ground terminal are connected is formed nearest, the substrate resistance has the smallest substrate resistance.

However, from the standpoint of the first transistor, since the substrate pickup region that is connected to the substrate and the ground terminal is formed farthest, the substrate has the largest substrate resistance. In terms of circuit, the transistors farther from the substrate pickup region have a structure in which a plurality of resistors are connected in series.

Referring to FIG. 3A, a plurality of transistors TrN to Tr1 arranged in a row are illustrated, and contacts are formed in the drain region and the source region of each transistor.

Although not shown in FIG. 3A, the drain region of the transistor is connected to the input pad through the contact, and the source region of the transistor is connected to the ground terminal through the contact.

And as described above. A substrate pick-up region connected to the substrate and the ground terminal is formed on the Nth transistor side.

For reference, another embodiment of the present invention uses the NMOS transistor, and it can be seen that a resistor made of a conductive material is connected in series to the gate of each transistor.

In another embodiment of the present invention, the conductive material used as the resistor may use the same material as the gate electrode (for example, polysilicon) or a conductive material used as wiring in a circuit. Alternatively, a semiconductor substrate doped with impurities may be used as a resistor.

Referring to the rightmost transistor formed in FIG. 3A, a resistor 104a is connected to a gate of the first transistor, and the resistor 104a is connected to a ground terminal through a contact. As described above, the resistor (a resistance closest to the ground terminal) 104a connected to the gate of the first transistor is preferably implemented as a variable resistor.

Next, referring to FIG. 3B, the electrostatic protection circuit according to another embodiment of the present invention will be described as follows.

When comparing the circuit shown in Fig. 3B with the circuit shown in Fig. 2B, it can be seen that the remaining connection relations are the same except for the configuration in which the substrate resistance is connected.

Therefore, a description of how the source / drain and the gate of the transistor are connected will be omitted, and a description of the connection relationship between the resistors 104 and 104a and the parasitic capacitor 103 will be omitted.

Subsequently, the substrate resistance of the transistor will be described. First, since the substrate pickup region to which the substrate and the ground terminal of the transistor are connected is formed on the Nth transistor side, the Nth transistor has the smallest substrate resistance.

Next, the transistor having the small substrate resistance is the N-th transistor. That is, in the case of the N-th transistor, one substrate resistor 105 is connected in series between the substrate and the ground terminal. Reference numeral '105' is a model of the substrate resistance.

Similarly, in the case of the first transistor formed at the rightmost side (in other words, farthest from the substrate pickup region connecting between the substrate and the ground terminal), N substrate resistors are connected in series between the substrate and the ground terminal.

Next, the operation of the static electricity protection circuit according to another embodiment of the present invention shown in Figures 3a to 3b.

First, when an electrostatic pulse is applied to the input pad, the Nth transistor first starts parasitic bipolar operation. That is, in the case of the Nth transistor, since the largest resistance is connected to the gate (N resistors are connected in series), the voltage drop due to this resistance is also the largest, so that a large voltage is applied to the gate.

Therefore, since the channel current of the transistor in which the Nth transistor is turned on also flows in proportion to the voltage applied to the gate, the channel current accelerates the parasitic bipolar operation time of the Nth transistor.

According to this mechanism, the first transistor having the smallest resistance connected to the gate is expected to start the parasitic bipolar operation at the latest, but in another embodiment of the present invention, the substrate resistance is used to compensate for this.

That is, in the case of the first transistor illustrated in FIG. 2B, since the resistance connected to the gate is the smallest, the parasitic bipolar operation may be activated late when the ESD pulse is applied. However, in the case of the first transistor shown in Fig. 3B, since the circuit is configured to have the largest substrate resistance, the parasitic bipolar operation of the first transistor can be compensated for late.

That is, when an electrostatic pulse is applied to the input pad, the potential of the substrate is increased by the voltage drop caused by the substrate resistance of the NMOS transistor. At this time, since the potential of the substrate corresponds to the base voltage in the parasitic bipolar transistor, an increase in the substrate potential helps to quickly activate the parasitic bipolar operation.

At this time, since the first transistor has the largest substrate resistance, the rise of the substrate potential is also the largest, and therefore, the parasitic bipolar operation time is also advanced.

As described above, in another embodiment of the present invention, the substrate resistance is compensated for the delayed time of activation of the parasitic bipolar operation in the transistor having a low gate resistance (first transistor).

As a result, in another embodiment of the present invention, the timing of the parasitic bipolar operation of a plurality of NMOS transistors connected in parallel can be made more uniform, thereby obtaining an excellent electrostatic discharge effect.

In the above-described embodiments of the present invention, the NMOS transistor has been described as an example, but the technical idea of the present invention can be applied to the case where the PMOS transistor is used as an electrostatic protection element.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

By applying the present invention as described above, compared to the conventional electrostatic protection circuit, it is possible to greatly reduce the area occupied on the chip, and to speed up the operation time of the electrostatic protection circuit, and for high-speed operation to which a thin gate oxide film is applied. There is an advantage that it can be cheaply manufactured in semiconductor devices.

In addition, if the present invention is applied, the timing of the parasitic bipolar operation of the plurality of electrostatic discharge transistors can be made more uniform, and the efficiency of electrostatic discharge can be improved.

Claims (10)

A signal line connected between the input pad and the internal circuit; A plurality of NMOS transistors connected in parallel between the signal line and a ground power supply terminal; And A plurality of resistors connected between gate ends of adjacent NMOS transistors, the last resistor being connected between the gate of the NMOS transistor furthest from the input pad and the ground voltage terminal, A channel of each NMOS transistor is connected to the ground power supply terminal, and a static parasitic capacitance is present between the gate terminal of each NMOS transistor and the signal line. A signal line connected between the input pad and the internal circuit; A plurality of NMOS transistors connected in parallel between the signal line and a ground power supply terminal; And A plurality of resistors connected between gate ends of adjacent NMOS transistors, the last resistor being connected between the gate of the NMOS transistor furthest from the input pad and the ground voltage terminal, A pick-up area for applying ground power is disposed to be adjacent to the NMOS transistor closest to the input pad, and as the distance from the input pad increases, the ground voltage applied to the channel of each NMOS transistor gradually increases. And a parasitic capacitance is present between the gate terminal of each NMOS transistor and the signal line so as to be increased by a resistance value. The method according to claim 1 or 2, The last resistor is a static resistance circuit of the semiconductor device, characterized in that the variable resistor. delete The method according to claim 1 or 2, And each of the plurality of resistors is one selected from a gate electrode material, a wiring material, and a doped substrate of the plurality of NMOS transistors. delete delete delete The method according to claim 1 or 2, And said parasitic capacitance comprises gate-drain fringing capacitance and gate-drain overlap capacitance of each NMOS transistor. delete

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