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KR100602123B1 - Semiconductor device with multilayer wiring and method of manufacturing the same - Google Patents

Semiconductor device with multilayer wiring and method of manufacturing the same Download PDF

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KR100602123B1
KR100602123B1 KR1020040106141A KR20040106141A KR100602123B1 KR 100602123 B1 KR100602123 B1 KR 100602123B1 KR 1020040106141 A KR1020040106141 A KR 1020040106141A KR 20040106141 A KR20040106141 A KR 20040106141A KR 100602123 B1 KR100602123 B1 KR 100602123B1
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film
hole
impurity
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interlayer insulating
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김상권
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명의 목적은 반도체 소자의 다층 배선 공정을 단순화하고 제조 비용을 절감하는 것이다.It is an object of the present invention to simplify a multilayer wiring process of a semiconductor device and to reduce manufacturing cost.

본 발명에 따른 반도체 소자의 제조방법은 반도체 기판 상에 층간절연막으로 제 1 불순물 농도를 가지는 제 1 불순물 함유 산화막과, 제 1 불순물 농도보다 낮은 제 2 불순물 농도을 가지는 제 2 불순물 함유 산화막을 순차적으로 형성하는 단계; 층간절연막을 식각하여 기판을 노출시키는 콘택 형상의 제 1 홀을 형성하는 단계; 제 1 불순물 함유 산화막만을 측면 방향으로 선택적으로 제거하여 하부 배선홀과 콘택홀로 이루어진 제 2 홀을 형성하는 단계; 제 2 홀을 매립하도록 층간절연막 상에 금속막을 형성하는 단계; 및 층간절연막이 노출되도록 금속막을 평탄화하여 하부 배선과 콘택 플러그를 형성하는 단계를 포함한다.A method of manufacturing a semiconductor device according to the present invention is a method for forming a first impurity-containing oxide film having a first impurity concentration and a second impurity-containing oxide film having a second impurity concentration lower than the first impurity concentration ; Etching the interlayer insulating film to form a first hole having a contact shape to expose the substrate; Selectively removing only the first impurity-containing oxide film in a lateral direction to form a second hole composed of a lower wiring hole and a contact hole; Forming a metal film on the interlayer insulating film so as to fill the second hole; And planarizing the metal film so as to expose the interlayer insulating film to form the lower wiring and the contact plug.

다층 배선, 콘택 플러그, BPSG, 불순물 농도, 습식 세정Multilayer wiring, contact plug, BPSG, impurity concentration, wet cleaning

Description

다층 배선을 구비한 반도체 소자 및 그 제조방법{Semiconductor device having multilayered interconnection line and method of manufacturing the same}TECHNICAL FIELD [0001] The present invention relates to a semiconductor device having multilayer interconnection and a method of manufacturing the same.

도 1a 내지 도 1e는 종래 반도체 소자의 배선 형성방법을 설명하기 위한 순차적 공정 단면도.FIGS. 1A to 1E are sequential process sectional views for explaining a method of forming a wiring of a conventional semiconductor device.

도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 배선 형성방법을 설명하기 위한 순차적 공정 단면도.FIGS. 2A to 2F are sequential process sectional views for explaining a method of forming a wiring of a semiconductor device according to an embodiment of the present invention; FIGS.

본 발명은 반도체 소자 제조 기술에 관한 것으로, 특히 다층 배선을 구비한 반도체 소자 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly, to a semiconductor device having a multilayer wiring and a manufacturing method thereof.

일반적으로, 배선 기술은 집적회로(Integrated Circuit; IC)에서 트랜지스터의 상호 연결회로, 전원공급 및 신호전달의 통로를 구현하는 기술을 말한다.In general, wiring technology refers to a technology that implements the interconnecting circuit, power supply, and signaling path of a transistor in an integrated circuit (IC).

최근에는 반도체 소자의 고집적화에 의해 디자인룰(desigh rule)이 감소하고 메모리 셀들이 스택(stack) 구조화 되고 있다. 이에 따라, 각 셀들간의 전기적 연결을 위한 배선을 배선 설계가 자유롭고 배선 저항 및 전류 용량 등의 설정이 용이 하도록 다층으로 형성하고 있다.In recent years, the design rules (desigh rule) are reduced by the high integration of semiconductor devices and the memory cells are being stacked. As a result, the wiring for electrical connection between the cells is formed in multiple layers so that the wiring design can be freely designed and the wiring resistance and the current capacity can be easily set.

이러한 종래 반도체 소자의 배선 형성방법을 도 1a 내지 도 1e를 참조하여 설명한다.A conventional method of forming a wiring of a semiconductor device will be described with reference to Figs. 1A to 1E.

도 1a를 참조하면, 반도체 기판(10) 상에 제 1 금속막을 증착하고, 포토리소그라피 공정에 의해 제 1 금속막 상에 제 1 포토레지스트 패턴(미도시)을 형성한다. 여기서, 제 1 금속막은 알루미늄막으로 3000 내지 6000Å의 두께로 증착한다. 그 다음, 제 1 포토레지스트 패턴을 마스크로하여 건식식각 공정에 의해 제 1 금속막을 식각하여 하부 배선(20)을 형성하고, O2 가스 플라즈마를 이용한 에싱(ashing) 공정에 의해 제 1 포토레지스트 패턴을 제거한다.Referring to FIG. 1A, a first metal film is deposited on a semiconductor substrate 10, and a first photoresist pattern (not shown) is formed on the first metal film by a photolithography process. Here, the first metal film is deposited as an aluminum film to a thickness of 3000 to 6000 ANGSTROM. Next, the first metal film is etched by a dry etching process using the first photoresist pattern as a mask to form a lower wiring 20, and an ashing process using an O 2 gas plasma is performed to form a first photoresist pattern .

도 1b를 참조하면, 하부 배선(20)을 덮도록 기판(10) 전면 상에 층간절연막(30)을 형성하고, 포토리소그라피 공정에 의해 층간절연막(30) 상에 하부 배선(20) 위의 층간절연막(30)을 일부 노출시키는 제 2 포토레지스트 패턴(40)을 형성한다. 여기서, 층간절연막(30)은 유에스지(USG; Un-doped Silicate Glass)막, 비피에스(BPSG; BoroPhospho-Silicate Glass)막 또는 에프에스지(FSG; Fluorinated Silica Glass)막으로 7000 내지 10000Å의 두께로 형성한다.Referring to FIG. 1B, an interlayer insulating film 30 is formed on the entire surface of the substrate 10 so as to cover the lower interconnection 20, and an interlayer insulating film 30 is formed on the interlayer insulating film 30 by a photolithography process. A second photoresist pattern 40 for partially exposing the insulating film 30 is formed. The interlayer insulating film 30 may be formed of a material selected from the group consisting of an un-doped silicate glass (USG) film, a borophospho-silicate glass (BPSG) film, and a fluorinated silica glass (FSG) .

도 1c를 참조하면, 제 2 포토레지스트 패턴(40; 도 1b 참조)을 마스크로하여 건식식각에 의해 층간절연막(30)을 식각하여 하부 배선(20)을 노출시키는 콘택홀(50)을 형성한다. 그 후, O2 가스 플라즈마를 이용한 에싱 공정에 의해 제 2 포토레지스트 패턴(40)을 제거한다.Referring to FIG. 1C, the interlayer insulating film 30 is etched by dry etching using the second photoresist pattern 40 (see FIG. 1B) as a mask to form a contact hole 50 exposing the lower wiring 20 . Thereafter, the second photoresist pattern 40 is removed by an ashing process using an O 2 gas plasma.

도 1d를 참조하면, 콘택홀(50)을 매립하도록 층간절연막(30) 상에 제 2 금속막(60)을 증착한다. 여기서, 제 2 금속막(60)은 텅스텐막으로 증착한다.Referring to FIG. 1D, a second metal film 60 is deposited on the interlayer insulating film 30 so as to fill the contact hole 50. Here, the second metal film 60 is deposited with a tungsten film.

도 1e를 참조하면, 화학기계연마(Chemical Mechanical Polishing; CMP) 공정에 의해 층간절연막(30)이 노출되도록 제 2 금속막(60)의 평탄화를 수행하여 콘택 플러그(61)를 형성한다. Referring to FIG. 1E, the second metal film 60 is planarized to expose the interlayer insulating film 30 by a chemical mechanical polishing (CMP) process to form a contact plug 61.

그 후, 기판 전면 상에 제 3 금속막을 증착하고, 포토리소그라피 및 건식식각 공정에 의해 패터닝하여 콘택 플러그(61)를 통하여 하부 배선(20)과 전기적으로 연결되는 상부 배선(70)을 형성한다. 여기서, 제 3 금속막은 제 1 금속막(60)과 마찬가지로 알루미늄막으로 3000 내지 6000Å의 두께로 증착한다.Thereafter, a third metal film is deposited on the entire surface of the substrate, and patterned by a photolithography and a dry etching process to form an upper wiring 70 electrically connected to the lower wiring 20 through the contact plug 61. Here, the third metal film is deposited with an aluminum film to a thickness of 3000 to 6000 Å in the same manner as the first metal film 60.

그러나, 상술한 바와 같이 하부 배선(20)과 상부 배선(70)의 다층으로 배선을 형성하기 위해서는, 하부 배선(20)과 상부 배선(70) 형성을 위한 제 1 및 제 3 금속막의 증착, 포토리소그라피 및 식각공정 이외에도, 이들 사이의 전기적 연결을 위한 콘택 플러그(61) 형성을 위해 제 2 금속막의 증착 및 CMP 공정 등도 수행하여야 하므로, 공정이 복잡하고 제조 비용이 높아지는 문제가 있다.However, as described above, in order to form the wiring with the multilayer of the lower wiring 20 and the upper wiring 70, it is necessary to deposit the first and third metal films for forming the lower wiring 20 and the upper wiring 70, In addition to the lithography and etching processes, deposition of the second metal film and CMP process must also be performed in order to form the contact plugs 61 for electrical connection therebetween, which complicates the process and increases manufacturing costs.

또한, 이러한 문제는 배선의 층수가 증가할수록 더욱 더 심해지게 된다.This problem also becomes worse as the number of wiring layers increases.

본 발명은 상기와 같은 종래의 문제점을 해결하기 위한 것으로, 반도체 소자의 다층 배선 형성 공정을 단순화하고 제조 비용을 절감하는데 그 목적이 있다.It is an object of the present invention to simplify the process of forming a multilayer wiring of a semiconductor device and to reduce manufacturing cost.

상기한 바와 같은 본 발명의 목적을 달성하기 위하여, 본 발명에 따른 반도 체 소자는 반도체 기판; 기판 상에 형성되고 하부 배선홀과 콘택홀로 이루어진 홀을 구비하는 층간절연막; 및 하부 배선홀과 콘택홀에 매립되고 동일 금속막으로 이루어진 하부 배선 및 콘택 플러그를 포함하고, 층간절연막이 하부 배선 주변을 둘러싸면서 제 1 불순물 농도를 가지는 제 1 불순물 함유 산화막과, 콘택 플러그 주변을 둘러싸면서 제 1 불순물 농도보다 낮은 제 2 불순물 농도를 가지는 제 2 불순물 함유 산화막을 포함한다.According to an aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; An interlayer insulating film formed on a substrate and having a hole formed by a lower wiring hole and a contact hole; A first impurity-containing oxide film which is buried in the lower wiring hole and the contact hole and includes a lower wiring and a contact plug made of the same metal film, the interlayer insulating film surrounding the lower wiring and having a first impurity concentration, And a second impurity-containing oxide film surrounding the first impurity-containing oxide film and having a second impurity concentration lower than the first impurity concentration.

여기서, 제 1 및 제 2 불순물 함유 산화막은 각각 BPSG막으로 이루어지고,금속막은 텅스텐막으로 이루어진다.Here, each of the first and second impurity-containing oxide films is made of a BPSG film, and the metal film is made of a tungsten film.

상기한 바와 같은 본 발명의 목적을 달성하기 위하여, 본 발명에 따른 반도체 소자의 제조방법은 반도체 기판 상에 층간절연막으로 제 1 불순물 농도를 가지는 제 1 불순물 함유 산화막과, 제 1 불순물 농도보다 낮은 제 2 불순물 농도을 가지는 제 2 불순물 함유 산화막을 순차적으로 형성하는 단계; 층간절연막을 식각하여 기판을 노출시키는 콘택 형상의 제 1 홀을 형성하는 단계; 제 1 불순물 함유 산화막만을 측면 방향으로 선택적으로 제거하여 하부 배선홀과 콘택홀로 이루어진 제 2 홀을 형성하는 단계; 제 2 홀을 매립하도록 층간절연막 상에 금속막을 형성하는 단계; 및 층간절연막이 노출되도록 금속막을 평탄화하여 하부 배선과 콘택 플러그를 형성하는 단계를 포함한다.According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a first impurity-containing oxide film having a first impurity concentration and a second impurity- Forming a second impurity-containing oxide film having a second impurity concentration; Etching the interlayer insulating film to form a first hole having a contact shape to expose the substrate; Selectively removing only the first impurity-containing oxide film in a lateral direction to form a second hole composed of a lower wiring hole and a contact hole; Forming a metal film on the interlayer insulating film so as to fill the second hole; And planarizing the metal film so as to expose the interlayer insulating film to form the lower wiring and the contact plug.

여기서, 제 1 및 제 2 불순물 함유 산화막은 각각 BPSG막으로 이루어진다.Here, each of the first and second impurity-containing oxide films is made of a BPSG film.

또한, 제 2 홀을 형성하는 단계는 제 2 불순물 함유 산화막에 비해 제 1 불 순물 함유 산화막에서 식각 속도가 빠른 화학액, 바람직하게 TMH＋H2O2＋H2O을 이용한 습식 세정으로 수행한다. 이때, 화학액의 온도는 70 내지 80℃ 정도로 조절하고, 화학액의 TMH:H2O:H2O의 비율은 1:1:40으로 조절한다.The step of forming the second hole is performed by wet cleaning using a chemical solution having a high etching rate in the first impurity-containing oxide film, preferably TMH + H 2 O 2 + H 2 O, as compared with the second impurity-containing oxide film. At this time, the temperature of the chemical liquid is adjusted to about 70 to 80 ° C, and the ratio of TMH: H 2 O: H 2 O in the chemical liquid is adjusted to 1: 1: 40.

또한, 제 1 홀을 형성하는 단계는 CF4＋C5F8 가스 플라즈마를 이용한 건식식각 공정으로 수행하고, 금속막은 텅스텐막으로 형성한다.In addition, the step of forming the first hole is performed by a dry etching process using a CF 4 + C 5 F 8 gas plasma, and the metal film is formed of a tungsten film.

또한, 층간절연막을 형성하는 단계와 제 1 홀을 형성하는 단계 사이에, 600 내지 700℃의 온도에서 상기 기판을 열처리하는 단계를 더욱 포함할 수 있다.The method may further include a step of heat-treating the substrate at a temperature of 600 to 700 占 폚 between the step of forming the interlayer insulating film and the step of forming the first hole.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2f를 참조하여 본 발명의 실시예에 다른 반도체 소자의 배선 형성방법을 설명한다.A method of forming a wiring of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2F.

도 2a를 참조하면, 반도체 기판(110) 상에 층간절연막(120)으로 제 1 불순물 농도를 가지는 제 1 불순물 함유 산화막, 바람직하게 제 1 비피에스지(BPSG; BoroPhospho-Silicate Glass)막(121)과, 제 1 불순물 농도보다 낮은 제 2 불순물 농도를 가지는 제 2 불순물 함유 산화막, 바람직하게 제 2 BPSG막(122)을 순차적으로 형성한다. 2A, a first impurity-containing oxide film having a first impurity concentration, preferably a first BPSG (Borophospho-Silicate Glass) film 121, and a second impurity-containing oxide film 121 are formed on the semiconductor substrate 110, , A second impurity-containing oxide film having a second impurity concentration lower than the first impurity concentration, preferably a second BPSG film 122 are sequentially formed.

이때, 제 1 BPSG막(121)은 B와 P가 각각 5.0 이상의 불순물 농도를 가지고, 제 2 BPSG막(122)은 B와 P가 각각 4.5 이하의 불순물 농도를 가지는 것이 바람직하고, 층간절연막(120)은 7000 내지 9000Å의 두께를 가지는 것이 바람직하다.In this case, the first BPSG film 121 preferably has an impurity concentration of B and P of 5.0 or more, and the second BPSG film 122 preferably has an impurity concentration of 4.5 or less of B and P, ) Has a thickness of 7000 to 9000A.

즉, BPSG막은 불순물 농도에 따라 화학액에 대한 식각 속도가 다르기 때문에 불순물 농도 차이를 이용하면 원하는 부분만을 선택적으로 제거할 수 있다.That is, since the BPSG film has a different etch rate with respect to the chemical liquid depending on the impurity concentration, only the desired portion can be selectively removed by using the impurity concentration difference.

그 후, 600 내지 700℃의 온도에서 열처리를 수행하여 제 1 및 제 2 BPSG막(121, 122)을 리플로우(reflow)시켜 표면을 평탄화하고, 포토리소그라피 공정에 의해 층간절연막(120) 상부에 포토레지스트 패턴(130)을 형성한다.Thereafter, the first and second BPSG films 121 and 122 are reflowed by performing heat treatment at a temperature of 600 to 700 ° C to planarize the surface of the first and second BPSG films 121 and 122, and then, by a photolithography process, A photoresist pattern 130 is formed.

도 2b를 참조하면, 포토레지스트 패턴(130; 도 2a 참조)을 마스크로하여 건식식각 공정에 의해 층간절연막(120)을 식각하여 기판(110)을 일부 노출시키는 콘택 형상의 제 1 홀(140)을 형성한다. 여기서, 건식식각 공정은 CF4＋C5F8 가스 플라즈마를 이용하여 수행한다. 그 다음, O2 가스 플라즈마를 이용한 에싱 공정에 의해 포토레지스트 패턴(130)을 제거한다.Referring to FIG. 2B, the interlayer insulating layer 120 is etched by a dry etching process using the photoresist pattern 130 (see FIG. 2A) as a mask to form a first hole 140 having a contact shape for partially exposing the substrate 110, . Here, the dry etching process is performed using a CF 4 + C 5 F 8 gas plasma. Then, the photoresist pattern 130 is removed by an ashing process using an O 2 gas plasma.

그 후, 제 2 BPSG막(122)에 비해 제 1 BPSG막(121)에서 식각 속도가 빠른 화학액, 바람직하게 테트라 메틸 암모늄 하이드록사이드(Tetra Methyl Ammonium Hydroxide: TMH)＋H2O2＋H2O 화학액(chemical)을 이용하여 습식 세정을 수행한다. 그러면, 제 1 BPSG막(121)만이 측면 방향으로 선택적으로 제거되어 하부 배선홀(141a)과 콘택홀(141b)로 이루어져 단면 형상이 역 T 자 형상을 가지는 제 2 홀(141)이 형성된다.The first BPSG layer 121 is then exposed to a chemical solution having a higher etch rate, preferably Tetra Methyl Ammonium Hydroxide (TMH) + H 2 O 2 + H 2 O Perform wet cleaning using chemical liquid. Then, only the first BPSG film 121 is selectively removed in the lateral direction to form a second hole 141 having a lower wiring hole 141a and a contact hole 141b and having an inverted T-shaped cross-section.

이때, 화학액의 온도는 70 내지 80℃ 정도로 조절하고, 화학액의 TMH:H2O2:H2O의 비율은 1:1:40으로 조절한다.At this time, the temperature of the chemical liquid is adjusted to about 70 to 80 ° C, and the ratio of TMH: H 2 O 2 : H 2 O in the chemical liquid is adjusted to 1: 1: 40.

도 2d를 참조하면, 제 2 홀(141)을 매립하도록 층간절연막(120) 상에 제 1 금속막(150)을 증착한다. 여기서, 제 1 금속막(150)은 텅스텐막으로 증착한다. Referring to FIG. 2D, a first metal layer 150 is deposited on the interlayer insulating layer 120 to fill the second holes 141. Here, the first metal film 150 is deposited with a tungsten film.

도 2e에 도시된 바와 같이, 화학기계연마(Chemical Mechanical Polishing; CMP) 공정에 의해 층간절연막(120)이 노출되도록 제 1 금속막(150)의 평탄화를 수행하여 하부 배선(151a) 및 콘택 플러그(151b)를 형성한다.The first metal film 150 is planarized to expose the interlayer insulating film 120 by a chemical mechanical polishing (CMP) process so that the lower wiring 151a and the contact plugs 151b.

즉, 층간절연막(120)인 BPSG막의 불순물 농도를 다르게 하여 1회의 건식식각 공정과 1회의 습식 세정으로 층간절연막(120)에 하부 배선홀(141a)과 콘택홀(141b)로 이루어진 하나의 홀(141)을 형성하고, 콘택 플러그 형성 공정만으로 하부 배선(151a)과 콘택 플러그(151b)를 동시에 형성하므로, 하부 배선(151a) 형성을 위한 금속막의 증착, 포토리소그라피 및 식각 공정 등을 배제할 수 있다.That is, one impurity concentration of the BPSG film as the interlayer insulating film 120 is different, and one dry etching process and one wet scrubbing process are performed to form one hole (not shown) of the lower interconnection hole 141a and the contact hole 141b in the interlayer insulating film 120 The lower wiring 151a and the contact plug 151b are simultaneously formed only by the contact plug forming process so that the deposition of the metal film for forming the lower wiring 151a and the photolithography and etching processes can be eliminated .

도 2f에 도시된 바와 같이, 기판 전면 상에 제 2 금속막을 증착하고 포토리소그라피 공정 및 건식식각 공정에 의해 제 2 금속막을 패터닝하여, 콘택 플러그(151b)를 통하여 하부 배선(151a)과 전기적으로 연결되는 상부 배선(160)을 형성한다. 여기서, 제 2 금속막은 알루미늄막으로 3000 내지 6000Å의 두께로 증착한다.2F, a second metal film is deposited on the entire surface of the substrate, and the second metal film is patterned by a photolithography process and a dry etching process, so that the second metal film is electrically connected to the lower wiring 151a through the contact plug 151b The upper wiring 160 is formed. Here, the second metal film is deposited as an aluminum film to a thickness of 3000 to 6000A.

한편, 상기 실시예에서는 하부 배선(151a)과 상부 배선(160)의 2층 구조의 배선을 형성하는 경우에 대해서만 설명하였지만, 3층 이상의 배선 형성 시에도 동일하게 적용하여 실시할 수 있다.In the above embodiment, the case of forming the wiring of the two-layer structure of the lower wiring 151a and the upper wiring 160 has been described. However, the present invention can also be applied to the wiring of three or more layers.

상술한 바와 같이, 본 발명은 층간절연막인 BPSG막의 불순물 농도 차이를 이용하여 콘택 플러그 공정만으로 하부 배선과 콘택 플러그를 동시에 형성할 수 있다. As described above, the present invention can simultaneously form the lower wiring and the contact plug by only the contact plug process using the impurity concentration difference of the BPSG film as the interlayer insulating film.                     

이에 따라, 하부 배선 형성을 위한 금속막의 증착, 포토리소그라피 및 식각 공정 등을 배제할 수 있다.Accordingly, the deposition of the metal film for forming the lower wiring, the photolithography, and the etching process can be omitted.

그 결과, 다층 배선 형성 공정을 단순화할 수 있을 뿐만 아니라 제조 비용을 절감할 수 있다.As a result, not only the process of forming the multilayer wiring can be simplified, but also the manufacturing cost can be reduced.

이상에서 설명한 본 발명은 전술한 실시예 및 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be clear to those who have knowledge.

Claims (11)

반도체 기판;A semiconductor substrate; 상기 기판 상에 형성되고 하부 배선홀과 콘택홀로 이루어진 홀을 구비하는 층간절연막; 및 An interlayer insulating film formed on the substrate and including a hole formed by a lower wiring hole and a contact hole; And 상기 하부 배선홀과 상기 콘택홀에 매립되고 동일 금속막으로 이루어진 하부 배선 및 콘택 플러그를 포함하고, A lower wiring hole and a contact plug embedded in the contact hole and made of the same metal film, 상기 층간절연막이 상기 하부 배선 주변을 둘러싸면서 제 1 불순물 농도를 가지는 제 1 불순물 함유 산화막과, 상기 콘택 플러그 주변을 둘러싸면서 제 1 불순물 농도보다 낮은 제 2 불순물 농도를 가지는 제 2 불순물 함유 산화막을 포함하는 반도체 소자.Wherein the interlayer insulating film surrounds the lower wiring and includes a first impurity-containing oxide film having a first impurity concentration and a second impurity-containing oxide film surrounding the contact plug and having a second impurity concentration lower than the first impurity concentration . 제 1 항에 있어서, The method according to claim 1, 상기 제 1 및 제 2 불순물 함유 산화막은 각각 BPSG막으로 이루어진 반도체 소자.Wherein the first and second impurity-containing oxide films each comprise a BPSG film. 제 1 항에 있어서, The method according to claim 1, 상기 금속막은 텅스텐막으로 이루어진 반도체 소자.Wherein the metal film is made of a tungsten film. 반도체 기판 상에 층간절연막으로 제 1 불순물 농도를 가지는 제 1 불순물 함유 산화막과, 제 1 불순물 농도보다 낮은 제 2 불순물 농도을 가지는 제 2 불순물 함유 산화막을 순차적으로 형성하는 단계;Sequentially forming a first impurity-containing oxide film having a first impurity concentration as an interlayer insulating film and a second impurity-containing oxide film having a second impurity concentration lower than the first impurity concentration on a semiconductor substrate; 상기 층간절연막을 식각하여 상기 기판을 노출시키는 콘택 형상의 제 1 홀을 형성하는 단계;Etching the interlayer insulating film to form a first hole having a contact shape to expose the substrate; 상기 제 1 불순물 함유 산화막만을 측면 방향으로 선택적으로 제거하여 하부 배선홀과 콘택홀로 이루어진 제 2 홀을 형성하는 단계;Selectively removing only the first impurity-containing oxide film in a lateral direction to form a second hole composed of a lower wiring hole and a contact hole; 상기 제 2 홀을 매립하도록 상기 층간절연막 상에 금속막을 형성하는 단계; 및 Forming a metal film on the interlayer insulating film to fill the second hole; And 상기 층간절연막이 노출되도록 상기 금속막을 평탄화하여 하부 배선과 콘택 플러그를 형성하는 단계를 포함하는 반도체 소자의 제조방법.And planarizing the metal film so that the interlayer insulating film is exposed to form a contact plug with the lower interconnection. 제 4 항에 있어서, 5. The method of claim 4, 상기 제 1 및 제 2 불순물 함유 산화막은 각각 BPSG막으로 이루어진 반도체 소자의 제조방법.Wherein the first and second impurity-containing oxide films each comprise a BPSG film. 제 4 항 또는 제 5 항에 있어서, The method according to claim 4 or 5, 상기 제 2 홀을 형성하는 단계는 상기 제 2 불순물 함유 산화막에 비해 상기 제 1 불순물 함유 산화막에서 식각 속도가 빠른 화학액을 이용한 습식 세정으로 수행하는 반도체 소자의 제조방법.Wherein the forming of the second hole is performed by wet cleaning using a chemical liquid having a higher etching rate in the first impurity-containing oxide film than the second impurity-containing oxide film. 제 6 항에 있어서, The method according to claim 6, 상기 화학액으로 TMH＋H2O2＋H2O을 이용하는 반도체 소자의 제조방법. Wherein TMH + H 2 O 2 + H 2 O is used as the chemical solution. 제 7 항에 있어서, 8. The method of claim 7, 상기 화학액의 온도는 70 내지 80℃ 정도로 조절하고, 상기 화학액의 TMH:H2O:H2O의 비율은 1:1:40으로 조절하는 반도체 소자의 제조방법.Wherein the temperature of the chemical liquid is adjusted to about 70 to 80 ° C, and the ratio of TMH: H 2 O: H 2 O of the chemical liquid is adjusted to 1: 1: 40. 제 4 항 또는 제 5 항에 있어서, The method according to claim 4 or 5, 상기 제 1 홀을 형성하는 단계는 CF4＋C5F8 가스 플라즈마를 이용한 건식식각 공정으로 수행하는 반도체 소자의 제조방법.Wherein the forming of the first hole is performed by a dry etching process using CF 4 + C 5 F 8 gas plasma. 제 4 항에 있어서, 5. The method of claim 4, 상기 금속막은 텅스텐막으로 형성하는 반도체 소자의 제조방법.Wherein the metal film is formed of a tungsten film. 제 4 항 또는 제 5 항에 있어서, The method according to claim 4 or 5, 상기 층간절연막을 형성하는 단계와 상기 제 1 홀을 형성하는 단계 사이에, Between the step of forming the interlayer insulating film and the step of forming the first hole, 상기 600 내지 700℃의 온도에서 상기 기판을 열처리하는 단계를 더욱 포함하는 반도체 소자의 제조방법.Further comprising the step of heat-treating the substrate at a temperature of 600 to 700 ° C.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980006147A (en) * 1996-06-21 1998-03-30 김주용 Method of forming multi-layer metal wiring in semiconductor device
KR20020054709A (en) * 2000-12-28 2002-07-08 박종섭 Method for Forming Multi-layered electrode lines of a semiconductor device
KR20030049029A (en) * 2001-12-13 2003-06-25 아남반도체 주식회사 Fabrication method of semiconductor device
KR20030056157A (en) * 2001-12-27 2003-07-04 아남반도체 주식회사 Fabrication method of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980006147A (en) * 1996-06-21 1998-03-30 김주용 Method of forming multi-layer metal wiring in semiconductor device
KR20020054709A (en) * 2000-12-28 2002-07-08 박종섭 Method for Forming Multi-layered electrode lines of a semiconductor device
KR20030049029A (en) * 2001-12-13 2003-06-25 아남반도체 주식회사 Fabrication method of semiconductor device
KR20030056157A (en) * 2001-12-27 2003-07-04 아남반도체 주식회사 Fabrication method of semiconductor device

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