KR100630671B1 - Selective precharge method to reduce power consumption and lead-only memory device using the same - Google Patents

Abstract

An optional precharge method for reducing power consumption and a read only memory device using the same are disclosed. The read-only memory device of the present invention includes a memory cell array, a bit line selector, a virtual ground line selector, a precharge circuit and a discharge unit. The memory cell array is a memory cell array including a plurality of word lines, a plurality of virtual ground lines, and a plurality of bit lines, and is divided into a plurality of memory blocks. The bit line selector selects any one bit line among the plurality of bit lines. The virtual ground line selector selects any one of the plurality of virtual ground lines. The precharge circuit is a circuit which precharges a plurality of bit lines and a plurality of virtual ground lines to a predetermined precharge voltage level, and is provided for each memory block and controlled for each memory block. The discharge unit discharges the virtual ground lines to a predetermined virtual ground voltage level. By using the Prachage method of the present invention and the ROM device using the same, the power consumption in the precharge circuit is reduced. Thus, ultimately, the overall power consumption of the ROM device is reduced.

Description

Selective precharge method for lowering power consumption and read-only memory device using the same}

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram schematically illustrating a read only memory (ROM) device according to the related art.

2 is a block diagram schematically illustrating a ROM device according to an embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating the ROM device shown in FIG. 2 in detail.

4 is a circuit diagram illustrating a comparative example compared to an embodiment of the present invention illustrated in FIG. 3.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a read-only memory (ROM) device consuming low power and a precharge method therefor.

ROM devices are read-only memory devices, and are widely used in computers, portable devices, and the like. However, in recent years, the demand for ROM that consumes less power has increased, and research on this has been continuously made.

1 is a schematic block diagram of a ROM device according to the prior art. Referring to this, the ROM device according to the related art includes the memory cell array 10, the word line selection circuit 12, the bit line selection circuit 14, the precharge circuits 160 to 16k and the data output circuit 18. It is provided.

The memory cell array 10 includes a plurality of word lines WL0 to WLn in a row direction and a plurality of bit lines and a plurality of ground lines in a column direction. The memory cell is formed between a word line, a bit line, and a ground line, and binary information stored in the memory cell is read out through the bit line connected to the memory cell. Before this read operation is performed, it is necessary to precharge the bit line and the ground line to a constant voltage level. The memory cell array 10 may be divided into a plurality of bit lines and memory blocks 100 to 10k in units of a predetermined number of ground lines.

The word line selection circuit 12 and the bit line selection circuit 14 select word lines WL0 to WLn, bit lines, and ground lines to designate memory cells to be read.

The precharge of the bit line and the ground line is performed by the precharge circuits 160 to 16k provided for each of the memory blocks 100 to 10k. That is, in response to the predetermined precharge signal PREC, the precharge circuits 160 to 16k bring all the bit lines and the ground lines to the precharge voltage level. The precharge voltage level is usually the external supply voltage level. When the ROM device enters the read mode, the precharge is stopped, and when the read operation is completed, the precharge is performed again. Although not shown in detail, the precharge circuits 160 to 16k include a plurality of inverters. Therefore, power consumption in the precharge circuits 160 to 16k is large in the inversion operation.

However, in the ROM device according to the prior art, all precharge circuits 160 to 16k are uniformly controlled by the precharge signal PREC. Therefore, even if only one or a predetermined number of memory blocks perform a read operation, all precharge operations are stopped, and when the read operation is finished, all precharge operations are performed again. Therefore, power consumption by the inverters in the precharge circuits 160 to 16k is large due to the unnecessary switching of the precharge operation. Therefore, the ROM device according to the prior art has the disadvantage that the overall power consumption is increased.

The technical problem to be achieved by the present invention is to selectively control each precharge circuit in a ROM device having a precharge circuit for each memory block, thereby reducing power consumption in the precharge circuit and ultimately reducing overall power consumption. It is to provide a read-only memory device that reduces.

Another object of the present invention is to provide a precharge method performed in the read-only memory device of the present invention.

The present invention for achieving the above technical problem relates to a read-only semiconductor memory device. A read only memory device of the present invention is divided into a plurality of memory blocks, and includes a memory cell array including a plurality of word lines, a plurality of virtual ground lines, and a plurality of bit lines; A bit line selector configured to select one bit line among the plurality of bit lines; A virtual ground line selector configured to select one virtual ground line among the plurality of virtual ground lines; A precharge circuit for precharging the plurality of bit lines and the plurality of virtual ground lines to a predetermined precharge voltage level; And a discharge circuit for discharging the virtual ground lines to a predetermined virtual ground voltage level in response to an output signal of the virtual ground line selector. The precharge circuit may be provided for each of the memory blocks and controlled for each of the memory blocks. Preferably, the precharge circuit performs a precharge operation in response to a predetermined precharge signal and a predetermined selection signal, wherein the selection signal selects a memory block from which the read operation is performed. This is a signal generated internally for

The present invention for achieving the above technical problem is divided into a plurality of memory blocks, read-only memory having a memory cell array including a plurality of word lines, a plurality of virtual ground lines and a plurality of bit lines And a method for precharging the bit lines and the virtual ground lines in an apparatus. The precharge method may further include precharging all of the virtual ground lines and all of the bit lines to a predetermined precharge voltage level when the read-only memory device is not in a read mode; And when some of the plurality of memory blocks enter the read mode, stopping precharges for the virtual ground lines and the bit lines of the some memory blocks entering the read mode. . Preferably the precharge voltage level is a predetermined power supply voltage level.

In the ROM device of the present invention, each precharge circuit is selectively controlled, so that power consumption in the precharge circuit is reduced. Thus, ultimately, the overall power consumption of the ROM device is reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present specification, for the convenience of description, signals performing the same role through the drawings are denoted by the same reference numerals.

2 is a block diagram schematically illustrating a ROM device according to an embodiment of the present invention. Referring to this, a ROM device according to an embodiment of the present invention may include a memory cell array 20, a word line selection circuit 22, a plurality of bit line selection circuits 240 to 24k, and a plurality of precharge circuits 260. 26 k) and a data output circuit 28.

The memory cell array 20 is divided into k + 1 memory blocks 200 to 20k. The memory cell array 20 includes n + 1 word lines WL0, WL1, WL2,..., WLn in a column direction, and a plurality of bit lines and a plurality of virtual lines in a row direction. Ground lines (virtual ground lines).

The word line selection circuit 22 decodes a predetermined address signal ADDR, selects and drives one word line. Here, the address signal ADDR is preferably a row address signal.

The bit line selection circuits 240 to 24k perform a bit line selection function and a virtual ground line selection function. The bit line selection circuits 240 to 24k select one bit line in the corresponding memory block according to the predetermined address signal ADDR and each of the selection signals SEL0 to SELk, and one adjacent to the selected bit line. Select the ground line. The selection signals SEL0 to SELk are signals for selecting the memory blocks 200 to 20k. The address signal ADDR and the selection signals SEL0 to SELk may be signals obtained by decoding a column address signal. Accordingly, the ROM device of the present invention decodes a column address, and selects a signal SEL0 to SELk for selecting a memory block to be read from all memory blocks 200 to 20k, and bit lines and virtual in the selected memory block. A decoder unit (not shown) for generating an address signal ADDR for selecting a ground line may be further provided.

Precharge circuits 260 to 26k and bit line select circuits 240 to 24k are provided for each memory block 200 to 20k. The precharge circuits 260 to 26k perform or stop the precharge operation in response to the precharge signal PREC and the respective selection signals SEL0 to SELk. Therefore, by individually adjusting the selection signals SEL0 to SELk, it is possible to control the precharge operation for each memory block.                     

The data output circuit 28 receives data DO0 to DOk read from the selected memory cell and outputs the data to the outside through the data output terminal DQ. In the ROM device illustrated in FIG. 2, one bit of data may be output for each memory block 200 to 20k by one read operation, and the number of bits of data that can be simultaneously output to the outside of the ROM device is m. That is, m memory blocks can be selected at the same time, so that m data can be read simultaneously.

A detailed configuration and operation of the ROM device according to the exemplary embodiment of the present invention illustrated in FIG. 2 will be described with reference to FIG. 3.

3 illustrates one memory block 200, one precharge circuit 260, and one bit line selection circuit 240 in the ROM device of FIG. 2. In addition, the ROM device of FIG. 3 further includes a discharge unit 270. The memory block 200, the precharge circuit 260, and the bit line selection circuits 245 and 250 illustrated in FIG. 3 are the remaining memory blocks 201 to 20k and the precharge circuits 261 ˜ illustrated in FIG. 2. 26k) and bit line selection circuits 241 to 24k, respectively. The word line selection circuit 22 and data output circuit 28 of FIG. 2 are circuits well known to those skilled in the art, and thus are not specifically illustrated in FIG. 3.

The memory block 200 includes two n + 1 word lines WL0 to WLn, three virtual ground lines VG0, VG1 and VG2, and two virtual ground lines VG0, VG1 and VG2. It includes the bit lines BL0 and BL1. Each memory cell located between the word lines WL0 to WLn, the virtual ground lines VG0, VG1 and VG2 and the bit lines BL0 and BL1 may be implemented as a single cell transistor or may be blanked. Is processed. A cell transistor is an NMOS transistor whose gate is connected to one word line, and its drain and source are connected to one bit line and a virtual ground line, respectively, and a portion indicated by CT in FIG. 3 is one of the cell transistors. The cell transistor is formed to store a logic row. In order to store logic high, the corresponding memory cell is treated as a blank. In FIG. 3, the memory cell BK positioned between the word line WL1, the bit line BL0, and the virtual ground line VG1 is one of the blank cells.

The bit line select circuit 240 includes a bit line selector 245 and a virtual ground line selector 250. The bit line selection unit 245 selects one bit line in response to the predetermined bit line selection address AD_BL. The bit line selector 245 includes transmission gates TG1 and TG2 connected to the respective bit lines. The bit line selector 245 turns on one transfer gate according to the bit line select address AD_BL and turns off the other transfer gate so that the data loaded on the bit line connected to the turned on transfer gate is output data D0. To read). The bit line selection address AD_BL is a part of the address ADDC shown in FIG. 2.

The virtual ground line selector 250 selects one virtual ground line in response to the predetermined virtual ground selection addresses AD_VG0 to AD_VG2 and the selection signal SEL0. The virtual ground selector 250 is composed of logic elements. In the present embodiment, three negative logic sum means NOR1, NOR2, and NOR3 and an inverter INV2 are included. Each of the NOR means NOR1, NOR2, and NOR3 receives an address of one of the virtual ground selection addresses AD_VG0 to AD_VG2 and an inverted signal of the selection signal SEL0, and its output is output of the discharge unit 270. It is connected to the virtual ground lines VG0, VG1, and VG2 through charge transistors NM0, NM1, and NM2, respectively.

The discharge unit 270 includes first to third discharge transistors NM0, NM1, and NM2. The drains of the first to third discharge transistors NM0, NM1, and NM2 are connected to the virtual ground line, and the source thereof is connected to the ground voltage GND, and the gate thereof is the negative of the virtual ground selector 250. The outputs NOR1, NOR2, and NOR3 of the OR unit may be implemented as NMOS transistors to which the outputs are respectively applied. The discharge unit 270 discharges the virtual ground line selected by the virtual ground line selector 250 to the virtual ground voltage level. Here, the virtual ground voltage level is a ground voltage (GND) level.

The precharge circuit 260 includes a logic unit 262 and first to fifth precharge transistors PM0 to PM4. The first to fifth precharge transistors PM0 to PM4 have a source connected to the power supply voltage VCC, a drain thereof connected to one bit line, or one virtual ground line, and a logic to the gate. The output signal of the unit 262 may be implemented as a PMOS transistor. When the output signal of the logic unit 262 is 'low level', the first to fifth precharge transistors PM0 to PM4 are turned on to free the bit lines and the virtual ground lines to the power supply voltage VCC level. Charge it. When the output signal of the logic unit 262 is 'high level', the first to fifth precharge transistors PM0 to PM4 are turned off to stop the precharge for the bit lines and the virtual ground lines. .

The logic unit 262 is composed of a negative AND product NAND and an inverter INV1. As the negative AND product NAND, the precharge signal PREC and the selection signal SEL0 are input. Here, the selection signal SEL0 is a signal for selecting the memory block 200. Therefore, if any one of the precharge signal PREC and the selection signal SEL0 is 'low level', the output signal of the logic unit 262 becomes 'low level' and precharge is performed. When both the precharge signal PREC and the selection signal SEL0 are 'high level', the output signal of the logic unit 262 becomes 'high level' and the precharge is stopped.

In order to read data from the memory cell, the precharge must be stopped. After the read operation is completed, the precharge is performed again. However, the read operation is not performed on all the memory blocks at once. When the ROM device reads only one bit of data at a time, only one memory block performs a read operation. Therefore, only the precharge for the corresponding memory block is stopped and the precharge is performed again after the read operation is completed. If the ROM device outputs m bits of data at a time, for example, as described in FIG. 2, only the precharge for the m memory blocks may be stopped and precharged again after the read operation is completed.

In the ROM device of the present invention, the above-described selective precharge control is possible. That is, when the precharge is to be stopped and the read mode is operated, the precharge signal PREC is set to 'high level' and the selection signal SEL0 corresponding to the memory block 200 to be read is set to 'high'. Level ', only the precharge of the memory block 200 is stopped. At this time, since the select signals SEL1 to SELk corresponding to the other memory blocks 201 to 20k of FIG. 2 are all 'low level', the precharge for the remaining memory blocks (201 to 20k of FIG. 2) is not stopped. Do not.

A detailed operation of the ROM device shown in FIG. 3 is described as follows on the assumption that one memory cell is selected.

First, the second word line WL1 is formed by the word line select circuit 22 (22), the first bit line BL0 is formed by the bit line selector 245, and the virtual ground line selector 250 is used. Assume that the second virtual ground line VG1 is selected by. Then, the second word line WL1 is driven to a 'high level' by the word line selection circuit 22 of FIG. 2. The first transfer gate TG1 of the bit line selector 245 is turned on and the second transfer gate TG2 is turned off. The second discharge transistor NM1 of the discharge unit 270 connected to the second virtual ground line VG1 is turned on by the virtual ground line selector 250 to turn on the second virtual ground line VG1. It is discharged to this virtual ground voltage level.

However, the memory cell formed between the selected second word line WL1, the first bit line BL0, and the second virtual ground line VG1 is a blank BK. Accordingly, even when the second virtual ground line VG1 is selected and discharged to the virtual ground voltage level, the first bit line BL0 and the second virtual ground line VG1 are not connected to each other. BL0) maintains the precharge voltage VCC level. Therefore, 'high level' data is loaded on the first bit line BL0, and the 'high level' data is read as the output data DO through the first transfer gate TG1. The output data DO is output to the outside of the ROM device through the data output circuit (28 in FIG. 2).

Next, the second word line WL1 is formed by the word line selection circuit (22 in FIG. 2), the second bit line BL1 is formed by the bit line selection unit 245, and the virtual ground line selection unit ( It is assumed that the second virtual ground line VG1 is selected by 250. Then, the memory cell formed between the selected second word line WL1, the second bit line BL1, and the second virtual ground line VG1 is the cell transistor CT. Therefore, when the second virtual ground line VG1 is selected and discharged to the virtual ground voltage level, the second bit line BL1 connected to the second virtual ground line VG1 through the cell transistor CT may also be discharged. Discharged. Therefore, 'low level' data is loaded on the second bit line BL1, and the 'low level' data is read as the output data DO through the second transfer gate TG2. The output data DO is output to the outside of the ROM device through the data output circuit (28 in FIG. 2).

In the read operation as described above, the precharge signal PREC is shifted to the 'high level' to stop the precharge operation. In addition, the selection signal SEL0 corresponding to the memory block 200 in which the read operation is performed becomes 'high level'. Accordingly, only the precharge by the precharge circuit 260 that receives the selection signal SEL0 that is 'high level' is stopped, and the precharge operation by the remaining precharge circuits 261 to 26k in FIG. It is not interrupted. In this way, by selectively controlling the precharge for each memory block according to whether the memory block is read or not, power loss in the precharge circuit due to interruption and resumption of the precharge can be reduced. In particular, in the ROM device of the present invention, even if the number of columns (bit lines and virtual ground lines) is increased, the increase in power consumption by the precharge circuit is insignificant unless the number of bits (m) of data read out at the same time is increased. Do.

The effects of the present invention described above will become more apparent through the comparative examples described below.

Comparative example

FIG. 4 is a diagram for explaining a comparative example compared to the embodiment shown in FIG. 3, and is a circuit diagram illustrating a ROM device in which precharge is not selectively controlled.

The ROM device according to the comparative example also has a memory cell array including a plurality of memory blocks, a precharge circuit provided for each memory cell block, a bit line selection circuit, a word line selection circuit, and a data output circuit like the ROM device of the present invention. It is provided. In FIG. 4, as shown in FIG. 3, one memory block 300, a precharge circuit 360, bit line selection circuits 345 and 350, and a discharge unit 370 are illustrated.

The memory block 300, the bit line selection circuits 345 and 350, and the discharge unit 270 illustrated in FIG. 4 may include the memory block 200, the bit line selection circuits 245 and 250 and the disk shown in FIG. 3. Since the charge portion 270 and its configuration and function are the same, a detailed description thereof will be omitted.

The precharge circuit 360 illustrated in FIG. 4 includes two inverters INV1 and INV2 and first to fifth precharge transistors PM0 to PM4. Since the first to fifth precharge transistors PM0 to PM4 are the same as the first to fifth precharge transistors PM0 to PM4 illustrated in FIG. 3, a detailed description thereof will be omitted.

The precharge circuit 360 precharges the bit lines BL0 and BL1 and the virtual ground lines VG0, VG1 and VG2 to the power supply voltage VCC in response to the precharge signal PREC. Let's do it. However, unlike the precharge circuit 260 of the present invention, the precharge circuit 360 according to the comparative example responds only to the precharge signal PREC and thus cannot be selectively controlled for each memory block.

Therefore, when a read operation occurs in any one memory block, all precharge operations are stopped, and all precharge operations are resumed again after the read operation is terminated. Therefore, inversion at the inverters INV1 and INV2 included in the precharge circuit 360 is often required. The inverters INV1 and INV2 included in the precharge circuit 360 may include all the bit lines BL0 and BL1 and the virtual ground lines VG0, VG1 and VG2 connected to the precharge circuit 360. Are inverters of a relatively large size since they must be driven to a power supply voltage (VCC) level. Therefore, a large amount of current is consumed in the inverting operation of the inverters INV1 and INV2. Since the switching of the precharge operation is performed in all precharge circuits, power consumption in the precharge circuit increases. Moreover, as the number of columns (bit lines and virtual ground lines) in the ROM device of the comparative example increases, the power consumption in the precharge circuit also increases proportionally.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the optional precharge method of the present invention and the ROM device using the same, each precharge circuit is selectively controlled, so that power consumption in the precharge circuit is reduced. Thus, ultimately, the overall power consumption of the ROM device is reduced.

Claims (7)

A memory cell array divided into a plurality of memory blocks and including a plurality of word lines, a plurality of virtual ground lines, and a plurality of bit lines; A bit line selector configured to select one bit line among the plurality of bit lines; A virtual ground line selector configured to select one virtual ground line among the plurality of virtual ground lines; A precharge circuit for precharging the plurality of bit lines and the plurality of virtual ground lines to a predetermined precharge voltage level; And And a discharge circuit configured to discharge the virtual ground lines to a predetermined virtual ground voltage level in response to an output signal of the virtual ground line selector. The precharge circuit is provided for each of the memory blocks and controlled for each of the memory blocks. According to claim 1, The precharge circuit performs a precharge operation in response to a predetermined precharge signal and a predetermined selection signal, The selection signal may be a signal generated internally to select a memory block in which a read operation is to be performed among the memory blocks. 3. The precharge circuit of claim 2, wherein the precharge circuit When the read only memory device is not in the read mode, all of the virtual ground lines and all the bit lines are precharged to a predetermined precharge voltage level, and some of the plurality of memory blocks may enter the read mode. And stop precharging the virtual ground lines and the bit lines of some of the memory blocks entering the read mode. The method of claim 1, wherein the precharge voltage level is The read only memory device, characterized in that the predetermined power supply voltage level. The method of claim 1, wherein the virtual ground voltage level is A read only memory device, characterized in that the predetermined ground voltage level. The bit lines and the virtual ground in a read-only memory device divided into a plurality of memory blocks and including a memory cell array including a plurality of word lines, a plurality of virtual ground lines, and a plurality of bit lines. In a method of precharging lines, Precharging all of the virtual ground lines and all of the bit lines to a predetermined precharge voltage level when the read only memory device is not in a read mode; And And when some of the plurality of memory blocks enter the read mode, stopping precharge of virtual ground lines and bit lines of the some memory blocks entering the read mode. Precharge method in only memory device. The method of claim 6, wherein the precharge voltage level is A precharge method in a read-only memory device, characterized in that the predetermined power supply voltage level.

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