KR100631962B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to increase data retention time and to restrain effectively junction leakage current by forming a buried insulating spacer in a source region. A silicon substrate(200) having a gate(250) is prepared. A groove is formed by recessing a source forming region. An insulating layer is deposited on the resultant structure including the groove. An insulating spacer(280a) is then formed at the bottom of both sidewalls of the groove. Silicon is filled in the groove having the insulating spacer by selective epitaxial growth processing. Source/drain regions(290a,290b) are formed in the substrate.

Description

Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

1 is a cross-sectional view of a semiconductor device for explaining the problems of the prior art.

2A through 2E are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to an embodiment of the present invention.

3 is a cross-sectional view of a semiconductor device for explaining another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

200: silicon substrate 210: device isolation film

220: gate insulating film 230: gate conductive film

240: hard mask 250: gate

260: gate spacer 270: photoresist pattern

280: insulating film 280a: insulating spacer

290a: source region 290b: drain region

R: home

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of suppressing a junction leakage current.

As the integration of semiconductor devices increases, the channel length and junction area area of a cell transistor are decreasing, and the doping concentration of the channel and junction areas is increasing. As a result, a short channel effect in which the threshold voltage Vt decreases rapidly is induced, and an increase in leakage current due to an increase in an electric field is caused, resulting in deterioration of device characteristics.

In particular, the leakage current is mainly generated at the point where the channel and the junction region contact each other, because the electric field is concentrated at the junction point. This leakage current is called a junction leakage current, and the junction leakage current reduces the retention time of data stored in a capacitor contacted with a source region in a memory device, thereby shortening the refresh interval of the device and thus improving device characteristics. It will be adversely affected. Therefore, in order to improve the refresh characteristics in the highly integrated memory device, the above-described problem of increase in junction leakage current must be solved.

In detail, Figure 1 is a cross-sectional view showing a semiconductor device formed according to the prior art, with reference to this will be described the manufacturing method and problems.

First, the gate insulating layer 120, the gate conductive layer 130, and the hard mask layer 140 are sequentially formed on the silicon substrate 100 having the device isolation layer 110, and then the layers 140, 130, and 120 are formed. ) Is etched to form the gate 150.

Next, gate spacers 160 are formed on both sidewalls of the gate 150, and the source region 190a and the drain region 190b are formed in the substrate 100 on both sides of the gate 150 including the gate spacer 160. Forming a junction region 190 comprising a.

Subsequently, although not shown in the drawings, a subsequent known process is sequentially performed to manufacture a semiconductor device.

However, in the above-described prior art, as mentioned above, the junction leakage current generated at the point (region A) where the channel under the gate 150 and the source region 170a are in contact with each other increases according to the trend of higher integration. There is a problem that the refresh characteristics are deteriorated.

Recently, in order to solve the problem of increasing the junction leakage current, techniques for selectively lowering the doping concentration to the junction portion (region A) have been proposed. In this case, since the electric field concentration phenomenon of the junction part can be prevented to some extent, it is possible to suppress the junction leakage current and to improve the refresh characteristics. However, the above-described conventional doping concentration control method has a limitation in overcoming the problem of deterioration of the refresh characteristics due to electric field concentration and reduction of the junction area due to high integration. Therefore, in order to implement the next generation highly integrated memory device having high reliability, a technique for more reliably solving the problem of increased junction leakage current is required.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device that can effectively solve the problem of deterioration of refresh characteristics caused by an increase in the junction leakage current.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of providing a silicon substrate with a gate; Recessing a source forming region of the substrate to form a groove; Depositing an insulating film on the entire surface of the resultant including the groove; Anisotropically etching the insulating film to form insulating spacers at lower ends of both sidewalls of the groove; Filling the groove in which the insulating spacer is formed with silicon according to a selective epitaxial growth method; And forming a source / drain region in the gate both substrate surfaces.

Here, the groove is formed to a depth of 1000 ~ 2000Å.

The insulating spacer is formed of an oxide film or a nitride film, or a laminated film of an oxide film and a nitride film.

The insulating spacer is formed to be disposed at a depth of 300 to 800 Å from the substrate surface.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, after the silicon substrate 200 having the trench type isolation layer 210 is formed, a gate insulating layer 220 made of an oxide film is formed on the substrate 200 by thermal oxidation. Subsequently, a gate conductive film 230 including a doped polysilicon film and a tungsten silicide film is formed on the gate insulating film 220. Subsequently, a hard mask of a nitride film material is formed on the gate conductive film 230. A film 240 is deposited.

Then, the layers 240, 230, and 220 are sequentially etched to form several gates 250. Next, gate spacers 260 including an oxide film or a stacked film of an oxide film and a nitride film are formed on both sidewalls of the gate 250.

Referring to FIG. 2B, a photoresist pattern 270 for selectively exposing a source formation region of the substrate 200 is formed on a resultant of the substrate 200, and then the photoresist pattern 270, the gate 250, and the gate are formed. Using the spacer 260 as an etching mask, the source R region of the exposed substrate 200 is recessed by about 1000 to 2000 microns to form the groove R. As shown in FIG.

Referring to FIG. 2C, in a state where the photoresist pattern is removed, an insulating film 280 is deposited on the entire surface of the resultant including the groove R to a predetermined thickness. In this case, the insulating film 280 is composed of a single layer made of an oxide film or a nitride film, or a laminated film of an oxide film and a nitride film.

Referring to FIG. 2D, the insulating layer is excessively etched by an anisotropic etching method to form insulating spacers 280a at lower ends of both side walls of the grooves R. Referring to FIG. Here, the insulating spacer 280a is formed to be disposed at a depth of 300 to 800 Å from the surface of the substrate 200.

Referring to FIG. 2E, the groove R in which the insulating spacer 290a is formed is buried in the silicon substrate 200 with single-bond silicon of the same material according to the selective epitaxial growth (SEG). As a result, an insulating spacer 280a buried in the source forming region of the substrate 200 is formed.

Next, an impurity is implanted into the exposed substrate using the gate 250 including the gate spacer 260 as an ion implantation barrier, so that the source region (in the substrate region on both sides of the gate 250 including the gate spacer 260) is implanted. The junction region 290 including the 290a and the drain region 290b is formed.

Subsequently, although not shown, the semiconductor device of the present invention is completed by sequentially performing subsequent known processes.

As described above, the present invention forms an insulating spacer 280a buried in the source region 290a of the substrate so as to cover lower ends of both sides of the source region 290a. In this case, the insulating spacer 280a blocks the lower end of the junction point between the source region 290a and the channel region. As a result, the leakage current at the junction point between the source region 290a and the channel region is effectively suppressed. Therefore, the present invention can effectively prevent the problem of increasing the junction leakage current in the highly integrated memory device to increase the data retention time and improve the refresh characteristics.

In addition, the present invention forms the buried insulating spacer 280a so as to cover the lower end of the side of the source region 290a, which is a current between the source region 290a and the channel region through the upper end of the source region 290a. This is to secure the currency. That is, the present invention secures a current flow space on the upper side of the source region 290a for smooth current conduction between the source region 290a and the channel region, and forms an insulating spacer 280a at the lower portion of the source region 290a. ) And the channel region are blocked to suppress the occurrence of junction leakage current.

Meanwhile, in the above-described embodiment of the present invention, after the gate 250 and the gate spacer 260 are formed on the substrate 200 (FIG. 2A), the gate 250 and the photoresist pattern including the gate spacer 260 are formed. An insulating spacer 280a that selectively recesses the source forming region of the substrate 200 using 270 as an etching mask to form a groove R (FIG. 2B) and covers a lower portion of the sidewall of the groove R. 2D), but the embodiment of the present invention, after forming the gate 250 on the substrate 200, and before forming the gate spacer, By selectively recessing the source forming region using the photoresist pattern as an etch barrier, grooves R 'having a width wider than that of the grooves R of the above-described embodiment are formed, and then, both sidewalls of the grooves R' are formed. Forming an insulating spacer 280a at the lower end (see FIG. 3), and then It is also possible to form gate spacers on both side walls of the trench 250.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention forms an insulating spacer buried in the source region of the substrate to cover the lower ends of both sides of the source region, thereby electrically blocking the lower end of the junction point between the source region and the channel region to effectively suppress the generation of junction leakage current. can do. Accordingly, the present invention can increase the data retention time of the highly integrated memory device and improve the refresh characteristics.

Claims (4)

Providing a silicon substrate having a gate formed thereon; Recessing a source forming region of the substrate to form a groove; Depositing an insulating film on the entire surface of the resultant including the groove; Anisotropically etching the insulating film to form insulating spacers at lower ends of both sidewalls of the groove; Filling the groove in which the insulating spacer is formed with silicon according to a selective epitaxial growth method; And Forming a source / drain region on both of the gate surfaces of the substrate. The method of manufacturing a semiconductor device according to claim 1, wherein the groove is formed to a depth of 1000 to 2000 microns. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating spacer is formed of an oxide film or a nitride film, or a laminated film of an oxide film and a nitride film. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating spacer is formed to be disposed at a depth of 300 to 800 Å from the surface of the substrate.

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