KR100649741B1 - Polymer-ceramic dielectric compositions, embedded capacitors and printed circuit boards using the same - Google Patents
Polymer-ceramic dielectric compositions, embedded capacitors and printed circuit boards using the same Download PDFInfo
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Abstract
세라믹의 함량을 낮추면서도 높은 유전율을 확보할 수 있는 폴리머-세라믹의 유전체 조성물과 이를 이용하는 캐패시터와 인쇄회로기판이 제공된다.A dielectric composition of a polymer-ceramic capable of securing a high dielectric constant while lowering the content of a ceramic, and a capacitor and a printed circuit board using the same are provided.
폴리머-세라믹의 유전체 조성물은, The dielectric composition of the polymer-ceramic,
폴리머와 Polymer and
상기 폴리머에 분산되는 세라믹으로 조성되고,Is composed of a ceramic dispersed in the polymer,
상기 세라믹은 Sn산화물:30중량%이하, As산화물:30중량%이하, 나머지 Mn산화물로 조성되는 것을 포함하여 이루어진다. 내장형 캐패시터의 유전체층은 상기한 유전체 조성물로 이루어지며, 인쇄회로기판은 상기 캐패시터가 내장된 것이다. The ceramic is composed of Sn oxide: 30% by weight or less, As oxide: 30% by weight or less, comprising the remaining Mn oxide. The dielectric layer of the embedded capacitor is made of the above dielectric composition, and the printed circuit board is formed of the capacitor.
Description
미국특허공보 5,079,069, U.S. Patent Publication 5,079,069,
미국특허공보 5,261,153, U.S. Patent Publication 5,261,153,
미국특허공보 5,800,575,U.S. Patent Publication 5,800,575,
본 발명은 폴리머-세라믹의 유전체 조성물과 이를 이용하는 내장형 캐패시터와 캐패시터가 내장되는 인쇄회로기판에 관한 것이다. 보다, 상세하게는 세라믹의 함량을 낮추면서도 높은 유전율을 확보할 수 있는 폴리머-세라믹의 유전체 조성물과 이를 이용하는 캐패시터와 인쇄회로기판에 관한 것이다. The present invention relates to a dielectric composition of a polymer-ceramic, an embedded capacitor using the same, and a printed circuit board in which the capacitor is embedded. More particularly, the present invention relates to a dielectric composition of a polymer-ceramic capable of securing a high dielectric constant while lowering the content of a ceramic, and a capacitor and a printed circuit board using the same.
인쇄회로기판상에 탑재되던 각종 수동소자는 제품의 소형화에 큰 장애가 되고 있다. 특히, 반도체 능동소자가 점차 내장화되고 그 입출력단자수가 증가함에 따라 그 능소자 주위에 보다 많은 수동소자의 확보공간이 요구되고 있다. Various passive elements mounted on printed circuit boards are a major obstacle to miniaturization of products. In particular, as semiconductor active devices are increasingly embedded and the number of input / output terminals thereof increases, more space for securing passive devices around the necessity devices is required.
대표적인 수동소자로는 캐패시터가 있다. 캐패시터는 운용주파수의 고주파화에 따라 인덕턴스를 감소시키기 위하여 입력단자와 최 근접 거리에 배치되는 것이 유리하다.A typical passive element is a capacitor. The capacitor is advantageously disposed at the closest distance to the input terminal in order to reduce the inductance according to the high frequency of the operating frequency.
이러한 소형화와 고주파화의 요구를 충족시키기 위해 최근 내장형 캐패시터의 구현방안이 활발이 연구되고 있다. 내장형 캐패시터는 인쇄회로기판에 내장된 형태로서, 제품의 크기를 획기적으로 감소시킬 수 있다. 또한, 능동소자의 입력단자에 근접거리에 배치할 수 있으므로 도선길이를 최소화하여 유도인덕턴스를 크게 저감시킬 수 있으며, 고주파 노이즈 제거에도 유리하다. Recently, in order to meet the demand of miniaturization and high frequency, an implementation method of an embedded capacitor has been actively studied. Built-in capacitors are embedded in the printed circuit board, which can significantly reduce the size of the product. In addition, since it can be disposed in close proximity to the input terminal of the active element, the inductance can be greatly reduced by minimizing the lead length, and is also advantageous for removing high frequency noise.
내장형 캐패시터의 대표적인 예가 미국특허공보 5,079,069, 5,261,153, 5,800,575호에 제안되어 있다. 이들 특허는 미국의 산미나(sanmina)사가 제안한 기술로서, 인쇄회로기판(PCB)의 내층에 캐패시터 특성을 갖는 별도의 유전체층을 삽입하여 캐패시터를 구현하는 것으로, 유전체층은 FR4로 알려진 PCB자재를 이용하여도 특성이 구현된다고 알려져 있다. 요구하는 정전용량을 구현하기 위하여 유전체층으로서, 폴리머-세라믹의 유전체가 사용될 수 있다고 알려져 있다.Representative examples of embedded capacitors are proposed in US Pat. Nos. 5,079,069, 5,261,153, 5,800,575. These patents are proposed by Sanmina of the United States, and implement a capacitor by inserting a separate dielectric layer having a capacitor characteristic into an inner layer of a printed circuit board (PCB). The dielectric layer uses a PCB material known as FR4. It is known that the figure property is implemented. It is known that a dielectric of polymer-ceramic may be used as the dielectric layer to realize the required capacitance.
폴리머-세라믹의 유전체는 폴리머의 우수한 가공성과 세라믹의 높은 유전상수를 결합한 것이다. 이 유전체는 저온에서도 캐패시터를 형성할 수 있어 인쇄회로기판에 적용할 수 있다. 폴리머-세라믹의 유전체에서 매트리스가 되는 폴리머의 유전율이 매우 낮다. 따라서, 세라믹 분말의 유전율을 향상시켜도 직렬연결의 캐패시터 형태가 형성되어 전체 유전율은 유전율이 낮은 폴리머의 값에 지배되는 것이다. 높은 유전율의 재료를 만들기 위해서는 세라믹 분말의 비율을 높여야 한다. 그러나, 세라믹 분말의 비율은 인쇄회로기판의 적층공정상에서 허용하는 한계가 있어서 쉽게 높일 수 없다. 또한, 그 비율을 높이면 공정 특성이 떨어질 수 밖에 없는 한계가 있다. Polymer-ceramic dielectrics combine the good processability of polymers with the high dielectric constants of ceramics. This dielectric can form a capacitor even at low temperatures, and thus can be applied to printed circuit boards. The dielectric constant of the polymer that becomes the mattress in the polymer-ceramic dielectric is very low. Therefore, even if the dielectric constant of the ceramic powder is improved, the capacitor form of the series connection is formed so that the overall dielectric constant is governed by the value of the polymer having a low dielectric constant. In order to make materials of high dielectric constant, the ratio of ceramic powder must be increased. However, the ratio of ceramic powder cannot be easily increased because there is a limit that is allowed in the lamination process of the printed circuit board. In addition, if the ratio is increased, there is a limit that the process characteristics are inevitably deteriorated.
본 발명은 폴리머-세라믹의 유전체에서 세라믹 분말의 함량을 높이지 않아도 유전율을 발현할 수 있는 유전체 조성물을 제공하는데 그 목적이 있다. 또한, 이 유전체 조성물을 이용하는 캐패시터와 인쇄회로기판을 제공하는데도 또 다른 목적이 있다. SUMMARY OF THE INVENTION An object of the present invention is to provide a dielectric composition capable of expressing dielectric constant without increasing the content of ceramic powder in a polymer-ceramic dielectric. Another object is to provide a capacitor and a printed circuit board using the dielectric composition.
상기 목적을 달성하기 위한 본 발명의 폴리머-세라믹의 유전체 조성물은, The dielectric composition of the polymer-ceramic of the present invention for achieving the above object,
폴리머와 Polymer and
상기 폴리머에 분산되는 세라믹으로 조성되고,Is composed of a ceramic dispersed in the polymer,
상기 세라믹은 Sn산화물:30중량%이하, As산화물:30중량%이하, 나머지 Mn산화물로 조성되는 것을 포함하여 이루어진다. The ceramic is composed of Sn oxide: 30% by weight or less, As oxide: 30% by weight or less, comprising the remaining Mn oxide.
본 발명의 내장형 캐패시터는, The built-in capacitor of the present invention,
제1전극막과 제2전극막의 사이에 유전체 층을 구비하고, 상기 유전체 층은 폴리머와 A dielectric layer is provided between the first electrode film and the second electrode film, and the dielectric layer is formed of a polymer.
상기 폴리머에 분산되는 세라믹으로 조성되고,Is composed of a ceramic dispersed in the polymer,
상기 세라믹은 Sn산화물:30중량%이하, As산화물:30중량%이하, 나머지 Mn산화물로 조성되는 것을 포함하여 이루어진다. The ceramic is composed of Sn oxide: 30% by weight or less, As oxide: 30% by weight or less, comprising the remaining Mn oxide.
본 발명의 인쇄회로기판은, 캐패시터가 내장되는 것으로,In the printed circuit board of the present invention, a capacitor is incorporated,
캐패시터는 제1전극막과 제2전극막의 사이에 유전체 층을 구비하고, The capacitor includes a dielectric layer between the first electrode film and the second electrode film,
상기 유전체 층은 The dielectric layer is
폴리머와 Polymer and
상기 폴리머에 분산되는 세라믹으로 조성되고,Is composed of a ceramic dispersed in the polymer,
상기 세라믹은 Sn산화물:30중량%이하, As산화물:30중량%이하, 나머지 Mn산화물로 조성되는 것을 포함하여 이루어진다. The ceramic is composed of Sn oxide: 30% by weight or less, As oxide: 30% by weight or less, comprising the remaining Mn oxide.
본 발명의 세라믹에서 상기 Sn산화물은 5-20중량%이고, 상기 As산화물은 5-20중량%이며, 상기 As산화물과 Sn산화물의 비(Sn산화물/As산화물)는 1~3을 만족하는 것이 바람직하다. 본 발명에서 Sn산화물은 SnO2이고, 상기 As산화물은 As2O3이고, 상기 Mn산화물은 MnO2가 바람직하다. In the ceramic of the present invention, the Sn oxide is 5-20% by weight, the As oxide is 5-20% by weight, and the ratio (Sn oxide / As oxide) of the As oxide and Sn oxide satisfies 1 to 3. desirable. In the present invention, the Sn oxide is SnO 2 , the As oxide is As 2 O 3 , the Mn oxide is preferably MnO 2 .
또한, 본 발명의 폴리머-세라믹의 조성에서 상기 세라믹 10-70vol%이고, 나머지 폴리머로 조성되는 것이 바람직하다. 본 발명에서는 세라믹의 함량을 낮추더라도 유전특성이 확보되는 것으로, 상기 세라믹의 함량은 15-40vol%, 보다 바람직하게는 15-30vol%의 범위이고 나머지 폴리머로 조성된다. In addition, the composition of the polymer-ceramic of the present invention is preferably 10-70 vol% of the ceramic, and is composed of the remaining polymer. In the present invention, even if the content of the ceramic is lowered, dielectric properties are ensured. The content of the ceramic is in the range of 15-40 vol%, more preferably 15-30 vol%, and is composed of the remaining polymer.
본 발명에서 상기 폴리머는 에폭시, 폴리이미드, 폴리카보네이트, 폴리에틸렌, 폴리에틸렌테레프탈레이트, 폴리프로필렌, 폴리스티렌, 폴리페닐렌 옥사이드, 폴리에스터, 폴리아미드의 그룹에서 선택되는 적어도 어느 하나로 이루어지는 것이다. In the present invention, the polymer is at least one selected from the group consisting of epoxy, polyimide, polycarbonate, polyethylene, polyethylene terephthalate, polypropylene, polystyrene, polyphenylene oxide, polyester, and polyamide.
이하, 본 발명을 상세히 설명한다. Hereinafter, the present invention will be described in detail.
본 발명은 폴리머-세라믹의 유전체 조성물의 세라믹으로 Mn산화물계를 이용하면서, Mn산화물의 표면에 스페이스 챠지(space charge)를 발생시킬 수 있는 As산화물과 함께 Sn산화물을 사용하면 세라믹의 함량을 높게 하지 않더라도 유전율이 증가된다는 사실에 착안하여 완성된 것이다.The present invention does not increase the content of ceramics when Sn oxide is used together with As oxide which can generate a space charge on the surface of Mn oxide while using Mn oxide system as ceramic of the dielectric composition of polymer-ceramic. If not, it is completed by paying attention to the fact that the dielectric constant is increased.
본 발명에서는 폴리머-세라믹의 유전체에서 세라믹이 Sn산화물:30중량%이하, As산화물:30중량%이하, 나머지 Mn산화물로 조성된다.In the present invention, the ceramic in the dielectric of the polymer-ceramic is composed of Sn oxide: 30 wt% or less, As oxide: 30 wt% or less, and the remaining Mn oxide.
Mn은 +2, +3로 전이가 쉬운 물질이다. 이러한 Mn산화물에 첨가제를 사용할 경우, Mn은 가수가 다른 새로운 산화물 상을 생성하게 된다. 이 때 생성된 다른 가수의 Mn 산화물에 의해 스페이스 차지(space charge)가 발생하게 되고 이로 인해 겉보기 유전율을 증가시켜 유전특성이 향상된다. Mn is a substance easily transitioned to +2 and +3. When additives are used for these Mn oxides, Mn will form new oxide phases with different valences. At this time, a space charge is generated by the Mn oxide of the other valences generated, thereby increasing the apparent dielectric constant and improving the dielectric properties.
예를 들어 MnO2에 As2O3를 첨가하여 열처리 하면 Mn2As2O7과 Mn2O3가 새로이 생성된다. 이 때, 생성된 Mn2O3는 Mn의 가수가 +4가에서 +3가로 전이하게 된다. 이로 인해 스페이스 챠지가 발생하는 것이다. For example, when As 2 O 3 is added to MnO 2 and heat treated, Mn 2 As 2 O 7 and Mn 2 O 3 are newly formed. At this time, the generated Mn 2 O 3 transitions from the valence of +4 to +3. This causes a space charge.
본 발명에서는 이러한 측면을 고려하여 Mn산화물에 As산화물을 첨가하는 것이다. 이와 같이, Mn산화물의 가수 변화에 의해 유전상수의 증가는 또한 전도도의 증가를 함께 가져와 신뢰성에 영향을 미칠 수 있다. 그러므로 첨가할 수 있는 양이 한정되며, 이로 인해 유전율의 증가 정도도 한정되게 된다. Sn산화물은 As산화물이 Mn의 가수를 변경시켜 새로운 산화물을 생성하는 것과 다르게, MnO2의 옥타헤드럴의 홀 내로 침입형으로 존재한다. 이 경우에도 역시 스페이스 챠지를 발생하게 되나, 그 효과는 As 등의 산화물에 의한 것보다는 미미하다. 그러나, 그로 인한 손실의 증가 등도 적기 때문에 As와 동시 첨가하면 유전특성을 향상시킬 수 있다. In the present invention, the As oxide is added to the Mn oxide in consideration of this aspect. As such, an increase in dielectric constant due to a change in the valence of Mn oxide may also bring about an increase in conductivity, which may affect reliability. Therefore, the amount that can be added is limited, thereby limiting the degree of increase in permittivity. Sn oxides are invasive into the holes of the octahedral of MnO 2 , unlike As oxides altering the valence of Mn to produce new oxides. In this case, too, a space charge is generated, but the effect is less than that of an oxide such as As. However, due to the small increase in losses, etc., it is possible to improve the dielectric properties when added simultaneously with As.
본 발명에서는 As산화물과 Sn산화물의 상호작용을 고려하여 이들을 함께 사용하는데, 특징이 있다.In the present invention, in consideration of the interaction between the As oxide and the Sn oxide to use them together, there is a feature.
본 발명에서 Sn산화물은 30중량%이하, As산화물은 30중량%이하 포함되는 것이 바람 직하다. 보다 바람직하게는 Sn산화물의 함량은 5-20중량%, As산화물의 함량은 5-20중량%로 하는 것이다. 스페이스 챠지의 발생은 분극의 증가에 따라 유전상수의 증가를 가져오나, 유전손실 또한 높게 되고, 유전상수의 온도에 따른 변화특성인 TCC 특성이 나빠지게 되므로, 그 첨가량을 너무 높이는 것은 바람직하지 않다. 또한, 첨가제의 첨가량이 너무 적으면 원하는 유전특성을 얻을 수 없다. 그러므로 스페이스 차지의 발생 정도는 이러한 특성을 고려하여 상기한 범위로 As산화물과 Sn산화물을 첨가하는 것이 바람직하다. In the present invention, Sn oxide is preferably 30 wt% or less, and As oxide is preferably included 30 wt% or less. More preferably, the content of Sn oxide is 5-20% by weight, and the content of As oxide is 5-20% by weight. The occurrence of the space charge increases the dielectric constant with increasing polarization, but the dielectric loss is also high, and the TCC characteristic, which is a change characteristic according to the temperature of the dielectric constant, becomes worse, so it is not desirable to increase the addition amount too much. In addition, if the amount of the additive added is too small, desired dielectric properties cannot be obtained. Therefore, it is preferable to add As oxides and Sn oxides in the above-mentioned ranges in consideration of these characteristics.
As산화물과 Sn산화물의 비(Sn산화물/As산화물)는 1~3을 만족하는 것이 바람직하다. 상기 Sn산화물/As산화물의 비가 1미만일 경우, 이들 산화물의 복합 첨가에 의한 유전상수의 향상이 크지 않고, 3을 초과할 경우 앞서 언급한 스페이스 챠지 발생에 의한 유전손실특성의 저하 등이 생길 수 있다. It is preferable that the ratio (Sn oxide / As oxide) of As oxide and Sn oxide satisfy | fills 1-3. When the ratio of Sn oxide / As oxide is less than 1, the improvement of the dielectric constant due to the complex addition of these oxides is not significant, and if it exceeds 3, the dielectric loss characteristic may be reduced due to the above-mentioned space charge generation. .
본 발명에서 Mn산화물로서 MnO2가 이용되는 경우에는 새로운 산화물 상인 Mn2As2O7, Mn2O3상을 생성하기 위해서 As산화물은 As2O3를 이용하는 것이 바람직하다. In the present invention, when MnO 2 is used as the Mn oxide, As 2 O 3 is preferably used as the As oxide in order to generate new oxide phases Mn 2 As 2 O 7 and Mn 2 O 3 phases.
본 발명에서 Sn산화물은 Sn계 산화물이면 적용 가능하며, 가장 바람직하게는 SnO2이다. Sn oxide in the present invention can be applied if the Sn-based oxide, most preferably SnO 2 .
본 발명에서 세라믹은 상기와 같이 조성되는 분말을 600℃이상에서 하소 처리한 것 이다. 소결하지 않고 하소 처리한 것만으로도 충분한 유전특성을 나타낸다. In the present invention, the ceramic is calcined at 600 ° C or more of the powder formed as described above. Just calcination without sintering shows sufficient dielectric properties.
본 발명에 따라 폴리머-세라믹에서 세라믹은 10-70vol%이고, 나머지 폴리머로 조성되는 것이 바람직하다. 세라믹의 함량이 10%미만의 경우에는 충분한 유전율을 얻기가 어렵고, 70%초과의 경우에는 필강도(Peel strength)의 저하로 신뢰성 문제가 생길 수 있다. 폴리머-세라믹에서 세라믹의 함량이 높을수록 전기적 특성은 좋아진다. 본 발명에서는 세라믹의 비율을 낮출 수 있는 기술이므로, 그러한 측면을 고려할 때 세라믹은 15-40vol%, 보다 바람직하게는 15-35vol%의 범위로 하고 나머지 폴리머로 할 수 있는 장점이 있다.According to the invention the ceramic in the polymer-ceramic is 10-70 vol%, preferably composed of the remaining polymer. If the ceramic content is less than 10%, it is difficult to obtain sufficient permittivity, and in the case of more than 70%, reliability problems may occur due to a decrease in peel strength. The higher the ceramic content in the polymer-ceramic, the better the electrical properties. In the present invention, since the ratio of the ceramic can be lowered, in consideration of such aspects, the ceramic has an advantage of being in the range of 15-40 vol%, more preferably 15-35 vol%, and the remaining polymer.
본 발명에서 폴리머는 내장형 캐패시터에 사용되는 것이면 적용 가능하며, 그 대표적인 예로는 에폭시, 폴리이미드, 폴리카보네이트, 폴리에틸렌, 폴리에틸렌테레프탈레이트, 폴리프로필렌, 폴리스틸렌, 폴리펜닐렌 산화물, 폴리에스터, 폴리아미드의 그룹에서 선택되는 적어도 어느 하나로 이루어지는 것이다. In the present invention, the polymer may be applied as long as it is used in an embedded capacitor, and representative examples thereof include epoxy, polyimide, polycarbonate, polyethylene, polyethylene terephthalate, polypropylene, polystyrene, polyphenylene oxide, polyester, and polyamide. It is made of at least one selected from.
다음으로 본 발명의 유전체를 이용하는 내장형 캐패시터에 대해 설명한다.Next, a built-in capacitor using the dielectric of the present invention will be described.
캐패시터는 제1전극막과 제2전극막의 사이에 유전체층을 구비하는데, 이 유전체층에는 본 발명의 폴리머-세라믹 조성물이 사용된다.The capacitor includes a dielectric layer between the first electrode film and the second electrode film, wherein the polymer-ceramic composition of the present invention is used.
제1전극막과 제2전극막은 캐패시터에 적용되는 도전성 금속들이면 가능하며, 그 예 로는 Pt, Au, Ag, Cu, Ni, Pd 등이 있다. 전극막의 두께는 0.1~100㎛가 바람직하다. The first electrode film and the second electrode film may be conductive metals applied to the capacitor, and examples thereof include Pt, Au, Ag, Cu, Ni, and Pd. As for the thickness of an electrode film, 0.1-100 micrometers is preferable.
내장형 캐패시터의 제조방법은 먼저, 금속 전극의 호일상에 본 발명의 폴리머-세라믹의 슬러리를 형성하고, 경화처리하여 적층체를 얻는다. 폴리머-세라믹 슬러리의 형성은 캐스팅법 예를 들어 테이프 캐스팅법과 같은 방법을 이용할 수 있다. 다음으로, 상기 적층체의 유전체상부에 금속 전극의 호일을 압착하여 캐패시터를 제조할 수 있다. In the manufacturing method of the built-in capacitor, first, the slurry of the polymer-ceramic of the present invention is formed on the foil of the metal electrode and cured to obtain a laminate. The formation of the polymer-ceramic slurry may use a casting method such as a tape casting method. Next, the capacitor may be manufactured by pressing the foil of the metal electrode on the dielectric of the laminate.
또는, 폴리머-세라믹의 유전체가 형성된 금속호일의 적층체 두개를 유전체가 면접하도록 적층하여 압착하여 형성할 수도 있다. Alternatively, two laminates of metal foils having a polymer-ceramic dielectric formed thereon may be formed by laminating and compressing them so that the dielectrics are interviewed.
본 발명에 따라 제조되는 캐패시터는 인쇄회로기판에 내장된다.The capacitor manufactured according to the present invention is embedded in a printed circuit board.
인쇄회로기판의 캐패시터의 내장은 본 발명의 캐패시터를 폴리머의 기재상에 적층하여 형성하는 방법이 있다. 또는, 미국의 산미나사에 제안하는 방법(미국특허공보 5,079,069, 5,261,153, 5,800,575)과 같이 코어의 폴리머를 폴리머-세라믹의 유전체층으로 사용할 수도 있다. The built-in capacitor of a printed circuit board is a method of laminating the capacitor of the present invention on a polymer substrate. Alternatively, the polymer of the core may be used as the dielectric layer of the polymer-ceramic, such as the method proposed by Sanmin, USA (US Patent Publication Nos. 5,079,069, 5,261,153, 5,800,575).
이하, 실시예를 통하여 본 발명을 보다 구체적으로 설명한다.Hereinafter, the present invention will be described in more detail with reference to Examples.
[실시예]EXAMPLE
에탄올을 용매로 하고 지르코니아 볼을 사용하여 표 1의 발명예1, 2의 세라믹분말 을 12시간 볼밀하여 혼합하였다. 혼합한 분말을 200℃에서 12시간 건조한 후 700℃에서 하소하였다. 하소는 분당 5℃의 속도로 승온하고, 최종온도에서 24시간 유지한 후 로냉하였다. 열처리한 후 에탄올을 용매로 하고 지르코니아 볼을 사용하여 24시간 동안 분쇄하고 200℃에서 건조하였다.Ethanol was used as a solvent, and the ceramic powders of Inventive Examples 1 and 2 of Table 1 were ball milled for 12 hours using zirconia balls. The mixed powder was dried at 200 ° C. for 12 hours and then calcined at 700 ° C. The calcining was heated at a rate of 5 ° C. per minute, and then cooled at a final temperature for 24 hours. After the heat treatment, ethanol was used as a solvent, pulverized with zirconia balls for 24 hours, and dried at 200 ° C.
건조한 세라믹분말은 20vol%의 비스페놀A 수지(에폭시계)와 혼합하였다. 혼합은 비스페놀A수지와 경화제 및 분산제를 아세톤에서 혼합하고 여기에 세라믹분말을 배합하여 슬러리로 제조하는 방법을 이용하였다. 경화제로는 디시안 구아니딘를 비스페놀A:경화제 62:8.5중량비가 되도록 그리고 분산제로는 Re 610을 조성물의 0.01vol%로 배합하였다. 한편, 종래예1에 해당하는 BaTiO3의 분말은 발명예1,2와 마찬가지로 비스페놀A수지와 혼합하였다. The dry ceramic powder was mixed with 20 vol% bisphenol A resin (epoxy watch). In the mixing, a bisphenol A resin, a curing agent and a dispersant were mixed in acetone, and a ceramic powder was added thereto to prepare a slurry. Dicyane guanidine was added as a curing agent in a bisphenol A: hardening agent 62: 8.5 weight ratio, and Re 610 was added as 0.01 vol% of the composition as a dispersant. On the other hand, the powder of BaTiO 3 corresponding to the conventional example 1 was mixed with the bisphenol A resin in the same manner as the invention examples 1 and 2.
제조한 슬러리를 두께 35㎛의 동판상에 두께 100㎛로 도포하고, 170℃에서 20분으로 경화하여 유전체층을 제조하고, 그 위에 전극을 형성하여 캐패시터층을 제조하였다. 그후 1kHz에서 유전체층의 유전율 및 손실값을 임피던스 애널라이즈(HP4294A)를 이용하여 IPC-TM-650에 준하여 측정하였으며, 결과를 표 1에 나타내었다.The prepared slurry was applied on a copper plate having a thickness of 35 μm at a thickness of 100 μm, cured at 170 ° C. for 20 minutes to prepare a dielectric layer, and an electrode was formed thereon to prepare a capacitor layer. Then, the dielectric constant and loss value of the dielectric layer at 1 kHz were measured according to IPC-TM-650 using impedance analysis (HP4294A), and the results are shown in Table 1.
표 1에 나타난 바와 같이, 발명예1,2는 유전특성, 손실계수의 특성이 월등이 향상되는 것을 확인할 수 있다. 발명예1,2의 전기적특성은 종래의 유전체의 약 1.5배 정도 특성이 향상되고 있다. 발명예1,2의 전기적특성은 종래의 BaTiO3의 세라믹분말을 45~50% 정도 혼합하는 세라믹-폴리머의 유전체(유전율 약 20~25)의 전기적 특성에 필적하는 것이다. As shown in Table 1, Examples 1 and 2 of the invention, it can be seen that the characteristics of the dielectric properties, loss coefficient, etc. is improved. The electrical characteristics of Inventive Examples 1 and 2 are about 1.5 times higher than those of conventional dielectrics. The electrical characteristics of the inventive examples 1 and 2 are comparable to those of the ceramic-polymer dielectric (dielectric constants of about 20 to 25) in which 45 to 50% of conventional ceramic powders of BaTiO 3 are mixed.
본 발명에서 상기 실시형태는 하나의 예시로서, 본 발명이 여기에 한정되는 것은 아니다. 본 발명의 특허청구범위에 기재된 기술적 사상과 실질적으로 동일한 구성을 갖고 동일한 작용효과를 이루는 것은 어떠한 것이어도 본 발명의 기술적 범위에 포함된다. 예를 들어, 본 발명의 실시예에서는 폴리머로서 에폭시계인 비스페놀A 수지를 사용하고 있지만, 이외에도 내장형 캐패시터에서 사용되는 폴리머는 적용 가능하다. In the present invention, the above embodiment is only one example, and the present invention is not limited thereto. Any thing that has substantially the same structure and the same effect as the technical idea described in the claim of the present invention is included in the technical scope of this invention. For example, although the bisphenol A resin which is epoxy type is used as a polymer in the Example of this invention, the polymer used by a built-in capacitor is applicable also in addition.
상술한 바와 같이, 본 발명에 따르면 폴리머-세라믹 유전체에서 세라믹분말의 함량을 낮추면서도 높은 정전용량 값을 확보할 수 있어 인쇄회로기판의 제조공정에 적용될 수 있는 유용한 효과가 있는 것이다. As described above, according to the present invention, it is possible to secure a high capacitance value while lowering the content of ceramic powder in the polymer-ceramic dielectric, which is useful in that it can be applied to the manufacturing process of a printed circuit board.
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| US4090100A (en) | 1975-03-21 | 1978-05-16 | Owens-Illinois, Inc. | Gas discharge display device with protected dielectric |
| KR20000074172A (en) * | 1999-05-18 | 2000-12-05 | 구자홍 | Composition of Dielectric for Plasma Display Panel |
| KR20040067285A (en) * | 2003-01-22 | 2004-07-30 | 삼화콘덴서공업주식회사 | Dielectric ceramic composition with reinforced insulation glass frit and reinforced insulation glass frit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4090100A (en) | 1975-03-21 | 1978-05-16 | Owens-Illinois, Inc. | Gas discharge display device with protected dielectric |
| KR20000074172A (en) * | 1999-05-18 | 2000-12-05 | 구자홍 | Composition of Dielectric for Plasma Display Panel |
| KR20040067285A (en) * | 2003-01-22 | 2004-07-30 | 삼화콘덴서공업주식회사 | Dielectric ceramic composition with reinforced insulation glass frit and reinforced insulation glass frit |
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