KR100649861B1 - Image sensor manufacturing method - Google Patents

Abstract

The present invention is to provide a method of manufacturing an image sensor that can prevent the damage to the substrate caused by the removal of the hard mask when forming the gate electrode of the CMOS image sensor, the present invention for this purpose is a substrate defined by a pixel region and a logic region Depositing a gate conductive layer on the upper surface, depositing a hard mask functioning as an ion implantation prevention layer in an ion implantation process for forming a photodiode of the pixel region on the gate conductive layer, and etching the hard mask to Removing the hard mask of the logic region while forming a hard mask pattern in the pixel region, forming a photoresist pattern on the gate conductive layer of the logic region, the hard mask pattern and the photoresist pattern Etching the gate conductive layer through the pixel region Forming a photodiode in the pixel region by forming a gate electrode in the logic region, removing the photoresist pattern, and performing an ion implantation process using the hard mask pattern as an ion implantation prevention film; And applying a photoresist to cover the hard mask pattern and the gate electrode, etching the photoresist to expose an upper portion of the hard mask pattern, and removing the hard mask pattern. It provides a manufacturing method.

Description

Image sensor manufacturing method {METHOD FOR MANUFACTURING IMAGE SENSOR}

1A to 1F are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the prior art.

FIG. 2 is a SEM photograph showing substrate damage in an active region actually generated when forming a gate electrode of a CMOS image sensor according to the prior art. FIG.

3A to 3H are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to Embodiment 1 of the present invention.

4A to 4H are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to Embodiment 2 of the present invention.

<Description of the symbols for the main parts of the drawings>

10, 30, 50: substrate

12, 32, 52: polysilicon film

13, 33, 53: hard mask

15, 17, 20a, 35, 37, 40a, 55, 57, 60a: photoresist pattern

12a, 32a, 52a, 52b: gate electrode

13a, 33a, 53a: hard mask pattern

18, 38, 58: ion implantation process

20, 40, 60: photoresist

Logic: Logic Area Pixel: Pixel Area

The present invention relates to a method of manufacturing an image sensor, and more particularly, to a method of forming a gate electrode of a CMOS image sensor.

The image sensor is a semiconductor device that converts an optical image into an electrical signal, and the image sensor is mainly composed of a charge coupled device (hereinafter referred to as a CCD) and a CMOS (Complementary MOS) image sensor.

A CCD is a device in which charge carriers are stored and transported in a capacitor while individual metal-oxide-silicon (MOS) capacitors are in close proximity to each other.

On the other hand, the CMOS image sensor includes one photodiode and three or four transistors for driving a unit pixel in one unit pixel by applying a semiconductor CMOS process. Such a plurality of transistors constituting the CMOS image sensor are made up of a gate electrode and a source / drain like a transistor of a general memory device.

Hereinafter, a general CMOS image sensor manufacturing method will be described with reference to FIGS. 1A to 1F. Here, 'Pixel' is a pixel area in which at least one pixel is to be formed, and 'Logic' is a logic area in which other peripheral devices are to be formed.

First, as shown in FIG. 1A, a gate oxide layer (not shown) is formed on a semiconductor substrate 10 defined as a pixel region Pixel and a logic region Logic, and then a gate conductive layer is formed on the gate oxide layer. The polysilicon film 13 is deposited.

Subsequently, an oxide-based hard mask 13 is deposited on the polysilicon film 13. In this case, the hard mask 13 functions as an ion implantation prevention layer during a deep N ⁻ ion implantation process for forming a photodiode forming each unit pixel.

Next, a photo process is performed to form a predetermined photoresist pattern 15 on the hard mask 13. Here, the photoresist pattern 15 is used to define a gate electrode and is formed in a structure in which a part of the pixel area and the logic area Logic are opened.

Subsequently, as illustrated in FIG. 1B, an etching process using the photoresist pattern 15 (see FIG. 1A) as an etching mask is performed to form the hard mask 13, the polysilicon layer 12, and the gate oxide layer (not shown). Etch in turn. As a result, the hard mask pattern 13a and the gate electrode 12a are formed on the substrate 10 for each pixel region and logic region, respectively.

Subsequently, a strip process is performed to remove the photoresist pattern 15. Then, after the photo process is performed to form a separate photoresist pattern 17, the ion implantation process 18 for forming a photodiode is performed using the photoresist as a mask. In this case, the photoresist pattern 17 is used to define a photodiode and has a structure in which a region in which the photodiode is to be formed is opened in the pixel region Pixel. As a result, a photodiode (not shown) is formed in the substrate 10 of the pixel region Pixel.

Subsequently, as shown in FIG. 1C, the photoresist 20 is coated on the substrate 10 to cover the gate electrode 12a and the hard mask pattern 13a. For example, the photoresist 20 is applied to a thickness of 6000 ~ 10000Å.

However, when the photoresist 20 is applied in this manner, the height of the gate structure protruding above the substrate 10, that is, the stacked structure of the gate electrode 12a / hard mask pattern 13a is very high overall. The problem arises that the thickness of the resist 20 is not uniformly applied and its thickness is changed. For example, it can be seen that the photoresist 20 is applied at a relatively low level in the 'A' portion that is a boundary portion between the pixel region Pixel and the logic region Logic.

Subsequently, as illustrated in FIG. 1D, an etching process is performed to etch the photoresist 20 (refer to FIG. 1C) as a whole. As a result, an upper portion of the hard mask pattern 13a is exposed and a photoresist pattern 20a surrounding the gate electrode 12a is formed. In particular, during the etching process, all of the photoresist 20 of the 'A' portion, in which the thickness of the photoresist 20 is significantly thin, is removed and the substrate 10 at the bottom of the photoresist 20 is etched together. Damage to the substrate 10 occurs.

Subsequently, as shown in FIG. 1E, a wet etching process using a buffered oxide etchant (BOE) solution is performed to remove the hard mask patterns 13a (see FIG. 1D) exposed between the photoresist patterns 20a.

Subsequently, as shown in FIG. 1F, a strip process is performed to remove the photoresist pattern 20a (see FIG. 1E).

As a result, there is a problem in that substrate damage occurs in some regions when forming a gate electrode of the CMOS image sensor according to the related art. FIG. 2 is a scanning electron microscope (SEM) photograph showing substrate damage (see 'A' region) of an active region that is actually generated when a gate electrode of a CMOS image sensor is formed.

Accordingly, the present invention has been made to solve the above-described problems of the prior art, and provides an image sensor manufacturing method that can prevent substrate damage caused by removal of a hard mask when forming a gate electrode of a CMOS image sensor. There is a purpose.

According to an aspect of the present invention, there is provided a semiconductor device comprising: depositing a gate conductive layer on a substrate defined by a pixel region and a logic region, and implanting ions for forming a photodiode of the pixel region on the gate conductive layer; Depositing a hard mask functioning as an ion implantation prevention film during the process, removing the hard mask in the logic region while etching the hard mask to form a hard mask pattern in the pixel region, and Forming a photoresist pattern on the gate conductive layer, etching the gate conductive layer through the hard mask pattern and the photoresist pattern to form gate electrodes in the pixel region and the logic region, respectively; Removing the photoresist pattern, and removing the hard mask pattern. Forming a photodiode in the pixel region by performing an ion implantation process using an implant prevention layer, applying a photoresist to cover the hard mask pattern and the gate electrode, and exposing an upper portion of the hard mask pattern A method of manufacturing an image sensor includes etching a photoresist and removing the hard mask pattern.

In addition, the present invention according to another aspect to achieve the above object, the step of depositing a gate conductive film on the substrate defined by a pixel region and a logic region, and forming a photodiode of the pixel region on the gate conductive film Depositing a hard mask functioning as an ion implantation prevention film during an ion implantation process, and etching the hard mask and the gate conductive film of the pixel region in such a manner that the gate conductive film and the hard mask remain in the logic region. Forming a photodiode in the pixel region by forming a hard mask pattern and a first gate electrode in the pixel region, performing an ion implantation process using the hard mask pattern as an ion implantation prevention film, and performing the hard mask pattern Applying a photoresist to cover the; Etching the photoresist to expose a top of the pattern pattern, removing the hard mask pattern of the hard mask and the pixel region of the logic region, and etching the gate conductive layer of the logic region to etch the logic region. It provides a method of manufacturing an image sensor comprising the step of forming a second gate electrode.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example 1

3A to 3H are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to Embodiment 1 of the present invention. Hereinafter, 'Pixel' is a pixel area in which at least one unit pixel is to be formed, and 'Logic' is a logic area in which other peripheral elements are to be formed.

First, as shown in FIG. 3A, an oxide process is performed to form a gate oxide layer (not shown) on the semiconductor substrate 30 defined as a pixel region and a logic region, and then a gate conductive layer. The polysilicon film 32 is deposited. For example, the gate oxide film is formed to a thickness of 22 kPa, and the polysilicon film 32 is deposited to a thickness of 1500 to 2500 kPa. Preferably, it is deposited to a thickness of 2000 kPa.

Here, the polysilicon film 32 is formed of a doped or undoped silicon film. For example, in the case of an undoped silicon film, it is deposited by a low pressure chemical vapor deposition (LPCVD) method using SiH ₄ . On the other hand, in the case of the doped silicon film is deposited by LPCVD method using a gas mixed with PH ₃ , PCl ₅ , BCl ₃ or B ₂ H ₆ in SiH ₄ .

Subsequently, a hard mask 33 is formed on the polysilicon layer 32 to function as an ion implantation prevention layer in an ion implantation process for forming a photo diode of a pixel region. Here, the hard mask 33 is formed of an oxide film, which is formed to a thickness of 2500 ~ 3500Å. Preferably, the hard mask 33 is formed of an oxide film with a thickness of 3000 GPa.

In particular, the hard mask 33 is formed for use as an ion implantation prevention layer on the gate electrode of the transistor that is aligned on one side of the photodiode in the pixel region Pixel. When the photoresist pattern for forming the photodiode is formed, the gate electrode and the photoresist pattern are misaligned on one side of the photodiode, so that the photoresist pattern alone impurity ions on the gate electrode. This is because the injection cannot be completely blocked.

Next, a photoresist pattern 35 is formed on the hard mask 33 by performing a photo process. In this case, the photoresist pattern 35 is formed in a portion of the pixel area Pixel. In the ion implantation process for forming a photodiode, the hard mask 33 is left only in the pixel region in which the ion implantation prevention film is required, and the hard mask 33 in the logic region Logic, in which the ion implantation prevention film is unnecessary, is removed. This is to reduce the thickness of the gate structure protruding above the substrate 30 of the logic region Logic.

3B, the hard mask 33 (see FIG. 3A) is etched by performing an etching process using the photoresist pattern 35 (see FIG. 3A) as an etching mask. As a result, a hard mask pattern 33a is formed in the pixel area Pixel.

Subsequently, a strip process is performed to remove the photoresist pattern 35, and then a photo process is performed again to form another photoresist pattern 36. In this case, the photoresist pattern 36 is formed in a portion of the logic region Logic. This is to define a gate electrode in the logic region Logic.

Subsequently, as shown in FIG. 3C, an etching process using the photoresist pattern 36 (see FIG. 3B) of the logic region Logic and the hard mask pattern 33a of the pixel region Pixel is performed as an etching mask. The silicon film 32 (see FIG. 3B) and the gate oxide film (not shown) are etched. As a result, a plurality of gate electrodes 32a are formed on the substrate 30 of the pixel region Pixel and the logic region Logic.

Here, the etching process is performed using a mixed gas of Cl ₂ , HBr, HeO ₂ and N ₂ .

Next, a strip process is performed to remove the photoresist pattern 36. Thereafter, a cleaning process is performed to remove residues on the surface of the substrate 30.

Subsequently, as shown in FIG. 3D, a photo process is performed to form the photoresist pattern 37. The photoresist pattern 37 is used to define a photodiode and has a structure in which a part of the pixel region Pixel is opened.

Subsequently, an ion implantation process 38 using the photoresist pattern 37 as a mask is performed to form a photodiode (not shown) in the substrate 30 of the pixel region Pixel. For example, when the substrate 30 is doped with a P type, a deep N ^- ion implantation process is performed to form an N ^- diffusion region for a photodiode.

Subsequently, as shown in FIG. 3E, a strip process is performed to remove the photoresist pattern 37 (see FIG. 3D).

Subsequently, the photoresist 40 is coated on the substrate 30 to cover the gate electrode 32a and the hard mask pattern 33a. For example, the photoresist 40 is applied to a thickness of 6000 ~ 10000Å.

On the other hand, the height of the gate structure protruding above the substrate 30 in the pixel region Pix is about 5000 kPa. This is the sum of the thickness (2000 ns) of the gate electrode 32a and the thickness (3000 ns) of the hard mask pattern 33a.

In this case, since only the gate electrode 32a having a thickness of about 2000 μs protrudes above the substrate 30 in the logic region Logic except for this, the height of the gate structure protruding above the substrate 30 from the logic region Logic is increased. Is reduced. Therefore, when the photoresist 40 is applied, the photoresist 40 may be applied with a uniform thickness as a whole.

Subsequently, as illustrated in FIG. 3F, an etching process is performed to etch the photoresist 40 (see FIG. 3E) until the upper portion of the hard mask pattern 33a is exposed. As a result, an upper portion of the hard mask pattern 33a of the pixel area Pixel is exposed between the photoresist patterns 40a.

Here, the etching process proceeds until the thickness of the remaining photoresist pattern 40a becomes 1000 to 2000 mm 3.

In the etching process, since the photoresist 40 is uniformly coated as a whole, the photoresist 40 is etched by a predetermined thickness as a whole, and thus, the photoresist 40 is completely removed at a certain portion so that the photoresist 40 is completely removed. It is possible to prevent the bottom substrate 30 from being etched.

Subsequently, as illustrated in FIG. 3G, a wet etching process using a BOE solution is performed to remove the hard mask pattern 33a exposed between the photoresist patterns 40a. As a result, a silicide layer may be formed on the gate electrode 32a through a silicide process which will be subsequently performed to reduce the contact resistance of the gate electrode 32a.

Subsequently, as shown in FIG. 3H, a strip process is performed to remove the photoresist pattern 40a (see FIG. 3G).

Example 2

4A to 4H are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to Embodiment 2 of the present invention. Hereinafter, 'Pixel' is a pixel area in which at least one unit pixel is to be formed, and 'Logic' is a logic area in which other peripheral elements are to be formed.

First, as shown in FIG. 4A, an oxide process is performed to form a gate oxide layer (not shown) on a semiconductor substrate 50 defined as a pixel region and a logic region, and then a gate conductive layer. The polysilicon film 52 is deposited. For example, the gate oxide film is formed to a thickness of 22 kPa, and the polysilicon film 52 is deposited to a thickness of 1500 to 2500 kPa. Preferably, it is deposited to a thickness of 2000 kPa.

Here, the polysilicon film 52 is formed of a doped or undoped silicon film. For example, in the case of an undoped silicon film, it is deposited by a low pressure chemical vapor deposition (LPCVD) method using SiH ₄ . On the other hand, in the case of the doped silicon film is deposited by LPCVD method using a gas mixed with PH ₃ , PCl ₅ , BCl ₃ or B ₂ H ₆ in SiH ₄ .

Subsequently, a hard mask 53 which functions as an ion implantation prevention layer is deposited on the polysilicon layer 52 during an ion implantation process for forming a photo diode of a pixel region. Here, the hard mask 53 is formed of an oxide film, which is formed to a thickness of 2500 ~ 3500Å. Preferably, the hard mask 53 is formed by depositing an oxide film with a thickness of 3000 kPa.

Subsequently, a photoresist pattern 55 is formed on the hard mask 53 by performing a photo process. In this case, the photoresist pattern 55 may be formed to cover the entire logic region Logic and open a portion of the pixel region Pixel. The reason why the photoresist pattern 55 is formed in such a structure is to form a hard mask pattern only in a portion where an ion implantation prevention film is required in an ion implantation process for forming a photodiode.

Subsequently, as shown in FIG. 4B, an etching process using the photoresist pattern 55 (see FIG. 4A) as an etching mask is performed to form the hard mask 53, the polysilicon layer 52, and the gate oxide layer (not shown). Etch it. As a result, a hard mask pattern 53a and a plurality of gate electrodes 52a (hereinafter, referred to as first gate electrodes) are formed in the pixel region Pixel, and the hard mask 53 and the polysilicon film are formed in the logic region Logic. 52 and the gate oxide film remain as they are.

Here, the etching process is performed using a mixed gas of Cl ₂ , HBr, HeO ₂ and N ₂ . Subsequently, a strip process is performed to remove the photoresist pattern 55. A cleaning process is then performed to remove residues on the surface of the substrate 50.

Subsequently, as shown in FIG. 4C, a photo process is performed again to form a separate photoresist pattern 57. The photoresist pattern 57 is used to define a photodiode and has a structure in which a region in which the photodiode is to be formed is opened in the pixel region Pixel.

Subsequently, an ion implantation process 58 using the photoresist pattern 57 as a mask is performed to form a photodiode (not shown) in the substrate 50 of the pixel region Pixel. For example, when the substrate 50 is doped with a P type, a deep N ^- ion implantation process is performed to form an N ^- diffusion region for a photodiode.

Subsequently, as shown in FIG. 4D, a strip process is performed to remove the photoresist pattern 57 (see FIG. 4C).

Subsequently, the photoresist 60 is coated on the substrate 50 to cover the hard mask pattern 53a as a whole. For example, the photoresist 60 is applied to a thickness of 6000 ~ 10000Å.

When the photoresist 60 is applied, the polysilicon layer has the same height as the gate structure having the stacked structure of the first gate electrode 52a and the hard mask pattern 53a of the pixel region in the entire logic region Logic. Covered by a gate structure having a stack structure of the 52 and the hard mask 53, the photoresist 60 may be applied to the entire pixel area Pixel with a uniform thickness. Therefore, the photoresist 60 may cover the hard mask pattern 53a with a uniform thickness while filling the empty space between the first gate electrode 52a and the hard mask pattern 53a of the pixel region Pixel.

In general, since the area of the pixel region Pixel occupies 20-30% of the total area, the dense gate structure pattern formed in the logic region serves as an obstacle when applying the photoresist 60. Therefore, in Embodiment 2 of the present invention, the polysilicon layer 52 and the hard mask 53 are left over the logic region Logic to remove the dense gate structure pattern of the logic region Logic.

Next, as shown in FIG. 4E, an etching process is performed to etch the photoresist 60 (see FIG. 4D) until the upper portion of the hard mask pattern 53a is exposed. As a result, an upper portion of the hard mask pattern 53a of the pixel region Pixel and the logic region Logic is exposed between the photoresist patterns 60a.

In the etching process, since the photoresist 60 is uniformly coated on the whole, the photoresist 60 is etched by a predetermined thickness as a whole, and thus, the photoresist 60 is completely removed at a certain portion so that the photoresist 60 is completely removed. It is possible to prevent the bottom substrate 50 from being etched.

Subsequently, as shown in FIG. 4F, a wet etching process using a BOE solution is performed to remove the hard mask pattern 53a exposed between the photoresist patterns 60a. As a result, a silicide layer may be formed on the first gate electrode 52a through a silicide process to be performed subsequently to reduce the contact resistance of the first gate electrode 52a.

Subsequently, as shown in FIG. 4G, a strip process is performed to remove the photoresist pattern 60a. Then, the photoresist pattern 61 is formed by performing a photo process. The photoresist pattern 61 is used to define a gate electrode in the logic region Logic, and has a structure in which the entire pixel region Pixel is opened and a portion of the logic region Logic is opened.

Subsequently, as shown in FIG. 4H, an etching process using the photoresist pattern 60a (see FIG. 4G) as an etching mask is performed to form a polysilicon film 52 (see FIG. 4G) and a gate oxide film (in the logic region). Not shown). As a result, a plurality of gate electrodes 52b (hereinafter, referred to as second gate electrodes) are formed in the logic region Logic.

Here, the etching process is performed using a mixed gas of Cl ₂ , HBr, HeO ₂ and N ₂ . At this time, since a hard mask does not automatically exist on the second gate electrode 52b formed in the logic region Logic, a silicide layer is formed on the second gate electrode 52b through a silicide process that will be subsequently performed to form a second gate. The contact resistance of the electrode 52b can be reduced.

Subsequently, a strip process is performed to remove the photoresist pattern 60a (see FIG. 4G).

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, when the gate electrode of the image sensor is formed, the photoresist is applied between the gate electrodes with a uniform thickness, thereby etching the photoresist to expose the hard mask pattern on the gate electrode. In some parts of the process, the photoresist can be prevented from completely damaging the substrate of the photoresist bottom.

Therefore, it is possible to increase the reliability of the image sensor and to improve the yield by preventing leakage current.

Claims (15)

Depositing a gate conductive layer over the substrate defined by the pixel region and the logic region; Depositing a hard mask on the gate conductive layer to function as an ion implantation prevention layer in an ion implantation process for forming a photodiode in the pixel region; Removing the hard mask in the logic region by etching the hard mask to form a hard mask pattern in the pixel region; Forming a photoresist pattern on the gate conductive layer in the logic region; Etching the gate conductive layer through the hard mask pattern and the photoresist pattern to form gate electrodes in the pixel region and the logic region, respectively; Removing the photoresist pattern; Forming a photodiode in the pixel region by performing an ion implantation process using the hard mask pattern as an ion implantation prevention film; Applying a photoresist to cover the hard mask pattern and the gate electrode; Etching the photoresist such that an upper portion of the hard mask pattern is exposed; And Removing the hard mask pattern Image sensor manufacturing method comprising a. The method of claim 1, And the hard mask is formed of an oxide film. The method of claim 2, Removing the hard mask is an image sensor manufacturing method using a BOE solution. The method according to any one of claims 1 to 3, The hard mask is an image sensor manufacturing method to form a thickness of 2500 ~ 3500Å. The method of claim 4, wherein The gate conductive film is an image sensor manufacturing method to form a thickness of 1500 ~ 2500Å. The method of claim 5, The photoresist is an image sensor manufacturing method for applying a thickness of 6000 ~ 10000Å. The method of claim 6, The etching of the photoresist is performed until the photoresist remains at a thickness of 1000 ~ 2000Å. The method according to any one of claims 1 to 3, The etching of the gate conductive layer may be performed using a mixed gas of Cl ₂ , HBr, HeO ₂ and N ₂ gas. Depositing a gate conductive layer over the substrate defined by the pixel region and the logic region; Depositing a hard mask on the gate conductive layer to function as an ion implantation prevention layer in an ion implantation process for forming a photodiode in the pixel region; Etching the hard mask and the gate conductive layer of the pixel region in order so that the gate conductive layer and the hard mask remain in the logic region to form a hard mask pattern and a first gate electrode in the pixel region; Forming a photodiode in the pixel region by performing an ion implantation process using the hard mask pattern as an ion implantation prevention film; Applying a photoresist to cover the hard mask pattern; Etching the photoresist such that an upper portion of the hard mask pattern is exposed; Removing the hard mask of the logic region and the hard mask pattern of the pixel region; And Etching the gate conductive layer of the logic region to form a second gate electrode in the logic region Image sensor manufacturing method comprising a. The method of claim 9, And the hard mask is formed of an oxide film. The method of claim 10, Removing the hard mask is an image sensor manufacturing method using a BOE solution. The method according to any one of claims 9 to 11, The hard mask is an image sensor manufacturing method to form a thickness of 2500 ~ 3500Å. The method of claim 12, The gate conductive film is an image sensor manufacturing method to form a thickness of 1500 ~ 2500Å. The method of claim 13, The photoresist is an image sensor manufacturing method for applying a thickness of 6000 ~ 10000Å. The method according to any one of claims 9 to 11, The etching of the gate conductive layer may be performed using a mixed gas of Cl ₂ , HBr, HeO ₂ and N ₂ gas.

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