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KR100641086B1 - Scratch Prevention Method by Chemical Mechanical Polishing of Semiconductor Device - Google Patents

Scratch Prevention Method by Chemical Mechanical Polishing of Semiconductor Device Download PDF

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KR100641086B1
KR100641086B1 KR1020010006245A KR20010006245A KR100641086B1 KR 100641086 B1 KR100641086 B1 KR 100641086B1 KR 1020010006245 A KR1020010006245 A KR 1020010006245A KR 20010006245 A KR20010006245 A KR 20010006245A KR 100641086 B1 KR100641086 B1 KR 100641086B1
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slurry
polishing
wafer
chemical mechanical
mechanical polishing
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KR20020066062A (en
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류정선
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09G—POLISHING COMPOSITIONS; SKI WAXES
    • C09G1/00—Polishing compositions
    • C09G1/02—Polishing compositions containing abrasives or grinding agents
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

본 발명은 반도체소자의 화학기계적연마에 의한 스크래치 방지방법에 관한 것으로, 특히, 반도체 소자의 제조 공정에 있어서, 평탄화 방법 중 화학기계적연마 방법을 진행하는데는 화학적기계 연마를 위한 슬러리와 패드가 필요하며, 상기 슬러리는 균일도가 떨어지므로 웨이퍼의 연마 공정 전에 슬러리를 먼저 연마하여 슬러리의 균일도를 높여준 후에 웨이퍼를 연마하여 슬러리에 의한 스크래치를 방지하는 것을 특징으로 하여 반도체 소자의 특성, 신뢰성을 향상시키는 기술로 매우 유용하고 효과적인 장점을 지닌 발명에 관한 것이다.
The present invention relates to a method for preventing scratches by chemical mechanical polishing of a semiconductor device. In particular, in the manufacturing process of a semiconductor device, a slurry and a pad for chemical mechanical polishing are required for the chemical mechanical polishing method of the planarization method. Since the slurry is inferior in uniformity, the slurry is first polished before the wafer polishing process to increase the uniformity of the slurry, and then the wafer is polished to prevent scratches by the slurry. It relates to an invention with very useful and effective advantages.

슬러리, 스크래치, 화학기계적연마Slurry, Scratch, Chemical Mechanical Polishing

Description

반도체소자의 화학기계적연마에 의한 스크래치 방지방법{Method for holding of semiconductor device by chemical mechanical polishing} Method for preventing scratches by chemical mechanical polishing of semiconductor devices {Method for holding of semiconductor device by chemical mechanical polishing}             

도 1은 종래 반도체소자의 화학기계적연마방법에 의해 발생된 스크래치를 나타낸 단면도이다.1 is a cross-sectional view showing a scratch generated by a chemical mechanical polishing method of a conventional semiconductor device.

도 2a 내지 도 2c는 본 발명에 따른 반도체소자의 화학기계적연마에 의한 스크래치 방지방법을 설명하기 위한 구성도이다.2A to 2C are diagrams for explaining a scratch prevention method by chemical mechanical polishing of a semiconductor device according to the present invention.

도 3은 본 발명에 따른 반도체소자의 화학기계적연마에 의한 스크래치 방지방법에 따른 사용상태도이다.
Figure 3 is a state diagram used in the scratch prevention method by chemical mechanical polishing of the semiconductor device according to the present invention.

-- 도면의 주요부분에 대한 부호의 설명 -- -Explanation of symbols for the main parts of the drawing-

100 : 슬러리 저장고 110 : 슬러리100: slurry storage 110: slurry

120 : 슬러리 공급통로 130 : 연마제 지지대120: slurry supply passage 130: abrasive support

140 : 연마패드 150 : 웨이퍼 안치대140: polishing pad 150: wafer support

160 : 웨이퍼 170 : 연마된 슬러리
160: wafer 170: polished slurry

본 발명은 반도체소자의 화학기계적 연마에 의한 스크래치 방지방법에 관한 것으로, 보다 상세하게는 반도체 소자의 제조 공정에 있어서, 평탄화 방법 중 화학기계적연마 방법을 진행하는데는 화학기계적 연마를 위한 슬러리와 패드가 필요하며, 상기 슬러리는 균일도가 떨어지므로 웨이퍼의 연마 공정 전에 슬러리를 먼저 연마하여 슬러리의 균일도를 높여준 후에 웨이퍼를 연마하여 슬러리에 의한 스크래치를 방지할 수 있는 반도체소자의 화학기계적연마에 의한 스크래치 방지방법에 관한 것이다.The present invention relates to a method for preventing scratches by chemical mechanical polishing of semiconductor devices. More specifically, in the manufacturing process of semiconductor devices, the chemical mechanical polishing method of the planarization method includes a slurry and a pad for chemical mechanical polishing. Since the slurry is inferior in uniformity, a method of preventing scratches by chemical mechanical polishing of a semiconductor device capable of preventing scratches by polishing the wafer by polishing the slurry first to increase the uniformity of the slurry before polishing the wafer and then polishing the wafer. It is about.

최근 반도체 소자는 고집적화와 더불어 그 구조가 다층화되고 있다. 그 결과 각 층간의 패턴 유무에 따라 단차가 발생하므로, 반도체 소자의 제조공정 중에는 반도체 웨이퍼의 연마 공정이 필수적으로 포함된다. 이러한 연마공정에서는 주로 화학기계적 연마(CMP : Chemical Mechanical Polishing)방법이 사용되며, 이 방법은 국소적인 평탄화 뿐만 아니라 넓은 영역의 평탄화에 있어서도 평탄도(uniformity)가 우수하므로 웨이퍼가 대구경화되어 가는 추세에 적합하다. In recent years, semiconductor devices have been highly integrated and their structures have been multilayered. As a result, a step occurs depending on the presence or absence of patterns between the layers, and thus, the semiconductor wafer polishing step is essentially included in the manufacturing process of the semiconductor device. In this polishing process, a chemical mechanical polishing (CMP) method is mainly used. This method has excellent uniformity not only in localized planarization but also in a wide area, so that wafers are large-scaled. Suitable.

일반적인 화학기계적 연마방법은 텅스텐이나 산화물 등이 입혀진 웨이퍼를 연마패드라는 연마용 판위에 올린 상태에서 소정의 하중을 가하며 회전시킴으로써 기계적 마찰에 의한 웨이퍼의 연마가 이루어지게 하며, 동시에 연마패드와 웨이퍼 사이에 공급되는 슬러리(slurry)라는 화학적 연마제에 의한 웨이퍼의 연마가 이루어지게 하는 방법으로, 아주 미세한 연마를 가능하게 한다. In general, a chemical mechanical polishing method is to rotate a wafer coated with tungsten or oxide on a polishing plate called a polishing pad under a predetermined load, thereby rotating the wafer by mechanical friction, and at the same time between the polishing pad and the wafer. This method enables polishing of the wafer by a chemical abrasive called slurry, which enables very fine polishing.                         

그러나, 종래의 화학기계적연마 방법은 웨이퍼와 패드 사이에 슬러리를 공급하여 각 박막들을 연마하게 되는데, 이 경우 슬러리가 뭉치는 등 균일도에 문제가 있을 경우에는 도 1에 도시된 바와 같이, 웨이퍼 상에 스크래치를 발생시키기 때문에 반도체소자의 신뢰성 문제가 있었다.However, in the conventional chemical mechanical polishing method, each thin film is polished by supplying a slurry between the wafer and the pad. In this case, when there is a problem in uniformity such as agglomeration of the slurry, as shown in FIG. Since scratches are generated, there is a problem of reliability of the semiconductor device.

또한, 상기 문제를 해결하기 위해 슬러리를 웨이퍼에 공급할 때 필터링을 하기도 하나, 이런 용도의 필터는 매우 고가일 뿐만 아니라 사용 도중에 필터의 손상이 자주 발생되기 때문에 여전히 많은 스크래치와 이에 따른 신뢰성의 문제가 발생하는 문제점이 있었다.
In addition, in order to solve the above problem, the slurry is filtered when the wafer is supplied to the wafer, but the filter for this purpose is not only very expensive, but also frequently causes damage to the filter during use, which still causes a lot of scratches and thus reliability problems. There was a problem.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 반도체 소자의 제조 공정에 있어서, 평탄화 방법 중 화학기계적연마 방법을 진행하는데는 화학기계적 연마를 위한 슬러리와 패드가 필요하며, 상기 슬러리는 균일도가 떨어지므로 웨이퍼의 연마 공정 전에 슬러리를 먼저 연마하여 슬러리의 균일도를 높여준 후에 웨이퍼를 연마하여 슬러리에 의한 스크래치를 방지하도록 하는 것이 목적이다.
The present invention has been made to solve the above problems, an object of the present invention in the manufacturing process of the semiconductor device, in order to proceed the chemical mechanical polishing method of the planarization method requires a slurry and a pad for chemical mechanical polishing Since the slurry is inferior in uniformity, an object of the present invention is to grind the slurry prior to the polishing process of the wafer to increase the uniformity of the slurry, and then to polish the wafer to prevent scratches by the slurry.

상기 목적을 달성하기 위하여, 본 발명은 슬러리 공급장치에 슬러리를 채운 후에 슬러리를 연마제지지대 상부로 공급하는 단계와, 상기 공급된 슬러리를 연마 제지지대와 연마패드를 이용하여 연마하는 단계와, 상기 연마된 슬러리를 웨이퍼 상부에 공급하여 연마패드로 웨이퍼의 표면을 연마하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 화학기계적연마에 의한 스크래치 방지방법을 제공한다.In order to achieve the above object, the present invention is to fill the slurry in the slurry feeder and supplying the slurry to the abrasive support top, polishing the supplied slurry using the abrasive paper support and the polishing pad, and the polishing The method of claim 1 provides a method of preventing scratches by chemical mechanical polishing of a semiconductor device, comprising the step of supplying the prepared slurry to the upper part of the wafer and polishing the surface of the wafer with a polishing pad.

본 발명은 슬러리의 크기를 균일하게 하여 웨이퍼 화학기계적 연마 시에 웨이퍼에 스크래치 현상이 나타나는 것을 방지하여 반도체소자의 특성 및 신뢰성을 향상시키도록 하는 것을 특징으로 한다.
The present invention is characterized in that the size of the slurry is uniform to prevent scratches from appearing on the wafer during wafer chemical mechanical polishing to improve characteristics and reliability of the semiconductor device.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명에 따른 반도체소자의 화학기계적연마에 의한 스크래치 방지방법을 설명하기 위한 구성도이다.2A to 2C are diagrams for explaining a scratch prevention method by chemical mechanical polishing of a semiconductor device according to the present invention.

도 2a에 도시된 바와 같이, 슬러리 공급장치는 슬러리(110)를 저장하는 슬러리 저장고(100)와 상기 저장된 슬러리(110)를 연마장치에 공급하는 슬러리 공급통로(120)로 구성되어져 있다.As shown in FIG. 2A, the slurry supply apparatus includes a slurry reservoir 100 for storing the slurry 110 and a slurry supply passage 120 for supplying the stored slurry 110 to the polishing apparatus.

그리고, 도 2b에 도시된 바와 같이, 슬러리 연마장치는 상기 슬러리 공급통로를 통해 공급된 슬러리(110)를 받칠 수 있는 연마제지지대(130)와 상기 연마제지지대(130) 상부의 슬러리(110)를 연마하는 연마패드(140)로 구성되어져 있다.As shown in FIG. 2B, the slurry polishing apparatus polishes the abrasive support 130 capable of supporting the slurry 110 supplied through the slurry supply passage and the slurry 110 on the abrasive support 130. It is composed of a polishing pad 140.

이어서, 도 2c에 도시된 바와 같이, 웨이퍼 연마장치는 웨이퍼(160)를 장착하는 웨이퍼안치대(150)와 상기 연마된 슬러리(110)를 받칠 수 있는 웨이퍼(160)와 상기 웨이퍼(160) 상부의 슬러리(110)를 연마하는 연마패드(140)로 구성되어져 있다.Subsequently, as shown in FIG. 2C, the wafer polishing apparatus includes a wafer support 150 for mounting the wafer 160, a wafer 160 capable of supporting the polished slurry 110, and an upper portion of the wafer 160. It consists of the polishing pad 140 which grinds the slurry 110 of this.

도 3은 본 발명에 따른 반도체소자의 화학기계적연마에 의한 스크래치 방지방법에 따른 사용상태도이다.Figure 3 is a state diagram used in the scratch prevention method by the chemical mechanical polishing of the semiconductor device according to the present invention.

도 3에 도시된 바와 같이, 화학기계적연마 공정에 사용될 슬러리(110)를 슬러리 저장고(100)에 채운 다음 슬러리 공급통로(120)를 통하여 연마장치에 슬러리(110)를 공급한다.As shown in FIG. 3, the slurry 110 to be used in the chemical mechanical polishing process is filled in the slurry reservoir 100, and then the slurry 110 is supplied to the polishing apparatus through the slurry supply passage 120.

이때, 상기 슬러리(110)는 아교질의 SiO2, CeO2, Al2O3 및 MnO 2 물질 중 적어도 어느 하나 이상의 물질을 사용한다.In this case, the slurry 110 uses at least one of colloidal SiO 2 , CeO 2 , Al 2 O 3, and MnO 2 materials.

그리고, 상기 슬러리 공급통로(120)를 통하여 공급된 슬러리(110)를 연마제지지대(130) 상부에 올려놓고 연마지지대(130) 상부의 연마패드(140)와 연마제지지대(130)를 원형운동 또는 직선운동한다.Then, the slurry 110 supplied through the slurry supply passage 120 is placed on the abrasive support 130, and the polishing pad 140 and the abrasive support 130 on the abrasive support 130 are moved in a circular or straight line. Exercise.

그러므로, 상기 슬러리(110)는 0.05㎛∼0.5㎛ 정도의 크기로 균일하게 연마된다.Therefore, the slurry 110 is uniformly polished to a size of about 0.05㎛ ~ 0.5㎛.

이어서, 상기 연마된 슬러리(170)를 웨이퍼안치대(150)에 장착된 웨이퍼(160) 상부에 올려놓고 웨이퍼(160) 상부의 연마패드(140)와 웨이퍼안치대(150)를 원형운동 또는 직선운동하여 웨이퍼(160)를 연마한다.Subsequently, the polished slurry 170 is placed on the wafer 160 mounted on the wafer holder 150, and the polishing pad 140 and the wafer holder 150 on the wafer 160 are moved in a circular motion or a straight line. The wafer 160 is polished by movement.

이때, 상기 슬러리(110)의 연마 정도를 변화시켜, 슬러리 연마속도를 조절하는 경우에 있어서, 웨이퍼(160) 연마와 슬러리(110) 연마를 동시에 실시할 수 있다.
In this case, when the polishing degree of the slurry 110 is changed to adjust the slurry polishing rate, the polishing of the wafer 160 and the polishing of the slurry 110 may be simultaneously performed.

따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 화학기계적연마에 의한 스크래치 방지방법을 이용하게 되면, 화학기계적연마에 사용되는 슬러리의 균일도가 떨어지므로 웨이퍼의 연마 공정 전에 슬러리를 먼저 연마하여 슬러리의 균일도를 높여준 후에 웨이퍼를 연마하여 슬러리에 의한 스크래치를 방지하여 반도체소자의 특성 및 신뢰성을 향상 시키도록 하는 매우 유용하고 효과적인 발명이다.Therefore, as described above, if the scratch prevention method by chemical mechanical polishing of the semiconductor device according to the present invention is used, since the uniformity of the slurry used for chemical mechanical polishing is reduced, the slurry is first polished before the wafer polishing process. It is a very useful and effective invention to improve the characteristics and reliability of a semiconductor device by improving the uniformity of the wafer and then polishing the wafer to prevent scratching by the slurry.

Claims (5)

슬러리 공급장치에 슬러리를 채운 후에 슬러리를 연마체패드 상부로 공급하는 단계와;Supplying the slurry to the polishing pad after filling the slurry in the slurry supply device; 상기 공급된 슬러리를 연마제지지대와 연마패드를 이용하여 연마하는 단계와;Polishing the supplied slurry using an abrasive support and a polishing pad; 상기 연마된 슬러리를 웨이퍼 상부에 공급하여 웨이퍼와 연마패드를 이용하여 연마하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 화학기계적연마에 의한 스크래치 방지방법.And supplying the polished slurry to the upper portion of the wafer to polish the wafer using a wafer and a polishing pad. 제 1항에 있어서, 상기 슬러리는 아교질의 SiO2, CeO2, Al2O3 및 MnO2 물질 중 적어도 어느 하나 이상의 물질을 사용하는 것을 특징으로 하는 반도체소자의 화학기계적연마에 의한 스크래치 방지방법.The method of claim 1, wherein the slurry is made of at least one of colloidal SiO 2 , CeO 2 , Al 2 O 3, and MnO 2 materials. 제 1항에 있어서, 상기 슬러리 연마 공정은 연마패드와 연마제지지대를 원형운동 또는 직선운동을 이용하는 것을 특징으로 하는 반도체소자의 화학기계적연마에 의한 스크래치 방지방법.The method of claim 1, wherein the slurry polishing process is performed by chemical mechanical polishing of a semiconductor device using a circular motion or a linear motion of the polishing pad and the abrasive support. 제 1항 및 제 3항에 있어서, 상기 슬러리 연마 공정 시, 슬러리의 크기는 0.05㎛∼0.5㎛ 정도로 하는 것을 특징으로 하는 반도체소자의 화학기계적연마에 의한 스크래치 방지방법.4. The method of claim 1 and 3, wherein the slurry has a size of about 0.05 µm to 0.5 µm in the slurry polishing process. 제 1항에 있어서, 상기 슬러리의 연마 정도를 변화시켜, 슬러리 연마속도를 조절하는 할 때, 웨이퍼 연마와 슬러리 연마를 동시에 실시할 수 있는 것을 특징으로 하는 반도체소자의 화학기계적연마에 의한 스크래치 방지방법.The method of claim 1, wherein wafer polishing and slurry polishing can be performed simultaneously when the slurry polishing rate is adjusted by changing the polishing degree of the slurry. .
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