KR100642383B1 - Flash memory device having improved erase efficiency and manufacturing method thereof - Google Patents

Abstract

The flash memory device of the present invention includes a semiconductor substrate having a recessed region, a tunnel insulating film disposed on the semiconductor substrate of the recessed region, a floating gate electrode disposed to overlap with the sidewall of the recessed region on the tunnel insulating film, and floating. An inter-gate insulating film disposed over the gate electrode, a control gate electrode disposed over the inter-gate insulating film, and an impurity region disposed adjacent to the sidewall of the semiconductor substrate of the recess region.

Description

Flash memory device having improved erase efficiency and method of fabricating the same

1 is a cross-sectional view illustrating a conventional flash memory device.

2 is a cross-sectional view illustrating a flash memory device according to the present invention.

3 to 6 are cross-sectional views illustrating a method of manufacturing a flash memory device according to the present invention.

The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to a flash memory device having an improved erase efficiency and a method of manufacturing the same.

Among the semiconductor memory devices, the flash memory device does not lose information stored in the memory cell even when power is not supplied. Therefore, it is widely used for memory cards used in computers. As a unit cell of a flash memory device, a stacked gate structure having a structure in which a floating gate electrode and a control gate electrode are sequentially stacked is widely used.

1 is a cross-sectional view illustrating a conventional flash memory device having such a stacked gate structure.

Referring to FIG. 1, a gate stack is disposed above a channel region of a semiconductor substrate 100. The gate stack includes a tunnel oxide film pattern 110, a floating gate electrode pattern 120, an inter-gate insulating film pattern 130, a control gate electrode pattern 140, a metal silicide film pattern 150, and a hard mask film pattern 160. ) Are sequentially stacked. Gate spacer layers 170 are disposed on both sides of the gate stack, and the gate spacer layer 170 has a structure in which the oxide spacer 171 and the nitride spacer 172 are sequentially stacked. Source regions 181 and drain regions 182 are disposed at both sides of the channel region of the semiconductor substrate 100, respectively.

In such a conventional flash memory device, the erasing operation forms a high electric field between the control gate terminal and the source region 181, thereby trapping electrons trapped in the floating gate electrode pattern 120 in the source region. 181 by tunneling. Therefore, the erase efficiency of the flash memory device is affected by the width w at which the floating gate electrode pattern 120 and the source region 181 overlap each other.

Typically, the width w overlapping the floating gate electrode pattern 120 and the source region 181 is determined by an impurity ion implantation process and an impurity diffusion process for forming the source region 181. However, there is a limit to increase the overlapping area of the floating gate electrode pattern 120 and the source region 181 only by the conventional impurity ion implantation process and the impurity diffusion process, thus increasing the erase efficiency of the flash memory device. Indicates a limit.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a flash memory device capable of improving the efficiency of an erase operation by increasing an overlapping region of a floating gate electrode pattern and a source region.

Another object of the present invention is to provide a method of manufacturing the flash memory device as described above.

In order to achieve the above technical problem, a flash memory device according to the present invention, a semiconductor substrate having a recess region; A tunnel insulating film disposed on the semiconductor substrate in the recess region; A floating gate electrode disposed on the tunnel insulating layer to overlap a sidewall of the recess region; An inter-gate insulating film disposed on the floating gate electrode; A control gate electrode disposed on the inter-gate insulating film; And an impurity region disposed adjacent to a sidewall of the semiconductor substrate of the recess region.

The depth of the recess region is preferably 10-3000 mm.

In the present invention, a metal silicide layer disposed on the control gate electrode, an insulating hard mask layer disposed on the metal silicide layer, and the floating gate electrode, an inter-gate insulating layer, a control gate electrode, a metal silicide layer, and an insulating hard layer The insulating spacer film may be further disposed on sidewalls of the mask film.

In order to achieve the above another technical problem, a method of manufacturing a flash memory device according to the present invention, forming a recessed region of a predetermined depth on the semiconductor substrate; Forming a gate stack in which a tunnel insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode are sequentially stacked on the recess region; And forming an impurity region to be adjacent to a sidewall of the semiconductor substrate of the recess region.

The forming of the recess region may include forming a mask layer pattern having an opening on the semiconductor substrate to expose a surface on which the recess region is to be formed, and etching the semiconductor layer by etching using the mask layer pattern as an etch mask. The method may include removing the exposed surface of the substrate to a predetermined depth to form the recessed region, and removing the mask layer pattern.

In this case, the mask film pattern is preferably formed to a thickness of 10-5000Å.

The etching may be performed using a dry etching method.

The recessed region is preferably formed to have a depth of 10-3000 microns.

The floating gate electrode may be formed to overlap the entire sidewall of the recess region.

The present invention increases the efficiency of the erase operation by disposing a floating gate electrode pattern of a flash memory device in a recess region of a semiconductor substrate so that the overlapping area between the floating gate electrode pattern on the sidewall of the recess region and the source region is increased. Has its features. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a flash memory device according to the present invention.

Referring to FIG. 2, a flash memory device according to the present invention is formed on a semiconductor substrate 200 having a recess region 202. The depth of the recessed area 202 is approximately 10-3000 mm 3. The source region 281 and the drain region 282 are disposed in the upper region of the semiconductor substrate 200 on both sides of the recess region 202. Although not shown, the active region in which the cell transistor of the flash memory device is formed is separated from other device regions by an isolation layer (not shown). In addition, the semiconductor substrate 200 is a p-type substrate or has a p-type well region. In this case, the source region 281 and the drain region 282 have a high concentration of n-type, that is, n ⁺ -type conductivity.

The tunnel insulating layer 210 is disposed on the semiconductor substrate 200 of the recess region 202. The tunnel insulation film 210 is made of an oxide film. The floating gate electrode pattern 220, the inter-gate insulation layer pattern 230, the control gate electrode pattern 240, the metal silicide layer pattern 250, and the hard mask layer pattern 260 are sequentially disposed on the tunnel insulation layer 210. Configure the gate stack. The floating gate electrode pattern 220 and the control gate electrode pattern 240 are made of a polysilicon film. The inter-gate insulating film pattern 230 is formed of an oxide film, or an oxide film / nitride film / oxide film (ONO) film. The metal silicide film pattern 250 is formed of a tungsten silicide film. However, it is natural that similar membranes may be used in addition to the membranes. The gate spacer layer 270 is disposed on the sidewall of the gate stack. The gate spacer film 270 has a structure in which the oxide film 271 and the nitride film 272 are sequentially stacked.

In the flash memory device having such a structure, in the erase operation for erasing the stored data, a bias is applied so that a high electric field is formed between the gate terminal and the source terminal, and a trap is trapped in the floating gate electrode pattern 220. This is achieved by tunneling the electrons into the source region 281. In this case, as the overlapping portion of the floating gate electrode pattern 220 and the source region 281 becomes wider, tunneling of electrons can be made faster. In the case of the flash memory device according to the present invention, the floating gate electrode pattern 220 and the source region 281 overlap each other by the depth of the recess region 202, as indicated by "d1" in the drawing. Therefore, by adjusting the depth of the recess region 202, the overlapping area of the floating gate electrode pattern 220 and the source region 281 can be adjusted. As a result, the depth of the recess region 202 is greater than or equal to a predetermined size. The erase operation speed of the device can be increased.

3 to 6 are cross-sectional views illustrating a method of manufacturing a flash memory device according to the present invention.

First, referring to FIG. 3, a mask film pattern 300 is formed on a semiconductor substrate 200. Although not shown in the drawing, before forming the mask film pattern 300, a step of forming a p-type well region (not shown) in the semiconductor substrate 200 and a device isolation process for defining an active region are performed. The mask layer pattern 300 is formed of a polysilicon layer having a thickness of about 10-5000 microns and has an opening 310 that exposes a surface of a portion to be recessed of the semiconductor substrate 200.

Next, referring to FIG. 4, the semiconductor substrate 200 is etched to a predetermined depth d2 by performing an etching process using the mask film pattern 300 as an etching mask. Then, a recessed region 202 having a predetermined depth d2 is formed in the upper predetermined region of the semiconductor substrate 200. The depth d2 of the recess region 202 is set to approximately 10-3000 kPa. An etching process for forming the recess region 202 may be performed using a dry etching method. After the recess region 202 is formed, the mask layer pattern 300 is removed.

Next, referring to FIG. 5, a tunnel insulating film 212, a floating gate electrode film 222, an inter-gate insulating film 232, and a control gate electrode film 242 are formed on the semiconductor substrate 200 having the recess region 202. The metal silicide film 252 and the hard mask film 262 are sequentially stacked. The tunnel insulating film 212 is formed of an oxide film. The floating gate electrode film 222 and the control gate electrode film 242 are formed of a polysilicon film. The inter-gate insulating film 232 is formed of an oxide film or an oxide film / nitride film / oxide film. The metal silicide film 252 is formed of a tungsten silicide film. The hard mask film 262 is formed of a nitride film.

Next, referring to FIG. 6, the tunnel insulating film pattern 210, the floating gate electrode pattern 220, the inter-gate insulating film pattern 230, and the like are formed on the recess region 202 of the semiconductor substrate 200 by performing normal patterning. A gate stack in which the control gate electrode pattern 240, the metal silicide layer pattern 250, and the hard mask layer pattern 260 are sequentially stacked is formed. Referring to the process of forming the gate stack in more detail, first, a photoresist film pattern (not shown) exposing a part of the surface of the hard mask film 262 is formed on the hard mask film 262 of FIG. 5. Next, in the etching process using this photoresist film pattern as an etching mask, the hard mask film 262, the metal silicide film 252, the control gate electrode film 242, the inter-gate insulating film 232, and the floating gate electrode film ( The exposed portions of the 222 and the tunnel insulating film 212 are sequentially removed. After the gate stack is formed by the etching process, the photoresist film pattern is removed.

Next, a gate spacer layer 270 is formed on the sidewall of the gate stack protruding from the recess region 202 onto the semiconductor substrate 200. The gate spacer layer 270 may be formed by sequentially stacking the oxide layer 271 and the nitride layer 272, and then performing an etching process such as a conventional etch-back. Next, a normal ion implantation process is performed to form a source region 281 and a drain region 282 on the semiconductor substrate 200 on both sides of the recess region 202, as shown in FIG.

As described so far, according to the flash memory device and the manufacturing method thereof, the floating gate electrode pattern is disposed in the recess region of the semiconductor substrate so that the floating gate electrode pattern on the sidewall of the recess region overlaps the source region. By allowing the area to be increased, the erase operation speed can be increased, and the improvement of the characteristics provides the advantage of reducing the power consumption by reducing the operating voltage.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

Claims (9)

A semiconductor substrate having a recess region; A tunnel insulating film disposed on the semiconductor substrate in the recess region; A floating gate electrode disposed on the tunnel insulating layer to overlap a sidewall of the recess region; An inter-gate insulating film disposed on the floating gate electrode; A control gate electrode disposed on the inter-gate insulating film; And And an impurity region disposed adjacent to a sidewall of the semiconductor substrate of the recess region. The method of claim 1, And a depth of the recess region is 10-3000 microns. The method of claim 1, A metal silicide layer disposed on the control gate electrode; An insulating hard mask layer disposed on the metal silicide layer; And And an insulating spacer layer disposed on sidewalls of the floating gate electrode, the inter-gate insulating layer, the control gate electrode, the metal silicide layer, and the insulating hard mask layer. Forming a recessed region of a predetermined depth in the semiconductor substrate; Forming a gate stack in which a tunnel insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode are sequentially stacked on the recess region; And And forming an impurity region adjacent to a sidewall of the semiconductor substrate of the recess region. The method of claim 4, wherein the forming of the recess region comprises: Forming a mask layer pattern on the semiconductor substrate, the mask layer pattern having an opening exposing a surface on which the recess region is to be formed; Forming the recess region by removing the exposed surface of the semiconductor substrate to a predetermined depth by etching using the mask layer pattern as an etching mask; And And removing the mask layer pattern. The method of claim 5, The mask film pattern is a method of manufacturing a flash memory device, characterized in that formed in a thickness of 10-5000Å. The method of claim 5, The etching is a method of manufacturing a flash memory device, characterized in that performed using a dry etching method. The method of claim 4, wherein The recessed area is formed to have a depth of 10-3000Å. The method of claim 4, wherein And forming the floating gate electrode to overlap the entire sidewall of the recess region.

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