KR100652374B1 - Semiconductor Multi Chip Package and Manufacturing Method Thereof - Google Patents

Abstract

A semiconductor multichip package and a method of manufacturing the same are disclosed. The multichip package according to the present invention includes a package substrate, which has a connection terminal disposed thereon. The first chip includes a center bonding pad formed on its substantially central portion. The first chip is disposed on the package substrate. The insulating support structure is formed to be located outside of the bonding pad on the first chip. One of the connection terminals and one or more of the center bonding pads are electrically connected by bonding wires. The second chip is disposed above the bonding pads and lies on the insulating support structure.

Description

Semiconductor multi-chip package and fabrication method for the same

1A is a plan view illustrating a center pad semiconductor chip according to the related art.

1B is a plan view illustrating a peripheral pad type semiconductor chip according to the related art.

2 is a cross-sectional view of a multi-chip package according to the prior art including a peripheral pad-type semiconductor chip.

3 is a cross-sectional view of a multi-chip package according to the prior art including a center pad type semiconductor chip rearranged by a peripheral bonding pad.

4 is a plan view of a semiconductor chip according to the prior art having bonding pads rearranged from a central region to a peripheral region.

5 is a cross-sectional view of a prior art semiconductor chip having bonding pads repositioned from a central region to a peripheral region.

6 through 12 are cross-sectional views illustrating a method of manufacturing a semiconductor multi-chip package according to an embodiment of the present invention.

13 is a cross-sectional view of an insulating support structure according to another embodiment of the present invention.

14A is a plan view illustrating a semiconductor chip included in a multi-chip package according to an aspect of the present invention and having an insulating support structure disposed thereon.

14B is a plan view illustrating a semiconductor chip included in a multi-chip package according to another aspect of the present invention and having an insulating support structure disposed thereon.

15 is a plan view of a wafer level package according to another embodiment of the present invention.

FIG. 16 is a plan view of a screen mask used to fabricate a wafer level package having the structure shown in FIG. 15.

17 is a cross-sectional view illustrating a semiconductor multi-chip package according to another embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a semiconductor multichip package and a method of manufacturing the same.

In general, semiconductor chips have a center pads configuration or a peripheral pad configuration. A semiconductor chip having a center pad configuration (hereinafter, referred to as a “center pad semiconductor chip”) refers to a bonding pad 12 formed on a center region of the chip, and has a semiconductor chip having a peripheral pad configuration. (Hereinafter referred to as a peripheral pad type semiconductor chip) means that the bonding pads 14 are formed on the peripheral region of the chip. 1A is a plan view of a center pad type semiconductor chip, and FIG. 1B is a plan view of a peripheral pad type semiconductor chip. In general, a center pad type semiconductor chip is more suitable as a semiconductor device that operates at high speed.

Currently, the semiconductor manufacturing industry is investing heavily in the manufacture of semiconductor multi-chip packages that can meet the needs for mounting high speed, multifunctional semiconductor devices at high packing density. As one of such efforts, the semiconductor manufacturing industry has proposed a semiconductor multi-chip package in which peripheral pad-type semiconductor chips are stacked.

One of the multi-chip packages according to the prior art is shown in FIG. Referring to FIG. 2, a semiconductor multichip package includes stacked chips 20 and 40, each chip being a peripheral pad type semiconductor chip. The chips 20 and 40 have a structure in which one chip is stacked on an upper surface of one chip, and a spacer 30 is positioned between the chips 20 and 40. However, the multi-chip package shown in Fig. 2 cannot be manufactured using the center pad type semiconductor chip as the bottom chip, because the center pad type semiconductor chip cannot provide sufficient space for the spacer to be located. to be.

3 is a lower chip originally configured to have a center pad configuration, that is, a pad wiring pattern (not shown) ("center pad wiring pattern") formed in a central region of a semiconductor chip according to the related art. That is, an example of the semiconductor multi-chip package 32 including the center pad type semiconductor chip as the lower chip is shown.

4 and 5 illustrate a method of rearranging the center pad wiring pattern 36 to the peripheral bonding pads 38, where the peripheral bonding pads 38 are actually portions where the wire bonding process is performed. 3 to 5, the multi-chip package 32 according to the prior art as shown includes structures 32 and 34 in which semiconductor chips originally configured to have a center pad configuration are stacked.

In other words, the center pad wiring pattern 36 is connected to the peripheral bonding pads 38 through redistribution patterns 39. Using this method, the spacers 37 can be located in the space between the bonding pads 38 on the lower chip 32, thereby including stacked chips 32 and 34 having the center pad wiring pattern 36. It is possible to form a multi-chip package.

However, in order to rearrange the pad wiring pattern, a considerable cost is required, and the reliability of the process and the package has not yet reached a reliable level. Accordingly, there is a continuing need for a method of manufacturing a semiconductor multichip package including a center pad type semiconductor chip in a reliable and cost-effective manner.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a chip stacked semiconductor multi-chip package not only economically but also highly reliable using a center pad semiconductor chip and a method of manufacturing the same.

According to the present invention, a high density semiconductor multichip package can be manufactured using a center pad type semiconductor chip. This can be achieved using existing manufacturing equipment and can be achieved without using a pad repositioning process which is costly and not very reliable.

According to one embodiment of the invention, a multichip package comprises a package substrate, the package substrate comprising bond fingers disposed thereon. A first chip is disposed on the package substrate, preferably the first chip comprises a first bonding pad formed in a substantially central portion on the chip. Preferably an insulating support structure is formed outside the bonding pads on the first chip. Preferably, a bonding wire electrically connects one of the connection terminals with at least one of the first bonding pads. A portion of the bonding wire is preferably kept away from the first chip using the insulating support structure. A second chip is placed on top of the bonding wire and lies on the insulating support structure.

Specific details of other embodiments are included in the detailed description and the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided by way of example so that the technical spirit of the present invention can be thoroughly and completely disclosed, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thickness of layers and / or the size of regions are exaggerated for clarity. Like numbers refer to like elements throughout.

12 illustrates a semiconductor multichip package according to a preferred embodiment of the present invention. Referring to FIG. 12, the multi chip package 400 includes a package substrate 200, and the package substrate 200 includes connection terminals 220 disposed thereon. Since the first chip 210 has a center pad configuration, the first chip 210 has a first bonding pad 215 formed at a substantially central portion on the chip. The first chip 210 is mounted on the package substrate 200.

An insulating support structure 260 is formed outside the bonding pad 215 on the first chip 210. For example, the insulating support structure 260 may be formed apart from each other along opposite surfaces of the first chip 210, and a bonding pad 215 may be disposed between the insulating support structures 260. The insulating support structure 260 may extend, for example, in the form of a line along at least two peripheral areas of the first chip 210 that face each other (see FIG. 9).

However, the insulating support structure 260 is by no means limited to a line form, and may be manufactured in other forms within the scope of the present invention. For example, the insulating support structure 260 may be a separate mound-like structure disposed along the length direction of two or more edges of the first chip 210. . The insulating support structure 260 may be formed at the corner of the first chip 210, as shown in FIGS. 14A and 14B. The use of a separate mound structure can reduce the amount of material required to form the insulating support structure, thereby reducing manufacturing costs and processing time compared to the line-shaped support structure 260. . In addition, the insulating support structure 260 is not limited to a straight line as shown in FIG. In the practice of the invention, it is also possible to use an insulating support structure different from the straight one, such as in the form of a wavy line shape. In addition, depending on the purpose of manufacturing, one or more insulating support structures 260 in the form of lines may be formed on the peripheral areas of the first chip 210 that face each other.

A bonding wire 230 is connected between one of the connection terminals 220 and at least one of the first bonding pads 215. The bonding wire 230 is spaced apart from the first chip 210 by the insulating support structure 260. It is also desirable that the top of the bonding wire 230 loop is not substantially higher than the top of the insulating support structure 260. A second chip 310 having a second bonding pad 315 is disposed on the bonding wire 230 and positioned on the insulating support structure 260.

13 is a view showing another embodiment in which the technical idea of the present invention is implemented. Referring to FIG. 13, the bonding wire 230 penetrates through the interior of the insulating support structure 260, rather than being located on the insulating support structure 260. In this structure, the insulating support structure 260 may directly support the second chip 310.

According to another embodiment of the present invention, the bonding wire 230 does not need to be in direct contact with the insulating support structure 260. Depending on the manufacturing purpose, for example, the bonding wire 230 may be arranged over or along the support structure 260 in the form of a line or without direct contact with the support structure 260 in the form of a separate mound. It may be formed.

11 is a cross-sectional view showing another aspect of the present invention. Referring to FIG. 11, the multichip package 400 includes an interposer 270 interposed therebetween for bonding the first chip 210 and the second chip 310. The interposer 270 supports the second chip 310 to prevent the bonding wire 230 connected to the first chip 210 and the second chip 310 from contacting each other. The material forming the interposer 270—for example, an epoxy that does not contain a filler, such as silica—is positioned away from the insulating support structure 260 (see FIG. 10), so that the interposer 270 To form. To support the second chip 310 and to insulate the bonding wire 230, without using the interposer 270, instead using the insulating support structure 260 and / or insulating tape 340. By the method, the present invention can be implemented in various other forms.

Referring back to FIG. 12, the multichip package 400 may further include an insulating tape 340, for example, between the second chip 310 and the bonding wire 230 to isolate them from each other. It may be. Insulating tape 340 is preferably formed on the bottom surface of the second chip (310). Although not shown, the insulating tape 340 may directly contact the bonding wire 230. In addition, if the bonding wire 230 penetrates the support structure 260, as described in connection with FIG. 13 or 14B, the insulating tape 340 may, for example, be in contact with the insulating support structure 260. It may also be in direct contact. Instead, the insulating tape 340 may contact the interposer 270 without contacting the bonding wire 230 or the insulating support structure 260.

The multi chip package 400 may also include an epoxy molding compound (EMC) 350 that seals the first chip 210 and the second chip 310. Although not shown, when the interposer 270 is not formed on the first chip 210, the EMC 350 replaces the interposer 270 with the first chip 210 and the second chip 310. It is preferable to arrange between).

<Manufacturing Method>

6 to 12, the method of manufacturing the above-described semiconductor multi-chip package 400 will be described in detail. Referring to FIG. 6, the semiconductor multi chip package 400 is formed by mounting a lower (or first) semiconductor chip 210 on the package substrate 200. This can be accomplished using conventional manufacturing techniques in the art. For example, adhesive 240 is applied to package substrate 200 using a conventional die-bonder having a dispenser unit for dispensing adhesive 240. Adhesives are common adhesive materials commonly used in the field of semiconductor packaging.

The package substrate 200 may be a printed circuit board (PCB) or another package substrate such as, for example, a lead frame or a wiring tape. The substrate 200 is provided with a connection terminal (or a wire connection contact 220) for electrically connecting the package substrate 200 and the first chip 210. The first chip 210 has a first bonding pad (center bonding pad) 215 formed on its substantially central region. The lower semiconductor chip 210 may be attached to the package substrate 200 using the adhesive 240.

Referring to FIG. 7, a liquid type non-conductive epoxy resin or other suitable non-conductive insulating material such as, for example, a hybrid type adhesive, a silicone type adhesive, a film type adhesive, or the like, may be formed using the peripheral surface ( That is, the insulating support structure 260 is formed by applying to the surface of the peripheral region). This process can be carried out using conventional techniques such as, for example, dispensing techniques. An epoxy resin may be provided on the peripheral surface of the lower chip 210 using the same dispenser unit of the die-bonder, as used to apply the adhesive 240 on the package substrate 200. For example, the insulating support structure 260 may be formed in a line shape along the periphery of the lower chip 210 (see FIG. 9) or may be aligned, for example aligned with the center bonding pad 215. It can be formed as a separate mound structure of.

Next, the resultant is heat-treated at a temperature of 100 ° C. or higher to cure the epoxy resin of the insulating support structure 260 as well as the adhesive 240. As a result, an insulating support structure 260 is formed on the peripheral region of the lower chip 210. The width d ₁ of the insulating support structure 260 is preferably smaller than 1/2 of the distance d ₂ between the center of the bonding pad 215 and the nearest edge of the first chip 210. In addition, the height h of the support structure 260 is preferably between about 25-200 μm.

Referring to FIG. 8, a portion of the connection terminal 220 is electrically connected to the first bonding pad 215 through the first bonding wire 230 made of a conductive material such as gold or copper. This wire bonding process can be carried out using conventional techniques such as wedge bonding technique or bump reverse ball bonding technique, which is limited to the above-described wire bonding techniques. It is not. The wire bonding process may be performed directly on the first bonding pad 215 formed at the substantially central portion of the first chip 210. The first bonding wire 230 may be in direct contact with the top surface of the support structure 260, such as the portion indicated by reference symbol A (ie, may be located directly above the support structure 260). The bonding wire 230 may be shaped to penetrate the support structure 260 (see FIG. 13), or may be positioned above the insulating support structure 260 so as not to contact the support structure 260. Use of the insulating support structure 260 can reduce conventional problems such as sagging of the bonding wires.

Referring to FIG. 10, the interposer material 170 is provided on the surface of the lower chip 210. The interposer material 170 may be a liquid and may be the same material that is used to form the insulating support structure 260. Interposer material 170 is added using conventional dispensing techniques.

Referring to FIG. 11, an upper (or second) semiconductor chip 310 is mounted on the first chip 210. The second chip 310 may be a center pad type semiconductor chip or a peripheral pad type semiconductor chip. The loop height and shape of the first bonding wire 230 may be adjusted so that the first bonding wire 230 does not contact the bottom surface of the second chip 310. For this reason, the first bonding wire 230 preferably has a low loop height and a substantially flat portion so as to be suitable for stacking the second chip 310 on the first chip 210. As a result, it is possible to reduce the thickness of the package, and to prevent unwanted defects caused by the contact between the first bonding wire 230 and the second chip 310.

Optionally, the second chip 310 may include a natural tape 340 disposed on its bottom surface. The insulating tape 340 prevents the bottom surface of the second chip 310 from contacting the first bonding wire 230 and the second chip 310 is located closer to the first chip 210. Reduce the thickness of the package.

However, the insulating tape 340 is not a necessary component, and even if the insulating tape 340 is not present, the interposer 270 positioned between the first chip 210 and the second chip 310 may be used. And / or the insulating support structure 260 may sufficiently isolate the first bonding wire 230 and the second chip 310. For example, as described with reference to FIGS. 13 and 14B, when the first bonding wire 230 penetrates the support structure 260, between the first chip 210 and the second chip 310. Insulation tape 340 is not required. In these embodiments, since the first bonding wire 230 is located far enough from the bottom surface of the second chip 310, the first bonding wire 230 and the second chip 310 are separated from each other. Thus, according to various embodiments of the present invention, it is possible to substantially reduce the height of the first bonding wire 230 (the height of the loop of the first bonding wire), resulting in a substantially reduced overall package thickness. You can.

While mounting or adhering the second chip 310 to the first chip 210, the interposer material 170 is pressed down to spread toward the peripheral area of the lower chip 210. During this process, the insulating support structure 260 (see FIG. 9) extending in the longitudinal direction of the first chip 210 may contain an interposer material 170 inside the boundary of the first chip 210. It serves as a dam structure by helping to prevent leakage onto the package substrate 200. Although the insulating support structure 260 may be arranged on two or more sides of the first chip 210, when the upper chip 310 is mounted or glued on the lower chip 210, the interposer is used. Since voids may be generated in the material 170, the insulating support structure 260 may be formed to extend along two opposite surfaces of the first chip 210.

By preventing the interposer material 170 from flowing along the sidewalls of the lower chip 210, the interposer 270 may maintain an appropriate thickness. In addition, by preventing the interposer material 170 from flowing between the lower chip 210 and the housing 350, the adhesion between them can be prevented from being weakened. For example, when the interposer material 170 flows out of the edge of the lower chip 210, the interposer material 170 having weak adhesive properties may cause the first and second chips 210 and 310 to move. It is interposed between the sealing epoxy molding compound and the lower chip 210, and as a result, the epoxy molding compound and the lower chip 210 forming the housing 350 (see FIG. 12) are prevented from being strongly and directly adhered to each other. Therefore, when the interposer material 170 flows down, the reliability of the entire package is degraded. The insulating support structure 260 may also help to maintain a parallel relationship between the first chip 210 and the second chip 310 during the bonding process. This also improves productivity and reduces the overall package thickness.

After the second chip 310 is mounted on the first chip 210, the interposer 270 is hardened by heat treatment at a temperature of about 50 ° C. to about 200 ° C. to cure the interposer material 170. Form. The interposer 270 not only protects the bonding wire 230 in the cured interposer 270 from the outside but also allows the lower chip 210 and the upper chip 310 to adhere to each other. Since the interposer 270 may prevent the first bonding wire 230 from being swept or bent due to the molding compound flowing during the transfer molding process, the interposer 270 may prevent the wire sweeping, which has been caused by the sealing material. This can effectively prevent molding process problems such as wire sweeping or wire sagging. In addition, the interposer 270 isolates the first chip 210 and the second chip 310 from each other.

The remaining portion of the connection terminal 220 is electrically connected to the second bonding pad 315 formed on the upper chip 310 by the second bonding wire 330. This can be done using conventional wire bonding techniques, as described above. The upper chip 310 may also include an insulating support structure formed using the same or similar method as described above.

Referring to FIG. 12, a molding process is performed on the result of the process to form a housing 350. This can be done by a conventional molding process using an epoxy molding compound. However, the housing 350 may be formed of a material different from the epoxy molding compound, such as ceramic, in which case, a process different from the conventional molding process is used. As noted above, the interposer 270 prevents the first wire 230 from being swept or sag by the epoxy molding compound during the transfer molding process. Therefore, according to the present invention, the reliability of the bonding wire and the reliability of the package are improved as compared with the conventional package having the wire sweeping and the deflection phenomenon of the wire. According to one aspect of the present embodiment, a conductive ball array, such as a solder ball array, is formed on the bottom surface of the package substrate 200 to form a ball grid array (BGA) package. It may also be electrically connected to the system.

<Other Example>

Figure 13 shows another embodiment according to the present invention. Referring to FIG. 13, the present embodiment is similar to the embodiment illustrated in FIGS. 6 to 13B except that the insulating support structure 260 is formed after the first bonding wire 230 is formed. Therefore, in the present embodiment, the first bonding wire 230 penetrates through the insulating support structure 260. In the embodiment shown in the figure, since the first bonding wire 230 penetrates the middle portion of the insulating support structure 260, the first bonding wire 230 is fixed and the insulating support structure 260 is provided. Is protected. One advantage of this embodiment is that the height of the first bonding wire 230 is lower than the top height of the insulating support structure 260. Accordingly, the bottom surface of the upper chip 310 is sufficiently insulated from the first bonding wire 230, and wire sweeping or wire sagging may be prevented, and the insulating tape 340 is not required. In addition, the upper chip 310 may be parallel to the lower chip 210.

According to another embodiment of the present invention, a single chip package can obtain various advantages from the technical idea of the present invention. According to the present exemplary embodiment, after the insulating support structure 260 is formed, a molding process and a solder ball array may be performed on the resultant. In this embodiment of the single chip package, the insulating support structure 260 serves to prevent the first bonding wire 230 from being swept or sag during the molding process.

<Wafer-level manufacturing technology>

15 and 16 illustrate a wafer-level fabrication technique in accordance with another embodiment of the present invention. The wafer-level fabrication technique is similar to the fabrication process described above with reference to FIGS. 6-13B, except that the insulating support structure 260 can be formed at the wafer stage.

Referring to FIG. 15, the wafer includes a plurality of chips 210, each having an insulating support structure 260 formed thereon. The insulating support structure 260 may be formed using a wafer-level dispensing technique similar to the dispensing technique described above. The insulating support structure 260 may be formed using a screen printing technique. 16 illustrates a screen mask 402 used to form a line-shaped insulating support structure 260. The screen mask 402 may also be used in a process of forming a plurality of insulating support structures 160 that are separated and spread. Using screen printing technology can more easily control the width and height of the insulating support structure 260. After the insulating support structure 260 is formed, a process of cutting the wafer (dicing process) is performed to individualize the plurality of chips 210. Next, a multi-chip package according to an embodiment of the present invention is formed by performing the above manufacturing process or a similar manufacturing method. The method of forming the insulating support structure 260 at the wafer level can also be used to form a single chip package.

<Multi-chip package containing 3 or more chips>

17 illustrates a multi-chip package according to another embodiment of the present invention in which three or more semiconductor chips are stacked.

Referring to FIG. 17, a multi-chip package 500 according to an embodiment of the present invention includes three or more stacked chips 510, 520, 530, and 540. For simplicity, all the bonding wires 512 are shown in this figure as being connected to one connection terminal 514. However, it will be apparent to those skilled in the art that each bonding wire 512 is connected to a connection terminal 514 corresponding to the need. Each of the stacked chips 510, 520, 530, 540 may have a center pad configuration or a peripheral pad configuration. The stacked chips 510, 520, 530, and 540 need not all have the same pad configuration.

Although the present invention has been illustrated and described with reference to specific embodiments, it will be apparent to those skilled in the art that various modifications may be made without departing from the spirit of the invention.

In conclusion, with or without the interposer 270, using the insulating structure 260 disclosed as part of the present invention, a multi-chip package is fabricated using a lower chip having a center pad configuration. can do. In addition, the method disclosed herein can save cost compared to the manufacturing method according to the prior art, it is possible to perform the packaging process using the existing equipment. It is also possible to solve problems according to the prior art, such as wire sweeping or sagging.

Claims (58)

A package substrate on which connection terminals are disposed; A first chip mounted on an upper portion of the package substrate such that a rear surface thereof is opposite to the package substrate, and including a first bonding pad disposed on a substantially central portion of the front surface; An insulating support structure formed on the first chip so as to be positioned outside the first bonding pad; A bonding wire connecting one of the connection terminals and at least one of the first bonding pads; And A second chip including a second bonding pad, disposed above the bonding wire, and disposed on the insulating support structure; And the insulating support structure comprises a plurality of separate mound shaped structures each disposed along both arraying surfaces of the first chip along an arrangement direction of the first bonding pad. delete delete The multichip package of claim 1, wherein the bonding wire passes through the insulating support structure. The multichip package of claim 4, wherein the bonding wire is in contact with the insulating support structure. delete delete The multichip package of claim 1, wherein the plurality of mound structures that are separated from each other are formed at corners of the first chip. The multichip package of claim 8, wherein the bonding wire passes through the insulating support structure. delete delete The multi-chip package of claim 1, wherein the multi-chip package further comprises an interposer interposed between the first chip and the second chip. 13. The multichip package of claim 12, wherein a substantial portion of the interposer is located on the first chip between the insulating support structures. The multi-chip package of claim 12, wherein the interposer supports the second chip to prevent the second chip from contacting the bonding wire. The multi-chip package of claim 12, wherein the interposer is formed of the same material as the insulating support structure. The multi-chip package according to claim 12, wherein the interposer is made of epoxy that does not contain a filler. The multi-chip package of claim 1, wherein the multi-chip package further comprises an insulating tape disposed between the second chip and the bonding wire. 18. The multichip package of claim 17, wherein the insulating tape is in direct contact with the bonding wire. 18. The multichip package of claim 17, wherein the insulating tape is in direct contact with the insulating support structure. The multichip package of claim 1 wherein the top of the bonding wire loop is not substantially higher than the top of the insulating support structure. The multichip package of claim 1, wherein the multichip package further comprises a housing that seals the first chip and the second chip. 22. The multichip package of claim 21, wherein the housing is formed of an epoxy molding compound. The multi-chip package according to claim 21, wherein the epoxy molding compound is also disposed between the first chip and the second chip. The multichip package of claim 1, wherein the package substrate is a lead frame or a wiring tape. The multi-chip package of claim 1, wherein a width of the insulating support structure is smaller than half of a distance between a center of the bonding pad and an edge of the first chip closest to the bonding pad. The multichip package of claim 1, wherein the insulating support structure has a height of about 25 μm to 200 μm. 2. The multichip package of claim 1, wherein the second chip comprises bonding pads formed in substantially edge regions thereof. 2. The multichip package of claim 1, wherein said second chip comprises bonding pads formed in a substantially central region thereof. The multichip package of claim 1, wherein the multichip package further includes one or more chips stacked on the second chip. 30. The multi-chip package of claim 29, wherein at least one chip of the chips constituting the multi-chip package has different bonding pads from other chips. The multichip package of claim 1, wherein the multichip package further comprises solder balls formed on a bottom surface of the package substrate to form a ball grid array (BGA) package. The multichip package of claim 1, wherein the insulating support structures are spaced apart from each other by the first bonding pads disposed therebetween. The multichip package of claim 1, wherein the bonding wires are arranged in parallel with the insulating support structure. delete delete delete delete delete delete delete Providing a package substrate; Mounting a first chip having a center bonding pad disposed on a substantially central portion of a front surface thereof on the package substrate such that a rear surface of the first chip faces the package substrate; Forming an insulating support structure on each of the outer side of the center bonding pad on the first chip, the insulating support structure including a plurality of separate mound-shaped structures disposed along an arrangement direction of the center bonding pad; Electrically connecting at least one of the package substrate and the center bonding pad using a bonding wire; And Stacking a second chip on the first chip. delete 42. The method of claim 41, prior to the step of stacking the second chip, And forming an interposer between the insulating support structures on the first chip. 42. The method of claim 41 wherein the second chip comprises an insulating tape formed on its bottom surface. Providing a package substrate having a connection terminal disposed thereon; Mounting a first chip having a center bonding pad disposed on a substantially central portion of a front surface thereof on the package substrate such that a rear surface of the first chip faces the package substrate; Forming a bonding wire electrically connecting one of the connection terminals and at least one of the center bonding pads; Forming an insulating support structure on the first chip to be positioned outside the center bonding pad and to penetrate the bonding wire therein; Electrically connecting one of the connection terminals and one or more of the center bonding pads using a bonding wire; And Stacking a second chip above the bonding wire and on the insulating support structure. 46. The method of claim 45, wherein forming the insulating support structure is performed using a dispensing technique. delete delete 46. The method of claim 45, wherein the insulating support structure extends along both sides of the first chip. 50. The method of claim 49, wherein the insulating support structure extends in a line along both opposing surfaces of the first chip. 46. The method of claim 45, wherein the insulating support structure is a plurality of mound-shaped structures that are separated from each other. 46. The method of claim 45, further comprising forming an interposer between the insulating support structures on the first chip prior to stacking the second chip. 53. The method of claim 52, wherein forming the interposer comprises forming an interposer material on the first chip, and stacking the second chip comprises depositing the interposer material on the first chip. A method of making a multi-chip package, comprising spreading out onto a peripheral surface of a phase. 46. The method of claim 45, wherein the second chip comprises an insulating tape formed on its bottom surface. delete delete delete delete

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