KR100666187B1 - Vertical semiconductor device using nanowires and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a vertical semiconductor device using nanowires and a method for manufacturing the same, wherein vertical growth of semiconductor nanowires in a high-density substrate vertical nano-pores spontaneously formed using a porous nanoplate, vertical nanowire semiconductor devices Can be fabricated by integrating densely, and the inside of the cylinder-shaped nanowire placed under the gate electrode of the silicon nanowire becomes a channel, and since the inside of the nanowire has a very small volume, a complete depletion state can be realized. It is possible to obtain a high current driving force, it is possible to reduce the channel length without a separate photo-etching equipment can provide a semiconductor device of several nm class and a manufacturing method thereof.

Porous nanoplates, nanowires, nanopores, cylinder gates, silicon nanowires

Description

Vertical semiconductor devices using nanowires and method of manufacturing the same

1 to 3 are conceptual diagrams for describing various types of semiconductor devices.

4 is a graph illustrating swing characteristics of devices according to structures and gate lengths of various semiconductor devices.

5A to 5C are cross-sectional views illustrating a method of manufacturing an AAO nano template using an aluminum thin film.

6A to 6D are conceptual diagrams for explaining the mechanism by which AAO nano templates are manufactured.

7 is a graph for explaining the relationship between the size of the nano-pores and the voltage of the nano-template.

8 is an SEM photograph of an AAO nano template formed on a silicon substrate.

9A to 9D are cross-sectional views illustrating a method of manufacturing a nano template using PS and PMMA, and FIG. 10 is a photograph and a graph for explaining the nano template manufactured by FIGS. 9A to 9B.

11A to 11H are cross-sectional conceptual views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

12 is a conceptual diagram illustrating the formation of a nano template having fine vertical pores.

Figure 13 is a cross-sectional TEM photograph after the gate insulating film deposition according to the present invention.

14 is a graph showing the characteristics of semiconductor devices according to the spacing of semiconductor nanowires.

15A to 15C are conceptual views of a vertical semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 110: substrate 20: hard mask

25, 150: nano-template 30: PS film

40, 1100: gate electrode 50, 1200: source

60, 1300: drain 45, 180, 1400: gate insulating film

70, 170, 1000: nanowire 120: oxide film

130: aluminum 140: aluminum oxide film

190, 210, 1500, 1700: interlayer insulating film 200, 1600: conductive material film

220: metal wiring 1800: insulating film space

The present invention relates to a vertical semiconductor device using nanowires and a method of manufacturing the same, in particular, a method of manufacturing a vertical nanowire semiconductor device using a high-density substrate vertical nano-pores spontaneously formed using a porous nanotemplate (Nanotemplate) It is about.

In the present semiconductor manufacturing process, the miniaturization and integration of semiconductor devices depend on how reliably the micro patterns are formed. Of course, the current technology is expected to evolve in the future, and it is expected that the line width of the pattern can directly direct devices of about 50 to 70 nm. However, the conventional semiconductor manufacturing process has a limitation in the fabrication of devices of several nanometers or less due to the process characteristics, and also has a limitation in the division of active regions depending on semiconductor patterning and etching techniques. It is known to make incisions difficult. In addition, as a conventional CMOS device, there is a problem in that a channel is formed only on the surface of a substrate so that the driving charge concentration is low.

Accordingly, many people all over the world are already trying to implement devices having a size of several atomic atoms, which are 10 nm or less and even 1 nm or less, and attempts are being made to divide the active region of the semiconductor into several. The world of so-called nanodevices is recognized as one of the core parts of nanotechnology that has recently attracted attention.

For such nanodevices, see Appl. Phys. Lett. 78, P2214, published by Y. Cui, et al., J. Phys. Chem. B104, P5213, published by Y. Cui, et al., Published by Science 291, P851, Y. Cui, et al., 2001, published by Science 302, P1377, Z. Zhong, 2003. It is. These documents are related to the growth of semiconductor nanowires using metal clusters, each of which can determine the diameter of nanowires, and the control of P or N-type doping levels during silicon nanogrowth using diborane. Reference is made to route fabrication and to fabrication of various devices such as diodes, bipolars, transistors and inverters using P or N type silicon nanowires. However, the above documents mainly describe the manufacturing by metal catalysts of free standing semiconductor nanowires, and the device manufactured by them is a crosswired array device arranged horizontally on a silicon substrate. . This conventional technique cannot grow nanowires vertically.

Therefore, in order to solve the above problems, silicon nanowires are vertically grown in high-density substrate vertical nanopores spontaneously formed by using porous nano-templates such as AAO to integrate vertical nanowire semiconductor devices at high density. To manufacture a device having a fully depleted channel structure, a current driving force having the same area energy as compared with the conventional one, and a vertical semiconductor device using a nanowire capable of forming channels of various lengths, and a method of manufacturing the same. To provide that purpose.

A semiconductor nanowire formed perpendicular to the semiconductor substrate according to the present invention, a gate insulating film formed on a surface of the semiconductor nanowire, and a first interlayer insulating film, a gate conductive film, and a second interlayer insulating film sequentially stacked to surround the semiconductor nanowire; It provides a vertical semiconductor device using a nanowire comprising a.

The display device may further include first and second insulating film spaces formed between the first and second interlayer insulating films and the gate conductive film.

In this case, in order to form an impurity region in the semiconductor nanowire, an insulating film doped with a predetermined impurity may be used as the first and second interlayer insulating films, and the semiconductor nanowire may form a porous nano template on the semiconductor substrate. It may be formed by growing a predetermined semiconductor material in the pores of the nano-template. In addition, the semiconductor nanowires may have a linear shape, a carbon nanotube shape, or a nano cable shape, and the gate insulating film may be formed to a thickness of 0.1 to 10 nm.

In addition, forming a nano-template formed with a plurality of vertical nano-pores on the semiconductor substrate, by growing a semiconductor material inside the nano-pores of the nano-template to form a semiconductor nanowire, and then removing the nano-template And forming a gate insulating film on the surface of the semiconductor nanowire, and sequentially forming a first interlayer insulating film, a conductive material film, and a second interlayer insulating film between the semiconductor nanowires to form a gate electrode, a source, and a drain. It provides a method of manufacturing a vertical semiconductor device using a nanowire comprising a.

In this case, the forming of the nano-template in which the plurality of vertical nano pores is formed on the semiconductor substrate may include forming a metal film, and forming a porous metal oxide film by first anodizing a portion of the metal film; Removing the metal oxide film except for the boundary region between the metal oxide film and the metal film through a predetermined etching process and performing a second anodization on the remaining metal film to form the nano-template in which the plurality of vertical nanopores are formed. Steps. Here, after the second anodizing of the remaining metal film to form the nano-template in which a plurality of the vertical nano-pores are formed, the inside of the vertical nano-pores of the nano-template to reduce the diameter of the vertical nano-pores The method may further include applying a predetermined precursor solution to and then performing a predetermined drying process. The precursor solution is preferably prepared by mixing ethanol, TEOS, HCl aqueous solution and the like between 15 to 200 ℃, further put CTAB and HCl solution, and then sufficiently mixed again. Here, the first and second anodization treatment may include depositing the semiconductor substrate in an electrolyte solution including phosphoric acid, oxalic acid, sulfuric acid, and the like, and applying a voltage of 0.1 to 500 V to the semiconductor substrate. . Here, before the forming of the metal film, the method may further include forming an oxide film on the semiconductor substrate.

In this case, the forming of the nano template on which the plurality of vertical nano pores are formed on the semiconductor substrate may include depositing a polymer such as an oxide film and a polytalan / PMMA on the semiconductor substrate, and performing a heat treatment process. Phase separation of the polymer, wet removal of the phase separated PMMA through a predetermined chemical solvent to form a porous polymer layer, and etching the oxide layer using the porous polymer layer as a mask to form the vertical nanopores. Forming the nano template.

Here, the semiconductor material is grown inside the nano-pores of the nano-template to form a semiconductor nanowire, and before removing the nano-template, at least Pt, Fe, Au and Ni on the bottom surface of the pore of the nano-template The method may further include depositing a metal catalyst including any one.

In the above, at a pressure of 1 to 100 mTorr, at least any one of Ar, He and H ₂ and a gas atmosphere at a temperature of 300 to 600 ° C., 5 to 200 sccm of SiH ₄ , GeH ₄ , B ₂ H ₆ and PH It is preferable to form the semiconductor nanowire by flowing at least one of _four gases for 10 to 30 minutes. Further, under a pressure of 1 to 100 mTorr and a temperature of 50 to 1000 ° C., silicon powder and / or germanium powder were pushed to a high temperature region using an alumina boat, and argon (Ar) and hydrogen were mixed to give a speed of 10 to 100 sccm. The semiconductor nanowires may be formed by flowing through. In addition, the semiconductor nanowire may be formed through source vapors and ions evaporated by sputtering a target having an element to be synthesized using an ion gun or a micro laser under a pressure of 1 to 100 mTorr.

It is effective to remove the nano-template described above using a mixed solution of these in which wt% of CrO ₃ and H ₃ PO ₄ are adjusted.

Here, using the silicon thermal oxide film formed by heat treatment for 30 to 90 minutes in a temperature in the range of 500 to 1000 ℃ and oxygen or H ₂ O atmosphere as the gate insulating film, or at least any one of Hf, Zr, La and Al, and these It is preferable to use a high dielectric constant oxide film formed using the silicate.

The first interlayer insulating film, the conductive material film, and the second interlayer insulating film may be sequentially formed between the semiconductor nanowires to form the gate electrode, the source, and the drain. Forming the first interlayer insulating film doped with a predetermined impurity so as to wrap, forming the conductive material film for the gate electrode to cover a portion of the semiconductor nanowire on the first interlayer insulating film, and the conductive material Forming the second interlayer insulating film doped with a predetermined impurity so as to surround an upper portion of the semiconductor nanowire on the film and spreading the impurities doped in the first and second interlayer insulating films to the semiconductor nanowire. Performing a heat treatment process. At this time, between the forming of the first interlayer insulating film and the forming of the conductive material, and between the forming of the conductive material and the forming of the second interlayer insulating film, forming an insulating film space insulating film It may further include. In this case, TEOS (tetraethyl orthosilicate), BSG (borosilicate glass), PSG (phosporosilicate glass) and the like are used as the first and second interlayer insulating films, and the first and second interlayer insulating films are formed to have a thickness of a source and a drain. It is desirable to.

After forming the gate electrode, the source and the drain described above, the step of performing a planarization process for removing the semiconductor nanowire and the gate insulating film exposed on the second interlayer insulating film and performing a metal wiring process It may further include.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

Prior to the description of the specific embodiment of the present invention, the technical spirit of the present invention and the features of the semiconductor device using the nanowire of the present invention will be described.

Hereinafter, various types of complementary metal oxide semiconductor (CMOS) semiconductor devices will be described with reference to the accompanying drawings.

1 to 3 are conceptual diagrams for describing various types of semiconductor devices.

1 is a bird's eye view of a planar CMOS semiconductor device. 1A is a plan view illustrating a planar CMOS semiconductor device in which a linear gate electrode 40 is formed on an active region, and a source 50 and a drain 60 are formed on both sides thereof. This divides the semiconductor substrate into an active region and a field region, forms a gate electrode 40 thereon, and then forms a source 50 and a drain 60 on the semiconductor substrates on both sides of the gate electrode 40. . Next, FIG. 1B is a plan view of a semiconductor device manufactured by dividing the active region into a rectangular bar shape divided into several parts, and c is a perspective view. The gate electrode 40 is formed on the semiconductor substrate 10, and the source 50 and the drain 60 are formed on both sides of the gate electrode 40, but the source 50 and the drain 60 are formed of silicon legs ( Silicon Legs) to form a three-dimensional connection to the gate electrode 40. In this way, if the active region is divided into two and formed on both sides of the gate electrode, a surface in contact with the metal gate electrode 40 and the active region is generated three-dimensionally to generate more charge in the active silicon. As a result, a larger current driving force can be obtained.

2 is a bird's eye view of a semiconductor device fabricated using cylindrical nanowires. 2A is a conceptual diagram of a semiconductor device in which the gate electrode 40 completely surrounds an active region of silicon, and FIG. 2B is a cross-sectional conceptual view of a. In this way, the gate insulating film 45 and the gate electrode 40 are formed in a predetermined region of the silicon silicon wire 70 of the cylinder type, and the source 50 and the drain 60 are formed on both sides thereof. As shown in b of FIG. 2, the metal gate electrode 40 is formed in a topology capable of completely encapsulating active silicon to maximize charge concentrations that can be induced in the silicon. Thus, when formed using the cylinder-type nanowire has the most ideal device structure.

Next, FIG. 3A shows the structure of a semiconductor device employing triangular nanowires, b shows a structure of a semiconductor device employing rectangular nanowires, and c is a double gate having a very thin body. A semiconductor device having a (Double Gate) structure is shown.

Table 1 and Table 2 are device simulation result tables for comparing the operation characteristics of the device according to the structure of the various semiconductor devices.

DG TW <110> RW <110> RW <100> CW <100> W _SL (nm) N / A 4.2 4.0 4.0 3.0 W (nm) N / A 6.7 6.0 6.0 5.0 ρ (nm) N / A 6.7 8.0 8.0 5.0 I _on (㎂ / ㎛) 2000 1630 1460 1650 3550 S (mV / dec) 97 91 96 97 77 DIBL (mV / V) 120 69 104 109 21 Delay (Ps) 0.075 0.056 0.069 0.062 0.046

DG TW <110> RW <110> RW <100> CW <100> W _SL (nm) N / A 8.5 4.0 4.0 6.0 W (nm) N / A 10.9 6.0 6.0 8.0 ρ (nm) N / A 10.9 8.0 8.0 8.0 I _on (㎂ / ㎛) 930 940 1680 1860 2290 S (mV / dec) 144 122 101 102 96 DIBL (mV / V) 396 195 157 163 129 Delay (Ps) 0.167 0.144 0.092 0.082 0.079

Table 1 above shows a device having a double gate electrode structure (DG) having a gate oxide film having a thickness of 1 nm and a gate length of 10 nm, and having a body thickness of 3 nm, a device having a triangle gate electrode structure (TW <110>), Table 1 shows the device characteristics of the devices RW <110> and RW <100> having a rectangular gate electrode structure and the elements CW <100> having a cylinder type gate electrode structure. In addition, Table 2 is a table showing the characteristics of the above-described device when the body thickness is 6nm.

Referring to Tables 1 and 2 above, a semiconductor device having a cylinder type gate electrode structure has a driving current (I _on ) characteristic, a drain-induced barrier lowering (DIBL) characteristic, a swing characteristic (S; swing characteristic), It can be seen that the delay characteristics are excellent.

4 is a graph illustrating swing characteristics of devices according to structures and gate lengths of various semiconductor devices.

Referring to Table 1, Table 2, and FIG. 4, as a result of examining the swing characteristics of the nanostructure having the gate length of 10 nm or less, the semiconductor device having the cylinder type gate electrode structure has the best swing characteristics. In addition, it can be seen that as the gate length decreases, the swing characteristic of the device having the cylinder type gate electrode structure is maximized.

In order to form a semiconductor device having such a gate type gate electrode structure, high-density vertical nanopores are regularly grown on a silicon substrate to grow silicon nanowires in these pores, and the nano-templates are removed by wet removal. Manufacture. Thereafter, the gate electrode may be formed to completely surround the silicon nanowires, thereby forming a semiconductor structure having the same shape as in FIG. 2. An embodiment of a method of manufacturing a semiconductor device having such a shape and structure will be described later with reference to the drawings.

First, prior to the manufacturing process of the semiconductor device, a brief description of the manufacturing method and technical principle of AAO nano-template (Anodized Aluminum Oxide Nanotemplate) is as follows.

5A to 5C are cross-sectional views illustrating a method of manufacturing an AAO nano template using an aluminum thin film.

Referring to FIG. 5A, in order to manufacture an AAO nano template using an aluminum thin film deposited on a silicon substrate, a thin oxide film 120 is formed on the silicon substrate 110 and then an aluminum thin film 130 is deposited. Of course, the aluminum thin film 130 may be directly deposited without forming the thin oxide film 120. Thereafter, a first anodization is performed in a suitable acid solution to form the aluminum oxide film 140. At this time, the aluminum oxide film 140 is spontaneously formed in a vertical shape between the aluminum thin film. That is, as shown in the drawing, there is a region (a portion forming a vertical wall of the drawing) that protrudes perpendicularly to an area having a predetermined curvature such as a wavy pattern at the bottom. This will be described later.

Referring to FIG. 5B, an area in which the aluminum oxide layer 140 formed through the first anodization process protrudes randomly, that is, the disordered part, is removed. At this time, it is preferable to remove the protruding region by the wet etching method. Of course, other dry methods and mixing methods of wet and dry can also be used.

Referring to FIG. 5C, the nanoplate 150 is formed by performing a second anodization process on the aluminum oxide layer 140 and the aluminum thin film 130 remaining at the bottom thereof. The uniformity and regularity may be improved through the two anodization and one etching process, and a clean nano template 150 may be formed.

6A to 6D are conceptual diagrams for explaining the mechanism by which AAO nano templates are manufactured.

Referring to FIGS. 6A to 6D, AAO nano-templates are aluminum ions that are positive ions as shown in the drawing (see FIGS. 6C and 6D) when voltage is applied to the aluminum thin film 130 in an electrolyte solution such as phosphoric acid, sulfuric acid, and oxalic acid. ²⁺ ) is a solution, and oxygen ions (O ^3- ), which are anions, try to move to the interface between the aluminum thin film 130 and the aluminum oxide film 140 where oxidation proceeds. At this time, regular curvature occurs at the interface where the reaction occurs in order to alleviate the compressive stress in the thin film due to the oxide film formation, the radius of curvature depends on the applied voltage. The radius of curvature is a very important factor in the size of the pores of the nano-template and the pore spacing and the shape of the nano-template.

7 is a graph for explaining the relationship between the size of the nano-pores and the voltage of the nano-template.

Referring to FIG. 7, the dependence of the size of the nanopores formed in the nano template and the voltage applied in the electrolyte is shown. That is, as the voltage decreases, the diameter of the pores decreases, thereby forming a large number of pores per unit area.

8 is an SEM photograph of an AAO nano template formed on a silicon substrate.

As shown in FIG. 8, it can be seen that the nano-template formed on the silicon substrate by the above method is formed in a very regular manner with a plurality of vertical nanopores.

Hereinafter, another method of manufacturing a nano template and a technical principle thereof will be described.

9A to 9D are cross-sectional views illustrating a method of manufacturing a nano template using PS and PMMA, and FIG. 10 is a photograph and a graph for explaining the nano template manufactured by FIGS. 9A to 9B.

9A to 9D and 10, an oxide film 20 is formed on a silicon substrate 10, and a PS / PMMA polymer film 30 is formed on the oxide film 20. Form. Thereafter, heat treatment is performed to separate the PMMA phase 30b. The PMMA film 30b in which the phases are separated in this way is wet-removed. PMMA is removed from the entire polymer film 30 to form a porous PS film 30a. Since the oxide film 20 is etched using the PS film 30 as a mask, a porous nano template 25 having a plurality of nano pores is formed. A photograph of FIG. 10 is a planar photograph after removing the phase-separated PMMA, and a photograph b of FIG. 10 is a plan photograph after pattern transfer to the oxide film. Next, after filling silicon (not shown) in the formed nanopores, the oxide layer 20 is removed. Figure 10c is a planar photograph after removing the oxide film after filling the silicon nano pillars. 10D is a graph showing a Gaussian distribution for each case of a to c photographs, and each case shows a single particle size distribution centered around 20 nm.

Hereinafter, the manufacturing method of the semiconductor device using AAO nano template is demonstrated.

11A to 11H are cross-sectional conceptual views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 11A, a nano template 150 having a plurality of nano pores 150a perpendicular to the semiconductor substrate 110 is formed. In this case, the method of manufacturing the AAO nano-template mentioned above and its technical principle are used.

To this end, first, a predetermined oxide film (see 120 in FIG. 5) and a metal film (see 130 in FIG. 5) are formed on the semiconductor substrate 110. A silicon substrate is used as the semiconductor substrate 110. Of course, the present invention is not limited thereto, and various kinds of substrates used in the semiconductor industry may be used. An oxide film having a thickness of less than about 500 kPa is formed on the semiconductor substrate 110 to facilitate template removal. Preferably it is formed in thickness of 80-120 micrometers. In this case, a natural oxide film may be used as the oxide film, and a thermal oxide film formed through a separate oxidation process may be used. Then, a metal film having a thickness of 1000 to 10000 nm is formed on the semiconductor substrate 110 on which the oxide film is formed to form a template having a target height. Preferably, it is formed to a thickness of 5000 to 50000 mm 3. The metal film is formed through a deposition process or a plating process used in the semiconductor industry. In addition, aluminum (Al) is used as a metal film. Before and after each step of forming the oxide film and the metal film, a predetermined cleaning step for removing contaminants on the substrate can be performed. The washing process may use a H ₂ O ₂ / NH ₄ OH aqueous solution.

Thereafter, a first anodization process is performed to form a porous metal oxide film. In the first anodization process, anodization is generated by applying a voltage to a substrate precipitated in an electrolyte solution including phosphoric acid, oxalic acid, sulfuric acid, and the like. The porous metal oxide film is formed by oxidizing about 10 to 50% of the height of the metal film through the first anodization process. The metal oxide film in the region except the metal oxide film surface is removed. That is, only the disordered parts forming the vertical walls of the porous membrane are removed by wet etching, leaving an ordered metal oxide film surface in which only the curvature of the nanopores at the bottom remains. Of course, the removal amount of the metal oxide film is not limited, but this may be variously changed according to the purpose and function of the nano template 150. Then, a second anodization process is performed to form vertically aligned vertical nanopores to form the nano template 150. The second anodization treatment is preferably carried out in the same manner as the first anodization treatment. Thus, a predetermined treatment process is performed in the electrolyte so that the vertical pores of the completed nano template 150 are connected to the substrate to remove the metal oxide film of the portion where the curvature is formed. As described above, the anodization process may be adjusted so that the nanopores may be disposed at a sufficient interval, and the diameter of the pores may be expanded by performing two anodization processes. In this case, when aluminum is used as the metal, the porous nano-template 150 becomes AAO.

In addition, polymer materials such as polytallan / PMMA can be used. The fabrication of such polytallan / PMMA template involves the deposition of a thick (about 500 to 5000 micron) oxide film on a silicon substrate followed by the deposition and heat treatment of two polymers thereon, resulting in phase separation on the polymer resulting in PMMA in the PS matrix. Agglomerate in cylinder shape. Subsequent injection of chemicals to dissolve PMMA leaves only the PS, which makes nanopores, remain on the oxide layer, and if it is continuously etched, the shape of the PS is pattern transferred to the silicon oxide layer. Then, by dissolving PS, a nano-template in which substrate vertical nano-pores are regularly formed in a silicon oxide film can be produced.

In the present exemplary embodiment, the nano template 150 having the diameter of 2 to 300 nm and the vertical pores of 3 to 10000 nm in height may be formed by adjusting the conditions of the anodization process. That is, as described above with reference to Figure 9 by adjusting the voltage to form a nano-template 150 having vertical pores of the target diameter and height. When the voltage is lowered under the anodization process conditions, the size of pores formed can be reduced. In this embodiment, a voltage of 0.1 to 500V is applied to the substrate to form a nano template 150 having pores of a target diameter. In order to uniformly form ultra-fine nanopores of less than 10 nm, it is necessary to finely control the concentration of the electrolyte and the reaction temperature, as well as to control the minute voltage of less than 1V.

In addition, the nano template 150 may form pores of a large size to control the diameter thereof, and then deposit a predetermined material therein to form pores of a small size.

12 is a conceptual diagram illustrating the formation of a nano template having fine vertical pores.

Referring to FIG. 12, as described above, the nano template 150 having the pores of the first size is formed. Thereafter, the silica-surfactant molecular sieve material (Silica-Suractant Molecular Sieve Precursor Solution) is filled to form pores of a second size. Through this, ultra-fine nano pores having a size of about 2 nm may be vertically formed along the wall of the template 150. In addition, a predetermined precursor solution may be applied in the pores of the template 150 and then dried in an air at room temperature to form fine vertical nanopores of about 3 nm. The precursor solution is Ethanol, TEOS (tetraethyl orthosilicate), HCl aqueous solution, etc. are mixed at room temperature between 200 ℃, additionally added CTAB and HCl solution, and then sufficiently mixed again to prepare.

In the present embodiment, after fabrication of the nanostructure, some aluminum metal is left at the bottom of the template 150 without polarizing all of the deposited aluminum to facilitate wiring, or other types of wiring metals before deposition of the substrate and aluminum. A membrane (not shown) may be inserted. As the metal to be inserted, a metal which is at least one of Cu, Nb, and Al may be used. When the predetermined metal is inserted as described above, after the formation of the nano-template 150 is completed, the lower end of the aligned aluminum oxide film having a large curvature so as to connect the lower substrate (or the deposited metal film) and the nanopores is electrolyte. It is preferable to remove from inside (mainly chromic acid).

Referring to FIG. 11B, the semiconductor material is vertically grown in the nano-pores of the nano-template 150 including the plurality of vertical nano-pores to form the semiconductor nanowires 170.

As a method of growing a semiconductor material, a method of growing using a predetermined metal catalyst (not shown) and a method of not using a metal catalyst may be applied.

In the case of using a predetermined metal catalyst, metal nano clusters (not shown) are deposited on the bottom surface of the pores of the nano template using electrodeposition (electroplating) in an electrolyte. It is preferable to use a metal containing Pt, Fe, Au and Ni as the metal catalyst (metal nanocluster). In the method using metal as a catalyst, these metals may be electroplated in an electrolyte so that a metal film is deposited on the bottom of the nanopores. As such, after forming a metal nanocluster on the bottom surface of the nanoplate, a semiconductor nanowire is formed thereon using the nucleus as a nucleus. The diameter of the nanowires thus grown is not determined by the pore diameter in the template 150, but by the particle size of the electrolytically deposited metal clusters. This allows gaps to exist in the grown nanowires and nanospaces.

On the other hand, when a metal catalyst is not used, a portion of the curvature in the pores of the template 150 is evaporated by the vaporization of SIO powder under a suitable atmosphere in a high temperature heat treatment furnace by a method called OAG (Oxide-Assisted Growth). It uses the principle of selective adsorption and growth at. It is preferable to use the metal catalyst in an environment in which the semiconductor nanowire 170 chemically plays an impurity role. This method can be performed very simply, but the crystallinity of the semiconductor nanowires 170 to be formed is lower than when using the metal nano-cluster, and the diameter of the semiconductor nanowires 170 to be formed is also large in the shape of the nano-pores Since it depends, the uniformity and shape of the pores formed in the nano-template 150 should be manufactured very well.

At this time, the synthesis of the semiconductor nanowire 170 uses a source gas such as SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl _{4 in} the case of silicon (Si), and source gas such as GeH _{4 in} the case of germanium (Ge). Can be used. In addition, the powder containing Ge, Si, or the like may be thermally decomposed and grown in a high temperature heat treatment process (using a furnace). In addition, physical vapor deposition can be synthesized by physically generating vapors of these elements by ion sputtering in a chamber in which a target containing these elements is installed. It is effective to use equipment that generates plasma to lower the temperature at which these methods are implemented.

In more detail, first, the conditions for growing the semiconductor nanowires 170 using a source gas may include a pressure of 100 mTorr or less, a gas atmosphere of at least one of Ar, He, and H ₂ , and 300 to 600 ° C. Under temperature, the source gas is flowed in about 5 to 200 sccm in about 20 minutes. That is, while maintaining the degree of vacuum in the reactor at 10 to 90 mTorr, the temperature inside the reactor is raised to about 300 to 600 ° C. under at least one gas atmosphere of Ar, He, and H ₂ . Thereafter, when SiH ₄ is poured into the chamber within about 10 to 30 minutes at about 5 to 200 sccm, silicon single crystal nanowires are grown. At this time, when GeH ₄ is added as a reaction gas, Ge nanowires are grown. In addition, when SiH ₄ and GeH ₄ are mixed into the reaction gas, SiGe nanowires may be grown. When SiH ₄ and GeH ₄ are mixed, the temperature of the chamber can be kept slightly lower (50 to 90%) compared to SiH ₄ . In addition, when B ₂ H ₆ or PH ₄ is added during growth, the growing semiconductor nanowires 170 may be doped with p type or n type by boron (B) or phosphorus (P), respectively. In this embodiment, the silicon single crystal nanowires are grown at the position of the metal cluster by chemical vapor deposition using a reaction gas such as SiH ₄ . Of course, as mentioned above, when GeH ₄ , B ₂ H ₆ , and PH ₄ are added, semiconductor single crystal nanowires containing Ge, B, and P may be grown.

In addition, the conditions for growing the semiconductor nanowires 170 by using the source powder is a state in which the vacuum degree inside the reactor is maintained at 100 mTorr or less, by using the alumina boat in the reactor by burning the silicon oxide film powder in the boat to the high temperature site and Argon (Ar) and hydrogen are mixed and flowed at a rate of 10 to 100 sccm. At this time, the temperature of the reactor to be heated is in the range of 50 to 1000 ℃, heat treatment for 20 to 40 minutes to grow the silicon nanowires. In this case, when germanium powder (Ge powder) is added to the alumina boat, germanium nanowires are grown, and when mixed with silicon oxide film, silicon germanium (SiGe) nanowires are grown.

In addition, in the case of using the target, the target having the element to be synthesized is sputtered by using an ion gun or an ion laser while maintaining the vacuum degree within the reactor at 100 mTorr or less. This allows evaporated source vapors and ions to grow on the substrate in the form of nanowires.

The semiconductor nanowires 170 grown in the nano pores through the above methods are coated in a wire form, a carbon nanotube form, or outside the nanowires with a different material from the nanowire material ( A natural oxide film formed outside the semiconductor nanowire. The semiconductor nanowire 170 may include at least one of Si, Ge, C, O, Ga, As, P, B, Zn, Se, S, Cd, Sn, Al, and In. . Of course, compounds made of these are also possible as described above, and once again referring to such compounds, SiO ₂ , SiGe, GaAs, AlGaAs, GaAsP, InAs, Sn, InAsP, InGaAs, AlAs, InP, GaP, ZnO, ZnSe Substances such as CdS, ZnCdS, and CdSe may be included in the component.

Referring to FIG. 11C, the nano template 150 is removed through a predetermined etching process. As a result, an array in which the semiconductor nanowires 170 vertically grown on the semiconductor substrate 110 are uniformly and densely arranged remains.

As shown in FIG. 11B, the nano template 150 remaining after the semiconductor nanowire 170 is synthesized is removed by wet etching. In this case, it is preferable to use these mixed solutions in which the wt% of CrO ₃ and H ₃ PO ₄ are adjusted, and each is used within 10 wt%. Of course, the present invention is not limited thereto, and various etching methods and etching agents may be used.

Figure 13 is a cross-sectional TEM photograph after the gate insulating film deposition according to the present invention.

11D and 13, a gate insulating layer 180 is formed on the surface of the semiconductor nanowire 170. FIG. 13 is a TEM photograph of a specimen in which a high dielectric constant oxide film having a thickness of about 2 nm is deposited on the silicon nanowire 170 having a diameter of about 5 nm through the ALD method.

Before the gate insulating layer 180 is formed, a natural oxide film formed on the surface of the semiconductor nanowire 170 is removed through a predetermined cleaning process. The cleaning process uses mixed HF. Thereafter, a high temperature oxidation process is performed to form a gate insulating layer 180 on the surface of the semiconductor nanowire 170. In this case, various insulating material films may be used for the gate insulating film 180, but in the present embodiment, a silicon oxide film formed by heat treatment with a high temperature oxidation atmosphere is used, or a high dielectric constant oxide film deposited through an ALD or CVD method is used as the gate insulating film. do.

The silicon thermal oxide film is formed by using a furnace, and is obtained by heat treatment for 30 to 90 minutes in an oxygen or H ₂ O atmosphere and a temperature in the range of 500 to 1000 ° C. Oxide films, such as Hf, Zr, La, and Al, or these silicates, are applicable to the said high dielectric constant oxide film, The oxide film and the silicate produced by mixing them are also applicable. That is, if the high dielectric constant oxide film is to be used as the gate insulating film 180, a high dielectric constant oxide film having a thickness adjusted to an atomic layer may be deposited in a deposition apparatus such as atomic layer deposition (ALD) after the cleaning process. That is, a high dielectric constant oxide film formed by ALD or CVD is exposed to an oxygen atmosphere in a reactor heated at 600 to 800 ° C. such as an organic precursor such as HfCl ₄ including Hf, Zr, La, and Al. Deposit on the surface of the nanowires. In this case, when the silicon precursor (Si-precursor) is put together, the deposited high dielectric constant film may be replaced with silicates such as HfOx to HfSiOx. Silicates generally have a lower dielectric constant than oxide films, but may be preferred because of their superior thermal stability. In addition, the main reason for using ALD is that a deposition technique having excellent step coverage for complex shapes should be used when the object to be deposited has a high aspect ratio as in the present embodiment.

11E through 11G, a first interlayer insulating layer 190, a conductive material layer 200, and a second interlayer insulating layer 210 are sequentially formed between the semiconductor nanowires 170 to form a gate electrode, a source, and a drain. To form.

After the gate insulating layer 180 is formed, a first interlayer insulating layer 190 is formed in a lower region between the semiconductor nanowires 170 through a predetermined deposition process, and TEOS (tetraethyl orthosilicate) is formed as the first interlayer insulating layer 190, BSG (borosilicate glass), PSG (phosporosilicate glass) and the like. In particular, since BSG and PSG each contain B and P, diffusion doping may be performed on the semiconductor nanowires 170 by using them. Diffusion doping refers to buried semiconductor nanowires 170 surrounded by BSG or PSG doped by B (or P) atoms diffused out of BSG (or PSG) during subsequent heat treatment at high temperature. In this case, the doping level of the silicon nanowires 170 may be determined by the diameter of the semiconductor nanowires 170, the subsequent heat treatment temperature, and the doping element content in the BSG (or PSG) used. Therefore, spontaneously doped nanowire devices can be obtained by using BSG as an insulating film in pMOS device fabrication and PSG in nMOS fabrication.

After the first interlayer insulating layer 190 is formed, the conductive material layer 200 is formed, and the conductive material layer 200 refers to a gate electrode material, and a material to be the gate electrode of the semiconductor device is used. That is, any one of Al, W, Pt, Au, Mo, Cu, C, Ti, TiN, WN and AlN is used as the conductive material film 200. In addition, silicides of these metals such as NiSix, CoSix, TiSix, MoSix, and WSix can be used, and polycrystalline silicon can be used because it can have similar conductivity as metal if it contains a high concentration of doping element. . The deposition of the conductive material may use a deposition method such as CVD or PVD, and may fill a gap by using a low viscosity of the metal after heat treatment such as aluminum reflow. Filling a chemical solution (such as metal alkoxide) and then depositing in a form that induces precipitation of metals is possible. At this time, since the thickness of the conductive material film 200 filled between the semiconductor nanowires 170 determines the length, it should be precisely controlled.

After the conductive material film 200 is formed, the second interlayer insulating film 210 is formed, and the second interlayer insulating film 210 uses the same material film as the first interlayer insulating film 190. A space between the semiconductor nanowires 170 may be completely filled through the first interlayer insulating layer 190, the conductive material layer 200, and the second interlayer insulating layer 210, or may be filled to a predetermined height. In addition, the first and second interlayer insulating layers 190 and 210 may be formed to have a thickness sufficient to cover the semiconductor nanowire 170 in the region where the source / drain is to be formed. That is, the first interlayer insulating film 190 is filled by the thickness of the source, the conductive material film 200 is filled by the thickness of the gate electrode, and the second interlayer insulating film 210 is removed by the thickness of the drain. Peel. Subsequently, a predetermined heat treatment may be performed to diffuse impurities doped into the first and second interlayer insulating layers 190 and 210 into the semiconductor nanowire 170 to form a separate impurity layer (source / drain). .

In addition, if BSG (or PSG) is used as the first and second interlayer insulating films 190 and 210, the amount of overlap capacitance between the gate electrode and the source / drain regions formed therebetween is increased. In this case, a predetermined insulating film space insulating film may be further formed between the interlayer insulating film and the gate conductive film. Looking at the structure formed by this, it can have a form of the first BSG (or PSG) / first insulating film space / gate conductive film / second insulating film space / second BSG (or PSG) in the vertical direction.

In this embodiment, the first and second interlayer insulating films 190 and 210 are formed to a thickness of about 1 to 200 nm, and the conductive material film 200 for the gate electrode is formed to a thickness of about 1 to 50 nm. In addition, when forming the insulating film space, it is formed to a thickness of about 1 to 30nm using a material such as SiO ₂ , Si ₃ N ₄ , SiON and the like as the insulating film space.

Referring to FIG. 11H, as described above, the first and second interlayer insulating layers 190 and 210 and the conductive material layer 200 are deposited to form a gate electrode and a source / drain, and then a predetermined planarization process is performed. The semiconductor nanowire 170 and the gate insulating layer 180 exposed on the second interlayer insulating layer 210 are removed. As the planarization process, a CMP or an etching-back process may be used.

The metal wiring 220 is formed on the planarized semiconductor substrate 110. That is, after the filling is completed, wiring is connected to the drain portion of the upper portion to form a drain pad. In addition, it is effective to allow the gate electrode to be wired with a pad so that a voltage can be applied. That is, it is preferable that the bit line is directly connected to the upper train terminal through metal wires, and the word line is preferably connected to the metal wires by using a pad using a predetermined pad to connect the gate electrode material embedded between the insulating layers of the nano wires. . In addition, a gate line patterning process may be performed to isolate the nanowires to be tied to the word line into separate blocks before the word line connection. The gate line patterning process may be performed by using a photolithography process using a separate pad layer. After the patterning process, a process of forming a pad for connecting nanowires in the same block to a common word line may be performed. After that, it is preferable to form the metal word line wiring through the aforementioned wiring process.

As mentioned in the present embodiment, p- or n-type silicon nanodevices may be manufactured by growing an undoped silicon nanowire and then diffusing doping using a subsequent interlayer insulating film. In addition, there may be another method of injecting the doping gas together when growing the silicon nanowire, but in this case, only one type of device is formed on the substrate, so that two p and n through patterning are needed to form CMOS. Formation of silicon nanowires is required, which makes the process very complex and undesirable in terms of productivity. The channel formed by the method described in this embodiment is inside a cylindrical nanowire placed under the gate electrode of the silicon nanowire, and since the nanowire is grown at a very high density in a small area, only the surface of the wafer is channeled. Compared to the planar device used, a very high current driving force can be obtained in the same area.

In addition, since the length of the channel is determined by the thickness of the gate metal to be buried, the channel length is not dependent on expensive photolithography equipment that determines the current semiconductor technology in the future sub-10 nm semiconductor device manufacturing technology. It is possible to reduce the size. In addition, the channel becomes inside a cylindrical nanowire placed under the gate electrode of the silicon nanowire, and the inside of the nanowire has a very small volume, thereby achieving a fully depletion state.

In addition, the higher density integration can improve the effect of the device.

14 is a graph showing the characteristics of semiconductor devices according to the spacing of semiconductor nanowires.

Referring to FIG. 14, it can be seen that both the operating current-leakage current ratio (Ion / Ioff) and the swing characteristics are greatly improved as the integration density of the semiconductor nanowire (nanostructure) increases. In other words, a large effect can be obtained when the semiconductor devices are integrated at a high density.

Looking at the device of the present invention formed by the method described above is as follows.

15A to 15C are conceptual views of a vertical semiconductor device according to the present invention.

Referring to FIG. 15A, a vertical semiconductor device of the present invention includes a semiconductor nanowire 1000 formed perpendicular to a substrate and a gate electrode formed to surround a predetermined region (channel region of the device) of the semiconductor nanowire 1000. 1100 and a source 1200 and a drain 1300 formed on the semiconductor nanowires 1000 on both sides of the gate electrode 1100. In addition, referring to FIG. 15B, the plurality of semiconductor nanowires 1000 formed perpendicular to the semiconductor substrate, the gate insulating film 1400 formed on the surfaces of the plurality of semiconductor nanowires 1000, and the semiconductor nanowires 1000 may be used. The first interlayer insulating film 1500, the gate conductive film 1600, and the second interlayer insulating film 1700 are sequentially stacked to surround the semiconductor nanowire 1000 therebetween. In this case, as shown in FIG. 15C, the first and second insulating interlayers 1500 and 1700 and the first and second insulating layer spaces 1800 and 1900 formed between the gate conductive layer 1600 may be further included.

In the first and second interlayer insulating films 1800 and 1900, impurity regions (sources / drains) are formed in the semiconductor nanowire 1000 using an insulating film doped with a predetermined impurity. In addition, the semiconductor nanowire 1000 is formed by using a porous nano template such as AAO.

As such, the present embodiment vertically grows semiconductor nanowires in a vertical nanopore of a high-density substrate spontaneously formed by using a porous nano-template such as AAO, and manufactures a high-density integrated vertical nanowire semiconductor device. Each vertical nanowire acts as a separate CMOS device.

The operation of the device is the same as that of a conventional semiconductor device (CMOS device), and it is possible to adjust the turn on / off of the device by applying a voltage to the drain and the gate connected to the pad separately. Because the thickness is defined to be extremely thin, the device's operating characteristics can be significantly improved over existing devices (see Tables 1 and 2). In addition, since the channel length for determining the shrink ratio of the semiconductor is determined by the thickness of the gate metal to be embedded, it is possible to reduce the size of the device by lowering the deposition thickness of the embedded metal. In addition, since it can be directly applied to carbon nanotubes, if a single-welded carbon nanotube (single-walled CNT) having the same conductivity can be grown on an AAO template, another one-dimensional nanowire device can be manufactured. These high density CNT arrays have very high applicability as field emitters in the display field.

As described above, the present invention can be manufactured by vertically growing semiconductor nanowires in a high-density substrate vertical nano-pores spontaneously formed using porous nano-templates, and integrating vertical nanowire semiconductor devices with high density.

In addition, the channel of the semiconductor device formed through the vertical nanowires becomes a cylinder-shaped nanowire placed under the gate electrode of the silicon nanowire, and since the nanowires grow at a very high density in a small area, only the surface of the wafer is channeled. Compared to the planar element used in the present invention, very high current driving force can be obtained in the same area.

In addition, the inside of the cylinder-shaped nanowires placed under the gate electrode of the silicon nanowires becomes a channel, and the inside of the nanowires has a very small volume, so that a complete depletion state can be realized.

In addition, since the channel length that determines the shrink ratio of the semiconductor is determined by the thickness of the gate metal to be buried, the expensive photolithography that influences the current semiconductor technology in the expected sub-10 nm semiconductor device manufacturing technology ( It is possible to reduce the channel length without depending on lithography equipment, and to reduce the thickness of the metal deposition to be buried, it is possible to refine the device.

In addition, it is applicable to the carbon nanotubes in the display field.

Claims (22)

Semiconductor nanowires formed perpendicular to the semiconductor substrate; A gate insulating film formed on a surface of the semiconductor nanowire; A gate conductive layer surrounding a central region of the semiconductor nanowire; And first and second interlayer insulating layers provided on both sides of the gate conductive layer to surround the semiconductor nanowires. A vertical semiconductor device using nanowires including impurity regions formed in the semiconductor nanowires under the first and second interlayer insulating films. The method of claim 1, A vertical semiconductor device using nanowires further comprising first and second insulating film spaces formed between the first and second interlayer insulating films and a gate conductive film. The method of claim 1, The vertical semiconductor device using a nanowire using an insulating film doped with a predetermined impurity with the first and second interlayer insulating film to form the impurity region in the semiconductor nanowire. The method of claim 1, The semiconductor nanowire is a vertical semiconductor device using nanowires formed by forming a porous nano-template on the semiconductor substrate, by growing a predetermined semiconductor material in the pores of the nano-template. The method of claim 1, The semiconductor nanowire has a shape of a linear, carbon nanotube or nano-cable form, the gate insulating film is a vertical semiconductor device using a nanowire to form a thickness of 0.1 to 10nm. Forming a nano template having a plurality of vertical nano pores formed on the semiconductor substrate; Forming a semiconductor nanowire by growing a semiconductor material inside the nano pores of the nano template, and then removing the nano template; Forming a gate insulating film on a surface of the semiconductor nanowire; And The impurity doped first interlayer insulating film, the conductive material film, and the impurity doped second interlayer insulating film are sequentially formed between the semiconductor nanowires to form a gate electrode outside the semiconductor nanowires, and a source and Forming a drain; Method of manufacturing a vertical semiconductor device using a nanowire comprising a. The method of claim 6, wherein the forming of the nano template on which the plurality of vertical nano pores is formed is performed on the semiconductor substrate. Forming a metal film; First anodizing a portion of the metal film to form a porous metal oxide film; Removing the metal oxide film except for the boundary region between the metal oxide film and the metal film through a predetermined etching process; And Forming the nano-template on which the plurality of vertical nanopores are formed by subjecting the remaining metal film to a second anodization process. 8. The method of claim 7, wherein after the second anodization of the remaining metal film to form the nano-template formed with a plurality of the vertical nano-pores, In order to reduce the diameter of the vertical nano-pores vertical semiconductor device using a nano-wire further comprising applying a predetermined precursor solution to the inside of the vertical nano-pores of the nano template, and then performing a predetermined drying process Method of preparation. The method of claim 8, The precursor solution is a method of manufacturing a vertical semiconductor device using a nanowire prepared by mixing ethanol, TEOS, HCl aqueous solution and the like between 15 to 200 ℃, further put CTAB and HCl solution, and then fully mixed again. The method of claim 7, wherein the first and second anodization treatment, Precipitating the semiconductor substrate in an electrolyte solution containing phosphoric acid, oxalic acid, sulfuric acid, and the like; And Method of manufacturing a vertical semiconductor device using a nanowire comprising the step of applying a voltage of 0.1 to 500V to the semiconductor substrate. The method of claim 7, wherein before forming the metal film, The method of manufacturing a vertical semiconductor device using a nanowire further comprising the step of forming an oxide film on the semiconductor substrate. The method of claim 6, wherein the forming of the nano template on which the plurality of vertical nano pores is formed is performed on the semiconductor substrate. Depositing an oxide film and a polymer such as polytallan / PMMA on the semiconductor substrate; Performing a heat treatment process to phase separate the polymer; Wet removing the phase separated PMMA through a predetermined chemical solvent to form a porous polymer layer; And And etching the oxide film using the porous polymer layer as a mask to form the nano-template in which the vertical nano-pores are formed. The method of claim 6, wherein the semiconductor material is grown inside the nano pores of the nano template to form a semiconductor nanowire, and then before removing the nano template, Method of manufacturing a vertical semiconductor device using a nanowire further comprises the step of depositing a metal catalyst containing at least one of Pt, Fe, Au and Ni on the bottom surface of the nano-template. The method of claim 6, At a pressure of 1 to 100 mTorr, at least one of Ar, He and H ₂ , and a gas atmosphere and a temperature of 300 to 600 ° C., at least 5 to 200 sccm of SiH ₄ , GeH ₄ , B ₂ H ₆ and PH ₄ 10. A method of manufacturing a vertical semiconductor device using nanowires which flow one of the gases for 10 to 30 minutes to form the semiconductor nanowires. The method of claim 6, At a pressure of 1 to 100 mTorr and a temperature of 50 to 1000 ° C., silicon powder and / or germanium powder were pushed to a high temperature region using an alumina boat, mixed with argon (Ar) and hydrogen, and flowed at a rate of 10 to 100 sccm. A method of manufacturing a vertical semiconductor device using nanowires to form the semiconductor nanowires. The method of claim 6, A method of manufacturing a vertical semiconductor device using nanowires to form the semiconductor nanowires through source vapors and ions evaporated by sputtering a target having an element to be synthesized using an ion gun or a fine laser under a pressure of 1 to 100 mTorr . The method of claim 6, The nano-template is a method for manufacturing a vertical semiconductor device using a nanowire to remove using a mixed solution in which the wt% of CrO ₃ and H ₃ PO ₄ are adjusted. The method of claim 6, Using a silicon thermal oxide film formed by heat treatment for 30 to 90 minutes in a temperature in the range of 500 to 1000 ℃ and oxygen or H ₂ O atmosphere as the gate insulating film, or at least one oxide film of Hf, Zr, La and Al and silicates thereof A method of manufacturing a vertical semiconductor device using nanowires using a high dielectric constant oxide film formed by using a. The semiconductor device of claim 6, wherein an impurity doped first interlayer insulating film, a conductive material film, and an impurity doped second interlayer insulating film are sequentially formed between the semiconductor nanowires to form a gate electrode outside the semiconductor nanowires. Forming a source and a drain inside the nanowires, Forming a first interlayer insulating layer doped with the impurity to surround a lower portion of the semiconductor nanowire; Forming the conductive material film for the gate electrode to surround a portion of the semiconductor nanowire on the first interlayer insulating film; Forming a second interlayer insulating layer doped with the impurities on the conductive material layer to surround an upper portion of the semiconductor nanowire; And And performing a predetermined heat treatment process to diffuse the impurities doped into the first and second interlayer insulating films into the semiconductor nanowires. 20. The method of claim 19, wherein between forming the first interlayer insulating film and forming the conductive material, forming the conductive material, and forming the second interlayer insulating film, A method for manufacturing a vertical semiconductor device using nanowires, further comprising forming an insulating film space insulating film. The method of claim 19, TEOS (tetraethyl orthosilicate), BSG (borosilicate glass), PSG (phosporosilicate glass), etc. may be used as the first and second interlayer insulating films, wherein each of the first and second interlayer insulating films is formed to have a thickness of a source and a drain. A method of manufacturing a vertical semiconductor device using a route. The method of claim 6, wherein after forming the gate electrode, the source and the drain, Performing a planarization process to remove the semiconductor nanowires and the gate insulating layer exposed on the second interlayer insulating layer; And Method of manufacturing a vertical semiconductor device using a nanowire further comprising the step of performing a metal wiring process.

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