KR100660831B1 - Manufacturing Method of Mixed Semiconductor Device with Logic and DRAM - Google Patents

Abstract

A method of manufacturing a mixed semiconductor device of logic and DRAM capable of simultaneously increasing the capacity of a DRAM device and the high speed of the logic device and reducing the steps of the manufacturing process is disclosed. To this end, the present invention uses a mask without performing ion implantation for adjusting the threshold voltage of the I / O region, the logic element region, the memory region, and ion implantation for forming the source / drain twice. At the same time, the gate insulating film thickness of the I / O region and the memory region are equally applied.

Description

Method for fabricating a mixed semiconductor device of logic and DRAM {Method for fabricating a Merged DRAM Logic Device}

1 is a cross-sectional view illustrating a method of manufacturing a mixed semiconductor device of logic and DRAM according to the prior art.

2 is a cross-sectional view illustrating a method of manufacturing a mixed semiconductor device of logic and DRAM according to the present invention.

Explanation of symbols on the main parts of the drawings

200: semiconductor substrate, 202: device isolation film,

204: first gate insulating film, 206: ion implantation for well formation,

208: ion implantation for adjusting threshold voltage, 210: second gate insulating film,

212: photoresist pattern, 214: third gate insulating film,

216: gate pattern, 218: ion implantation for source / drain formation.

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a mixed DRAM logic device of logic and DRAM.                         

Recently, a mixed semiconductor device (MDL device) of logic and DRAM, which designs a dynamic randon access memory (DRAM) and a logic device (Logic device) on a single semiconductor chip, has been introduced to improve the processing capability of the semiconductor device. In a mixed semiconductor device (MDL device) of such a logic and a DRAM, it is an ideal development direction to design a single semiconductor chip utilizing the high integration of the DRAM and the high speed of the logic device.

To achieve this goal, the thickness of the gate insulating layer must be designed differently in the logic element region and the memory region. A different thickness of the gate insulating film is advantageous because the voltages applied to the gate insulating film of the memory region and the logic element region are different even at the same external voltage in the mixed semiconductor device of the logic and the DRAM.

In general, in the memory region where the DRAM is formed, in order to increase the accumulated charge amount of the memory cell, that is, to increase the voltage applied to the capacitor, 3.5 to 3 which is a voltage higher than or equal to the threshold voltage Vth on the word line. The write operation is performed by walking the 7V. In practice, a voltage of 4V or more is often applied. At this time, the thickness of the gate insulating film needs to be about 100 GPa or more.

On the other hand, a design rule of 0.35 占 퐉 and a logic device composed of an internal area and an I / O area apply a 3.3V supply voltage without boosting the voltage to the I / O area. A voltage of 5V and 5V is applied, and a 3.3V power supply voltage is applied to the logic region. In general logic devices, the thickness of the gate insulating film should be as thin as possible for high speed and excellent driving capability. In fact, the gate insulating film thickness of a general logic device is about 70% of the thickness of the gate insulating film of the DRAM.

Therefore, in a mixed semiconductor device of logic and DRAM in which a memory device such as a logic device and a DRAM are formed on one semiconductor chip, the design and the high capacity of the DRAM device are not sacrificed without sacrificing the high speed of the logic device. The situation requires a manufacturing method.

1 is a cross-sectional view illustrating a method of manufacturing a mixed semiconductor device of logic and DRAM according to the prior art.

1A and 1B, a device isolation process is performed on a semiconductor substrate 100 to form a device isolation layer 102, and an I / O region, a logic element region, and a memory region of a mixed semiconductor element of logic and DRAM. Define each one. Subsequently, after the first gate insulating layer 104 is formed, ion implantation for forming a well (not shown) is performed on the semiconductor substrate.

1C and 1D, a photoresist pattern 106 is formed on the well-formed ion implanted semiconductor substrate. The photoresist pattern 106 is a pattern covering the memory area and exposing the I / O area and the logic device area of the logic device. Thereafter, ion implantation for adjusting the threshold voltage Vth of the I / O region and the logic element region is first performed. At this time, the ion implantation conditions are performed by implanting BF ₂ ions of 2.0E12 dose with energy of 50 KeV. Subsequently, the photoresist pattern 106 is removed, another photoresist pattern 108 for exposing the memory region is formed, and ion implantation for adjusting the threshold voltage of the memory region is subsequently performed. At this time, the ion implantation conditions are ion implanted with energy of 50KeV of 1.2E13 dose of BF ₂ ions. In other words, ion implantation is carried out in two stages.

1E and 1F, the other photoresist pattern 108 is removed from the resultant, and the first gate insulating layer 104 exposed in the damaged state due to ion implantation is removed by an etching process. Next, the second gate insulating layer 110 is formed on the entire surface of the semiconductor substrate from which the first gate insulating layer 104 is removed. Thereafter, the photoresist pattern 112 exposing the logic device region and the memory region is formed, and all exposed second gate insulating layers 110 are removed.

1G and 1H, the photoresist pattern 112 is removed and a third gate insulating film is formed on the entire surface of the semiconductor substrate. In this case, a gate insulating film having a thickness in which the second gate insulating film 110 and the third gate insulating film 114 are combined is formed in the I / O region, and a gate insulating film having a thickness of the third gate insulating film 114 in the logic device region and the memory region. Is formed. Here, the I / O region is an area to which a 5V power supply voltage is applied, and the logic element area and a memory area are an area to which a 3V power supply voltage is applied. Subsequently, gate patterns 116 are formed in the respective regions.

1I and 1J, after the photoresist pattern 118 exposing the memory region is formed, ion implantation for source / drain formation of the memory region is primarily performed. Under the ion implantation conditions, P ⁺ ions of 2.0E13 dose are ion-implanted at an energy of 30 KeV. Thereafter, the photoresist pattern 118 is removed, and another photoresist pattern 120 is formed to expose the I / O region and the logic element region, and source / drain formation of the I / O region and the logic element region is performed. Proceed with ion implantation. Ion implantation condition at this time is, the second ion implantation after the first ion implantation of As ⁺ ion dose of 3.0E13 to the energy of 40KeV, and then the As ⁺ ion dose of 1.0E13 to the energy of 60KeV.

However, in the above-described conventional technique, the ion implantation for the threshold voltage and the ion implantation for the source / drain formation in the logic element region and the memory region must be separately performed due to the thickness limitation of the gate insulating film. As a result, the overall manufacturing process of the mixed semiconductor device of logic and DRAM is long and complicated.

SUMMARY OF THE INVENTION The present invention provides a method for manufacturing a mixed semiconductor device of logic and DRAM which can apply the same thickness of the gate insulating film of an I / O region and a memory region of a logic element while dramatically shortening an ion implantation process. It is.

In order to achieve the above technical problem, in the mixed semiconductor device of logic and DRAM having an I / O region, a logic element region, and a memory region, a well of each region is formed on a semiconductor substrate. A first step of forming an ion implantation for performing the ion implantation, an ion implantation for adjusting the threshold voltage of each region, but simultaneously using a mask without using a mask; and a second gate on the semiconductor substrate A third step of forming an insulating film, a fourth step of etching the second gate insulating film in an exposed state by using a mask that opens only a logic element region on the semiconductor substrate, and removing the mask and depositing the entire surface of the semiconductor substrate. Forming a three-gate insulating film, the fifth step of forming a gate insulating film having the same thickness in the I / O region and the memory region; And a seventh step of performing ion implantation for source and drain formation in the I / O region, the logic element region, and the memory region at the same time without using a mask. It provides a method for manufacturing a mixed semiconductor device of logic and DRAM.

According to a preferred embodiment of the present invention, it is preferable to further form a first gate insulating film on the entire surface of the semiconductor substrate before the first step, and to further remove the first gate insulating film after the second step.

Preferably, the ion implantation conditions for adjusting the threshold voltage of each region of the second step, it is suitable to implant the BF ₂ ions of 2.0E12 ± 10% dose with energy of 50KeV ± 10% . It is preferable that the thickness of the second gate insulating film of the third step is in the range of 120 mA ± 20%.

According to a preferred embodiment of the present invention, the gate insulating film thickness of the logic region and the memory region may be different from each other in the fifth step, and the overall gate insulating film thickness of the logic region is in the range of 70Å ± 20%. The overall gate insulating film thickness of the I / O region and the memory region is preferably in the range of 140 to 150 Å.

In the seventh step, the ion implantation conditions for the source and drain formation, it is preferable that the ion implantation of the P ion of 4.0E13 ± 10% dose, the energy of 30KeV ± 10%.

According to the present invention, the number of processes can be drastically reduced in the process of manufacturing a mixed semiconductor device of logic and DRAM, and the advantages of the high capacity of the high speed memory device of the logic device can be utilized in one semiconductor chip.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments disclosed in the following detailed description are not meant to limit the present invention, but to those skilled in the art to which the present invention pertains, the disclosure of the present invention may be completed in a form that can be implemented. It is provided to inform the category.

The gate pattern used in the present specification is used in the widest sense and does not limit only a specific shape as shown in the drawings. The invention can be practiced in other ways without departing from its spirit and essential features. For example, in the following preferred embodiment, the gate pattern is a structure in which a gate electrode made of polysilicon and a silicide layer are laminated, but structures such as a capping layer and a gate spacer made of a nitride film are formed on the gate pattern. You may add it. Therefore, the content described in the following preferred embodiments is exemplary and not intended to be limiting.                     

2 is a cross-sectional view illustrating a method of manufacturing a mixed semiconductor device of logic and DRAM according to the present invention.

Referring to FIGS. 2A and 2B, an isolation layer 202 is formed on the semiconductor substrate 200 to form an isolation layer 202, and an I / O region, a logic region, and a memory region of a mixed semiconductor device of logic and DRAM. Define each one. Subsequently, after the first gate insulating layer 204 is formed, ion implantation 206 is performed to form a well (not shown) in the semiconductor substrate in which the respective regions are defined.

Referring to FIG. 2C, the ion implantation 208 for adjusting the threshold voltage (Vth) is performed on the semiconductor substrate on which the ion implantation is completed. In one ion implantation process, ion implantation 208 is simultaneously performed in the I / O region, the logic element region, and the memory region, respectively. At this time, the ion implantation condition is 2.0F 12 ± 10% dose of BF ₂ ⁺ Ions can be implanted with energy of 50 KeV ± 10%. Therefore, the amount of impurities implanted into the ion is changed in the memory region compared with the conventional art.

2D and 2E, the first gate insulating layer 204 exposed in the damaged state due to ion implantation is removed by an etching process. Next, a second gate insulating film 210 is formed on the entire surface of the semiconductor substrate from which the first gate insulating film 204 is removed. The thickness of the second gate insulating layer 210 may be adjusted within a range of 120 μs ± 20%. Thereafter, the photoresist pattern 212 exposing only the logic device region is formed, and all of the exposed second gate insulating layers 210 are removed. Next, the photoresist pattern 212 is removed.

Referring to FIG. 2F, a third gate insulating layer 214 is grown on the semiconductor substrate from which the photoresist pattern is removed. At this time, the thickness of the third gate insulating film 214 to be grown is suitably in the range of 70 kΩ ± 20%. However, in the logic element region made of single crystal silicon, an oxide film, which is a gate insulating film of about 70 kW, is grown. However, in the I / O region and the memory region where the second gate insulating film 210 having the thickness of about 120 GPa is already formed, the oxide film of 70 GPa does not grow, and the third gate insulating film 214 of about 20 to 30 GPa is grown. As a result, the overall gate insulating film has a thickness of 140 to 150 kPa. Here, the I / O region is a region where a voltage of 5V is applied, and the logic element region and a memory region are regions where a 3V power supply voltage is applied. Although the thickness of the entire gate oxide film is increased in the memory region, the operation is not a problem by compensating for this by changing the amount of impurities implanted into the lower portion.

Referring to FIG. 2G, a gate pattern, for example, a gate electrode made of polysilicon, and a gate pattern 216 having a structure in which tungsten silicide is stacked are formed on a semiconductor substrate on which the third gate insulating layer 214 is formed.

Referring to FIG. 2H, ion implantation is performed to form a source / drain region of each region on the entire surface of the semiconductor substrate on which the gate pattern 216 is formed, but ion implantation is performed at the same time without using a mask. The ion implantation condition at this time is P ⁺ of 4.0E13 dose. Ions are implanted at an energy of 30 KeV. That is, in the prior art, ion implantation is performed on the logic region and the memory region, respectively. However, in the present invention, the operation of the mixed semiconductor device of the logic and the DRAM can be performed even with one ion implantation. Can be reduced.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.

Therefore, according to the present invention described above, first, the process simplification can be achieved by simultaneously performing the ion implantation process applied to the logic device and the memory device differently at the same time.

Second, by achieving the above process simplification and applying the same thickness of the gate insulating film of the I / O region and the memory region, it is possible to simultaneously realize the large-capacity characteristics of the DRAM and the high transferability of the logic elements in a single semiconductor chip. .

Claims (9)

In a mixed semiconductor device of logic and DRAM having an I / O region, a logic element region, and a memory region, A first step of forming an ion implantation for forming a well of each region in a semiconductor substrate; A second step of performing ion implantation for adjusting the threshold voltage (Vth) of each region, but simultaneously and simultaneously without using a mask; Forming a second gate insulating film on the semiconductor substrate; A fourth step of removing the second gate insulating layer in an exposed state by using a mask that opens only a logic element region in the semiconductor substrate; Removing a mask to form a third gate insulating film on the entire surface of the semiconductor substrate, and forming a gate insulating film having the same thickness in the I / O region and the memory region; Forming a gate pattern in each of the regions; And And a seventh step of performing ion implantation to form a source and a drain in the I / O region, the logic element region, and the memory region at the same time without using a mask. Mixed semiconductor device manufacturing method. The method of claim 1, And forming a first gate insulating film on the entire surface of the semiconductor substrate before the first step. The method of claim 1, And removing the first gate insulating layer after the second step. The method of claim 1, The ion implantation conditions for adjusting the threshold voltage of each region of the second step is, BF ₂ ⁺ of 2.0E12 ± 10% dose A method for manufacturing a mixed semiconductor device of logic and DRAM, wherein the ion is implanted with energy of 50 KeV ± 10%. The method of claim 1, The second gate insulating film of the third step is a thickness of 120Å ± 20% range, characterized in that the logic and DRAM mixed semiconductor device manufacturing method. The method of claim 1, And the gate insulating thicknesses of the logic device region and the memory region are different from each other in the fifth step. The method of claim 1, In the fifth step, the thickness of the gate insulating layer of the logic device region is 70Å ± 20% range, characterized in that the logic and DRAM mixed semiconductor device manufacturing method. The method of claim 1, In the fifth step, the overall gate insulating film thickness of the I / O region and the memory region ranges from 140 to 150Å, the method of manufacturing a mixed semiconductor device of logic and DRAM. The method of claim 1, In the seventh step, the ion implantation conditions for forming the source and drain is a mixed semiconductor of logic and DRAM, characterized in that the ion implantation of P ⁺ ions of 4.0E13 ± 10% dose, 30KeV ± 10% energy Device manufacturing method.

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