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KR100680950B1 - Method for manufacturing of fbga package - Google Patents

Method for manufacturing of fbga package Download PDF

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Publication number
KR100680950B1
KR100680950B1 KR1020040088837A KR20040088837A KR100680950B1 KR 100680950 B1 KR100680950 B1 KR 100680950B1 KR 1020040088837 A KR1020040088837 A KR 1020040088837A KR 20040088837 A KR20040088837 A KR 20040088837A KR 100680950 B1 KR100680950 B1 KR 100680950B1
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fbga
substrate
wire
semiconductor chip
attached
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KR20060039652A (en
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유승용
고광덕
조한력
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0655—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 FBGA 패키지 공정 중 와이어 본더(wire bonder)의 순간정지 에러(error)를 개선할 수 있는 FBGA 패키지 제조방법을 개시한다. 개시된 본 발명은, 웨이퍼로부터 개별 반도체 칩으로 분리된 반도체 칩들이 FBGA용 기판 상에 다수 개 부착되고, 상기 FBGA용 기판 상에 부착된 상기 반도체 칩들 중 불량이 발생된 반도체 칩이 상기 FBGA용 기판으로부터 제거되고, 와이어 본딩 공정을 통해 반도체 칩의 본딩패드와 FBGA용 기판의 금속배선이 전기적으로 연결되며, 와이어 본딩된 부분과 반도체 칩의 상부면이 밀봉되고, FBGA용 기판 금속배선의 볼 랜드에 솔더 볼이 부착되는 FBGA 패키지의 제조방법에 있어서, 와이어 본딩 전에 FBGA용 기판 상에서 반도체 칩이 제거되어 반도체 칩이 부착되지 않은 부분마다 미리 별도의 패턴을 형성하고, 와이어 본딩시 와이어 본더가 반도체 칩이 부착되지 않은 부분을 발견하는 경우에는 FBGA용 기판 상에 미리 형성된 별도의 패턴을 인식하여 자동 스킵(skip)함으로써 와이어 본딩시 와이어 본더가 순간 정지하는 에러를 방지할 수 있는 것을 특징으로 한다.The present invention discloses a method for manufacturing an FBGA package that can improve an instant stop error of a wire bonder during an FBGA package process. According to the present invention, a plurality of semiconductor chips separated from a wafer into individual semiconductor chips are attached to a substrate for an FBGA, and a semiconductor chip in which a defect occurs among the semiconductor chips attached to the substrate for an FBGA is formed from the substrate for the FBGA. And the wire bonding process electrically connects the bonding pad of the semiconductor chip and the metal wiring of the FBGA substrate, seals the wire bonded portion and the upper surface of the semiconductor chip, and solders to the ball lands of the FBGA substrate metal wiring. In the manufacturing method of the FBGA package to which the ball is attached, before the wire bonding, the semiconductor chip is removed from the FBGA substrate to form a separate pattern in advance for each portion where the semiconductor chip is not attached, and the wire bonder is attached to the wire bonder during wire bonding. If it finds an unseen part, it automatically skips by recognizing a separate pattern previously formed on the FBGA substrate. As it is characterized in that to avoid the error to stop the wire bonder when wire-bonding moment.

Description

ＦＢＧＡ 패키지의 제조방법{METHOD FOR MANUFACTURING OF FBGA PACKAGE}Manufacturing method of FAH package {METHOD FOR MANUFACTURING OF FBGA PACKAGE}

도 1은 종래 FBGA용 기판을 설명하기 위한 도면.1 is a view for explaining a conventional substrate for FBGA.

도 2는 본 발명의 실시예에 따른 기판을 설명하기 위한 도면.2 is a view for explaining a substrate according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100 : FBGA용 기판 120 : 별도의 패턴100: FBGA substrate 120: separate pattern

본 발명은 FBGA 패키지의 제조방법에 관한 것으로, 보다 상세하게는, FBGA 패키지 공정 중 와이어 본더(wire bonder)의 순간정지 에러(error)를 개선할 수 있는 FBGA 패키지의 제조방법에 관한 것이다.The present invention relates to a manufacturing method of the FBGA package, and more particularly, to a manufacturing method of the FBGA package that can improve the instantaneous error of the wire bonder (wire bonder) during the FBGA package process.

반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지속적으로 발전되고 있다. 예컨데, 소형화에 대한 요구는 칩 크기에 근접한 패키지에 대한 기술 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키징 기술에 대한 중요성을 부각시키고 있다. In the semiconductor industry, packaging technology for integrated circuits is continuously developed to meet the demand for miniaturization and mounting reliability. For example, the demand for miniaturization is accelerating the development of technologies for packages close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting operations and the mechanical and electrical reliability after mounting. I'm making it.

상기 패키지의 소형화를 이룬 한 예로서, FBGA(Fine-Pitch Ball Grid Array ) 패키지를 들 수 있다. 상기 FBGA 패키지는 전체적인 패키지의 크기가 반도체 칩의 크기와 동일하거나 거의 유사하며, 특히, 외부와의 전기적 접속 수단, 즉, 인쇄회로기판(Printed Circuit Board : 이하, PCB)에의 실장 수단으로서, 솔더 볼이 구비됨에 따라 실장 면적이 감소되고 있는 추세에 매우 유리하게 적용할 수 있다는 잇점이 있다.One example of the miniaturization of the package is a fine pitch pitch grid array (FBGA) package. The FBGA package has an overall package size that is substantially the same as or similar to that of a semiconductor chip. In particular, the FBGA package is a solder ball as a means for mounting to an external device, that is, a printed circuit board (PCB). This has the advantage that it can be very advantageously applied to the trend that the mounting area is reduced.

통상적으로 FBGA 패키지는 반도체 칩들이 복수개의 열과 행으로 형성된 웨이퍼를 절단하여 상기 반도체 칩들을 개별적으로 분리하는 공정을 진행한 후에 분리된 반도체 칩들을 FBGA용 기판 상에 부착한다. 이어서, 와이어 본딩을 통해 반도체 칩의 본딩패드와 FBGA용 기판의 금속배선이 전기적으로 연결되고, 상기 와이어 본딩부 및 반도체 칩의 상부면이 밀봉되고, 상기 FBGA용 기판 금속배선의 볼 랜드에 솔더 볼이 부착된다.In general, an FBGA package cuts a wafer in which semiconductor chips are formed in a plurality of columns and rows, and then separates the semiconductor chips, and attaches the separated semiconductor chips onto a FBGA substrate. Subsequently, the bonding pad of the semiconductor chip and the metal wiring of the FBGA substrate are electrically connected through wire bonding, the wire bonding portion and the upper surface of the semiconductor chip are sealed, and solder balls are formed on the ball lands of the FBGA substrate metal wiring. Is attached.

그러나, 도 1에 도시된 바와 같이, FBGA용 기판(10) 상에 부착된 복수 개의 반도체 칩들(20) 중에 반도체 칩의 본딩패드 및 다이 어태치(die attatch) 공정으로 인해 발생된 불량 반도체 칩들(30a, 30b)이 존재하게 된다. 여기에서, 불량 반도체 칩들은 도 2a 내지 도 2b에 도시된 바와 같이, 레이저 마킹(laser marking)을 통해 "X" 또는 "ㅇ" 형태로 표시되며, "X" 또는 "ㅇ" 형태로 레이저 마킹된 불량 반도체 칩들(30a, 30b)은 FBGA용 기판(10)으로부터 제거된다. 이로 인해, FBGA용 기판(10) 상에서 불량 반도체 칩들(30a, 30b)이 부착되었던 부분에는 반도체 칩이 존재하지 않으므로, 와이어 본더(wire bonder)가 반도체 칩을 인식하지 못해서 FBGA용 기판 당 4∼6번의 순간정지 에러가 발생하게 된다. 그러므로, 와이어 본더는 한 달에 대략 2,500,000번의 순간정지 에러가 발생하게 되고, 이로 인해 제품 수율이 저하되는 문제점이 있다.However, as shown in FIG. 1, out of the plurality of semiconductor chips 20 attached to the FBGA substrate 10, the defective semiconductor chips generated by the bonding pad and the die attatch process of the semiconductor chip ( 30a, 30b) will be present. Here, the defective semiconductor chips are represented in the form of "X" or "o" through laser marking, as shown in FIGS. 2A to 2B, and are laser marked in the form of "X" or "o". The defective semiconductor chips 30a and 30b are removed from the FBGA substrate 10. As a result, since the semiconductor chip does not exist in the portion where the defective semiconductor chips 30a and 30b are attached on the FBGA substrate 10, the wire bonder does not recognize the semiconductor chip and thus 4 to 6 per FBGA substrate. Stop error occurs. Therefore, the wire bonder generates approximately 2,500,000 instantaneous stop errors per month, which causes a problem in that the yield of the product is lowered.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, FBGA용 기판에 별도의 패턴을 형성함으로써 FBGA 패키지 공정 중 와이어 본더의 순간정지에러를 개선할 수 있는 FBGA 패키지의 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, by providing a separate pattern on the FBGA substrate to provide a method of manufacturing a FBGA package that can improve the instantaneous stop error of the wire bonder during the FBGA package process. The purpose is.

상기와 같은 목적을 달성하기 위한 본 발명은, 웨이퍼로부터 개별 반도체 칩으로 분리된 상기 반도체 칩들이 FBGA용 기판 상에 다수 개 부착되고, 상기 FBGA용 기판 상에 부착된 상기 반도체 칩들 중 불량이 발생된 반도체 칩이 상기 FBGA용 기판으로부터 제거되고, 와이어 본딩 공정을 통해 상기 반도체 칩의 본딩패드와 FBGA용 기판의 금속배선이 전기적으로 연결되며, 상기 와이어 본딩된 부분과 상기 반도체 칩의 상부면이 밀봉되고, 상기 FBGA용 기판 금속배선의 볼 랜드에 솔더 볼이 부착되는 FBGA 패키지의 제조방법에 있어서, 상기 와이어 본딩 전에 상기 FBGA용 기판 상에서 상기 반도체 칩이 제거되어 상기 반도체 칩이 부착되지 않은 부분마다 미리 별도의 패턴을 형성하고, 상기 와이어 본딩시 와이어 본더가 상기 반도체 칩이 부착되지 않은 부분을 발견하는 경우에는 상기 FBGA용 기판 상에 미리 형성된 별도의 패턴을 인식하여 자동 스킵(skip)함으로써 상기 와이어 본딩시 상기 와이어 본더가 순간 정지하는 에러를 방지하는 FBGA 패키지의 제조방법을 제공한다.According to the present invention for achieving the above object, a plurality of the semiconductor chips separated from the wafer into individual semiconductor chips are attached to the FBGA substrate, the failure of the semiconductor chips attached on the FBGA substrate The semiconductor chip is removed from the FBGA substrate, the bonding pad of the semiconductor chip and the metal wiring of the FBGA substrate are electrically connected through a wire bonding process, and the wire bonded portion and the upper surface of the semiconductor chip are sealed. In the manufacturing method of the FBGA package in which solder balls are attached to the ball land of the FBGA substrate metal wiring, the semiconductor chip is removed on the FBGA substrate before the wire bonding, so that the semiconductor chip is separately attached to each portion where the semiconductor chip is not attached. Form a pattern, and the wire bonder finds the portion where the semiconductor chip is not attached during the wire bonding If there provides a process for the preparation of FBGA package to prevent an error to stop when the wire bonding the wire bonder moment by automatically skip (skip) to recognize the separate pattern previously formed on the substrate for the FBGA.

여기에서, 상기 별도의 패턴은 FBGA용 기판에 형성된 파워 라인의 솔더 레지스트를 제거하여 형성하는 것을 특징으로 한다.Here, the separate pattern is formed by removing the solder resist of the power line formed on the FBGA substrate.

상기 별도의 패턴은 "I" 형태를 제외시키고 형성하는 것을 특징으로 한다.The separate pattern is formed to exclude the "I" form.

(실시예)(Example)

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 보다 상세하게 설명하도록 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3는 본 발명의 실시예에 따른 FBGA용 기판을 설명하기 위한 도면이다.3 is a view for explaining a substrate for an FBGA according to an embodiment of the present invention.

본 발명은 반도체 칩들이 복수개의 열과 행으로 형성된 웨이퍼를 절단하여 상기 반도체 칩들을 개별적으로 분리하는 공정을 진행한 후에 분리된 반도체 칩들을 FBGA용 기판 상에 부착한다. 이어서, 와이어 본딩 공정이 진행되는데, 도 3에 도시된 바와 같이, FBGA용 기판(10) 상에 부착된 복수 개의 반도체 칩들(20) 중에 반도체 칩의 본딩패드 및 다이 어태치(die attatch) 공정 불량으로 인해 불량 반도체 칩들이 존재하게 되며, 불량이 발생된 반도체 칩들은 FBGA용 기판(100)으로부터 제거된다. 따라서, FBGA용 기판(100)에서 불량 반도체 칩들이 부착되었던 부분에는 반도체 칩이 존재하지 않게 된다. 이로 인해, 본 발명에서는 와이어 본딩시 와이어 본더가 순간정지하는 에러를 방지하기 위해 FBGA용 기판(100) 중 불량 반도체 칩이 제거된 자리에 별도의 패턴(120)을 형성한다. 여기에서, 상기 별도의 패턴(120)은 FBGA용 기판(100)에 형성된 파워 라인의 솔더 레지스트(solder resist)를 제거하여 형성한다. 이때, 상기 별도의 패턴(120)은 FBGA용 기판(100)의 가장자리 부분에 "I" 형태를 제외한 어떠한 형태로든 형성할 수 있다. 그 이유는 별도의 패턴을 "I" 형태로 형성하게 되면, 칩 패턴과 같은 형태를 갖으므로, 와이어 본더가 잘못 인식할 수 있기 때문이다.According to the present invention, the semiconductor chips are cut into a plurality of columns and rows, and the separated semiconductor chips are attached onto the FBGA substrate. Subsequently, a wire bonding process is performed. As illustrated in FIG. 3, a bonding pad and a die attatch process of the semiconductor chip are defective among the plurality of semiconductor chips 20 attached to the FBGA substrate 10. Due to this, there are defective semiconductor chips, and the defective semiconductor chips are removed from the FBGA substrate 100. Therefore, the semiconductor chip does not exist in the portion where the defective semiconductor chips are attached to the FBGA substrate 100. For this reason, in the present invention, in order to prevent an error in which the wire bonder stops momentarily during wire bonding, a separate pattern 120 is formed in a place where the defective semiconductor chip is removed from the FBGA substrate 100. Here, the separate pattern 120 is formed by removing a solder resist of a power line formed on the FBGA substrate 100. In this case, the separate pattern 120 may be formed in any shape except for the “I” shape on the edge portion of the FBGA substrate 100. The reason for this is that when the separate pattern is formed in the form of "I", since it has the same shape as the chip pattern, the wire bonder may recognize it incorrectly.

그 다음, 상기 와이어 본딩시 와이어 본더가 FBGA용 기판(100)에 형성된 별도의 패턴(120)을 인식하게 되면, 와이어 본딩을 진행하지 않고 자동으로 스킵하게 되어 와이어 본더가 순간정지하는 에러를 방지할 수 있다.Then, when the wire bonder recognizes a separate pattern 120 formed on the FBGA substrate 100 during wire bonding, the wire bonder skips automatically without proceeding wire bonding to prevent an error that the wire bonder stops momentarily. Can be.

상기와 같이, 본 발명은 FBGA용 기판 상에 부착된 복수 개의 반도체 칩들 중에는 불량 반도체 칩들이 존재하게 되는데, 와이어 본딩시 상기 불량 반도체 칩들은 FBGA용 기판 상에 부착되어 있지 않으므로, 와이어 본더가 칩을 인식하지 못해서 순간정지하는 에러가 발생하는 종래 공정과 달리, FBGA용 기판의 파워 라인의 솔더 레지스트를 제거하여 별도의 패턴을 형성함으로써 와이어 본딩시 와이어 본더가 FBGA용 기판에 미리 형성된 별도의 패턴을 인식하여 순간정지하는 에러 없이 자동으로 스킵하여 와이어 본딩 공정을 진행하여 제품 수율을 향상시킬 수 있다.As described above, in the present invention, among the plurality of semiconductor chips attached to the FBGA substrate, the defective semiconductor chips exist. In the wire bonding, since the defective semiconductor chips are not attached to the FBGA substrate, the wire bonder is used for the chip. Unlike conventional processes in which an error occurs due to an uninterrupted error, a separate pattern is formed by removing the solder resist of the power line of the FBGA substrate so that the wire bonder recognizes a separate pattern previously formed on the FBGA substrate during wire bonding. By skipping automatically without error to stop the wire bonding process to improve the product yield.

이상, 본 발명을 몇 가지 예를 들어 설명하였으나, 본 발명은 이에 한정되는 것은 아니며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 본 발명의 사상에서 벗어나지 않으면서 많은 수정과 변형을 가할 수 있음을 이해할 것이다.In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and a person of ordinary skill in the art may make many modifications and variations without departing from the spirit of the present invention. I will understand.

이상에서 설명한 바와 같이, 본 발명은 FBGA용 기판에 별도의 패턴을 형성함으로써 와이어 본딩시 와이어 본더가 FBGA용 기판에 미리 형성된 별도의 패턴을 인식하여 순간정지하는 에러 없이 자동으로 스킵하여 와이어 본딩 공정을 진행함으로 인해 제품 수율을 향상시킬 수 있다.As described above, the present invention forms a separate pattern on the FBGA substrate so that the wire bonder recognizes the separate pattern formed on the FBGA substrate in advance and automatically skips the wire bonding process without error. As a result, product yields can be improved.

Claims (3)

웨이퍼로부터 개별 반도체 칩으로 분리된 상기 반도체 칩들이 FBGA용 기판 상에 다수 개 부착되고, 상기 FBGA용 기판 상에 부착된 상기 반도체 칩들 중 불량이 발생된 반도체 칩이 상기 FBGA용 기판으로부터 제거되고, 와이어 본딩 공정을 통해 상기 반도체 칩의 본딩패드와 FBGA용 기판의 금속배선이 전기적으로 연결되며, 상기 와이어 본딩된 부분과 상기 반도체 칩의 상부면이 밀봉되고, 상기 FBGA용 기판 금속배선의 볼 랜드에 솔더 볼이 부착되는 FBGA 패키지의 제조방법에 있어서,A plurality of the semiconductor chips separated from the wafer into individual semiconductor chips are attached on the FBGA substrate, and a defective semiconductor chip of the semiconductor chips attached on the FBGA substrate is removed from the FBGA substrate, and the wire The bonding pad of the semiconductor chip and the metal wiring of the FBGA substrate are electrically connected through a bonding process, the wire bonded portion and the upper surface of the semiconductor chip are sealed, and soldered to the ball lands of the FBGA substrate metal wiring. In the manufacturing method of the FBGA package to which the ball is attached, 상기 와이어 본딩 전에 상기 FBGA용 기판 상에서 상기 반도체 칩이 제거되어 상기 반도체 칩이 부착되지 않은 부분마다 미리 별도의 패턴을 형성하고, 상기 와이어 본딩시 와이어 본더가 상기 반도체 칩이 부착되지 않은 부분을 발견하는 경우에는 상기 FBGA용 기판 상에 미리 형성된 별도의 패턴을 인식하여 자동 스킵(skip)함으로써 상기 와이어 본딩시 상기 와이어 본더가 순간 정지하는 에러를 방지할 수 있는 것을 특징으로 하는 FBGA 패키지의 제조방법.Before the wire bonding, the semiconductor chip is removed on the FBGA substrate to form a separate pattern in advance for each portion where the semiconductor chip is not attached, and the wire bonder discovers a portion where the semiconductor chip is not attached during the wire bonding. In the case of the FBGA package manufacturing method characterized in that it is possible to prevent the error that the wire bonder is momentarily stopped during the wire bonding by recognizing a separate pattern previously formed on the FBGA substrate. 제 1 항에 있어서, 상기 별도의 패턴은 상기 FBGA용 기판에 형성된 파워 라인의 솔더 레지스트를 제거하여 형성하는 것을 특징으로 하는 FBGA 패키지의 제조방법.The method of claim 1, wherein the separate pattern is formed by removing a solder resist of a power line formed on the FBGA substrate. 제 1 항에 있어서, 상기 별도의 패턴은 "I" 형태를 제외시키고 형성하는 것을 특징으로 하는 FBGA 패키지의 제조방법.The method of claim 1, wherein the separate pattern is formed without forming an "I" shape.
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