KR100691001B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

The present invention discloses a manufacturing method that simplifies a manufacturing process, comprising: providing a first and a second substrate, forming a capacitor on one surface of the first substrate, and forming a first substrate on the first substrate including the capacitor. Forming an insulating film, bonding a second substrate on the first insulating film of the first substrate, inverting the resultant so that the other surface of the first substrate is disposed in an upward direction, and forming the other surface of the first substrate Polishing to a thickness, forming a device isolation film defining an active region by performing an isolation process on the first substrate having completed the polishing process, and sequentially forming a gate line and a bit line on the active region of the first substrate. Steps.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1 and 2 are layout views illustrating a method of manufacturing a semiconductor device according to the prior art.

3A to 3I are cross-sectional views illustrating a cutting plane taken along line A-B in FIGS. 1 and 2;

Figures 4a to 4e is a cross-sectional view showing a cross section of the C-D line of Figs.

5A to 5D are cross-sectional views illustrating a cutting plane taken along line E-F in FIGS. 1 and 2.

6 and 7 are layout views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

8A to 8I are cross-sectional views of the cutting lines taken along the line G-H of FIGS. 6 and 7.

9A to 9I are cross-sectional views illustrating a cutting plane taken along line I-J of FIGS. 6 and 7.

10 is a plan view in which active regions are arranged side by side in accordance with each row and column;

As an example, the active regions of each row are arranged side by side in accordance with each column.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device with a simplified manufacturing process.                         

In general, a DRAM manufacturing process of a semiconductor device is performed in order of an isolation process, a gate electrode formation process, a bit line formation process, a capacitor formation process, and a metal wiring formation process.

1 and 2 are layout views illustrating a method of manufacturing a semiconductor device according to the prior art. FIG. 1 is a layout view of a semiconductor device in which an isolation process, a gate line forming process, and a landing plug forming process are performed. FIG. 1 is a layout diagram of a semiconductor device in which processes subsequent to FIG. 1, that is, a bit line contact forming process, a bit line forming process, a storage node contact forming process, and a storage node electrode forming process are performed.

3A to 3I are cross-sectional views of the cutting lines of the AB lines of FIGS. 1 and 2, and FIGS. 4A to 4E are cross-sectional views of the CD lines of FIGS. 1 and 2, and FIGS. Process sectional drawing which showed the cut surface of the EF line of FIG.

The semiconductor device manufacturing method according to the related art provides a semiconductor substrate 1 in which a field region (not shown) and an active region (not shown) are defined, as shown in FIGS. 1, 3A, and 4A. Subsequently, a device isolation film 2 is formed by applying a shallow trench isolation (STI) process to the field region of the substrate 1.

Next, as shown in FIGS. 1, 3B, and 4B, after forming the gate line 3 on the substrate including the device isolation layer 2, the first insulating layer 4 covering the structure of the gate line 3 is formed. ). Thereafter, ion implantation is performed on the entire substrate using the gate line 3 as a mask to form respective source / drain regions S1 / D1 (shown in FIG. 1) on the lower substrates on both sides of the gate line 3. .                         

3C and 4C, after the first insulating film 4 is CMP, the first insulating film is selectively etched to form a contact hole 5 exposing the source region or the drain region. Subsequently, a conductive plug 6 filling the contact hole 5 is formed.

Then, as shown in FIG. 3D, the second insulating film 7 is formed on the entire surface of the substrate including the conductive plug 6. Then, as shown in FIG. 4D, the second insulating film is selectively etched to form the conductive plug ( A bit line contact 8 exposing 6) is formed.

Thereafter, as shown in FIGS. 3E and 4E, after forming the bit line 9 to fill the bit line contact 8, the third insulating layer 10 is formed on the entire surface of the bit line 9 structure. do. At this time, although not shown in the figure, an insulating spacer is formed on the side surface of the bit line 9 to prevent a short circuit with the capacitor in a subsequent process.

3F and 5A, the third and second insulating layers are selectively etched to form a storage node contact 11, and as shown in FIGS. 3G and 5B, the storage node contacts are etched. A landing plug 12 for embedding 11 is formed.

Then, as illustrated in FIGS. 3H and 5C, a fourth insulating layer 13 is formed on the entire surface of the substrate including the landing plug 12.

After that, as shown in FIGS. 3I and 5D, the fourth insulating layer is selectively etched to form a contact hole 14 exposing the landing plug 12, and then the inside of the contact hole 14 is covered. The storage node electrode 15 of the capacitor connected to the landing plug 12 is formed. Thereafter, the dielectric film 16 and the plate electrode 17 covering the storage node electrode 15 of the capacitor are sequentially formed.

In general, the gate line and the bit line are orthogonal to each other, and the bit line contact is ideally formed at the center of the source region because the bit line should be connected to the source region.

However, in the semiconductor device manufacturing process according to the prior art, after the isolation process, the gate line forming process, the bit line forming process, and the capacitor forming process are sequentially performed, but the bit line passes over the drain region where the capacitor should be formed. There was a problem that the ideal arrangement was impossible.

In addition, since the bit line contact in the cell region and the bit line contact in the peripheral circuit region cannot be etched at the same time, the bit line contact process is performed twice, which complicates the manufacturing process of the semiconductor device. In addition, by forming a landing plug in the drain of the active region to manufacture a capacitor connected to the drain through the landing plug, a separate landing plug forming process must be performed, which leads to a complicated manufacturing process of the semiconductor device.

Therefore, in order to solve the above problems, an object of the present invention is to form a capacitor on a first substrate, and then to bond the second substrate to the other surface of the first substrate on which the capacitor is formed, an isolation process, a gate line forming process, and a bit line forming process. By sequentially proceeding, etc., a separate landing plug is unnecessary, and the manufacturing method of a semiconductor device can be simplified by reducing the process of forming a bit line contact twice in one cycle.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of providing a first and a second substrate, forming a capacitor on one surface of the first substrate, the first substrate on the first substrate including the capacitor Forming an insulating film, bonding a second substrate on the first insulating film of the first substrate, inverting the resultant so that the other surface of the first substrate is disposed in an upward direction, and forming the other surface of the first substrate Polishing to a thickness, forming a device isolation film defining an active region by performing an isolation process on the first substrate having completed the polishing process, and sequentially forming a gate line and a bit line on the active region of the first substrate. Characterized in that it comprises a step.

In this case, the second substrate may be any one of a silicon wafer, a glass substrate, and a plastic substrate.

(Example)

6 and 7 are layout views illustrating a method of manufacturing a semiconductor device according to the present invention. FIG. 6 is a layout view illustrating a semiconductor device in which a capacitor forming process is performed. FIG. 7 is a gate line forming process and a bit line forming process. This is a layout diagram of the semiconductor elements respectively advanced.

8A to 8I are process cross-sectional views showing the cut lines of the G-H lines of FIGS. 6 and 7, and FIGS. 9A to 9I are the process cross-sectional views showing the cut lines of the lines I-J of FIGS. 6 and 7.

In the method of manufacturing a semiconductor device according to the present invention, as shown in FIGS. 6, 8A, and 9A, a first insulating layer 21 is formed on one surface of a first substrate 20 made of silicon, and then the first insulating layer 21 is formed. The insulating layer is selectively etched to form the storage node contact 22.

Then, as shown in FIGS. 8B and 9B, a conductive plug 23 for filling the storage node contact 22 is formed, and then a second insulating layer 24 is formed over the entire structure.

8C and 9C, the second insulating layer is selectively etched to form a contact hole 25 exposing the conductive plug 24, and then covers the inside of the contact hole 25 to cover the conductive plug ( The storage node electrode 26 of the capacitor connected to 24 is formed. Subsequently, the dielectric layer 27 and the plate electrode 28 are sequentially formed on the storage node electrode 26 of the capacitor.

Then, as shown in FIGS. 8D and 9D, a third insulating film 29 is formed on the plate electrode 28 structure.

Thereafter, the second substrate 30 on which the first insulating film 31 is formed is provided. Here, the second substrate 30 uses any one of a silicon substrate, a glass substrate, or a plastic substrate.

Subsequently, the second substrate 30 is bonded to the third insulating layer 29 of the first substrate. At this time, the third insulating film 29 of the first substrate and the first insulating film 31 of the second substrate are disposed to be in contact with each other.

Then, as shown in Figs. 8E and 9E, the bonded first and second substrates are turned upside down again so that the other side of the first substrate (the opposite side of the surface on which the capacitor is formed) is placed upward.

Thereafter, as shown in FIGS. 8F and 9F, the other surface of the first substrate is etched to a predetermined thickness.

Next, as shown in FIGS. 7, 8G, and 9G, an isolation process is performed on the other surface of the etched first substrate to form the device isolation layer 40. In this case, reference numeral 20a, which is not described, becomes an active region (a portion indicated by S2 / D2 of FIG. 7).

Then, as shown in FIGS. 8H and 9H, the gate line 41 is formed on the device isolation layer 40 and the active region 20a, and then a fourth insulating layer 42 covering the gate line is formed. .

Thereafter, as shown in FIGS. 8I and 9I, the fourth insulating layer is selectively etched to form a bit line contact 43 exposing the active region, and a bit line filling the bit line contact 43. 44). Next, a fifth insulating layer 45 covering the bit line structure is formed.

10 is a plan view in which the active regions are arranged side by side in accordance with each row and column.

As shown in FIG. 10, in the present invention, the active regions A may be arranged side by side in accordance with each row and each column, so that the cell size may be reduced as compared with a conventional arrangement in which the active regions of each row are staggered regardless of columns. Unexplained reference numeral B denotes a bit line and unexplained reference numeral C denotes a gate line.

As described above, the present invention manufactures a capacitor, proceeds with a device isolation process, and then manufactures a gate line and a bit line in order, thereby forming a landing plug for connecting to a separate source region to form a bit line. This makes the process simple and the manufacturing process is simplified because the contact forming process for the bit line can be performed only once without discriminating the cell region and the peripheral circuit region.

In addition, in the present invention, since the active regions of each row are arranged side by side in accordance with the columns, the cell size can be reduced as compared with the conventional arrangement of the active regions of each row staggered regardless of the columns.

On the other hand, the present invention does not need to form an insulating spacer on the side of the bit line in order to prevent the short circuit with the bit line in the process of connecting the capacitor to the drain region, there is an advantage that the process of forming the insulating spacer of the bit line can be omitted .

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (3)

Providing respective first and second substrates, Forming a capacitor on one surface of the first substrate, Forming a first insulating film on the first substrate including the capacitor; Bonding a second substrate on the first insulating film of the first substrate; Flipping the resultant so that the other surface of the first substrate is disposed upward; Polishing the other surface of the first substrate to a predetermined thickness; Forming an isolation layer defining an active region by performing an isolation process on the first substrate on which the polishing process is completed; And sequentially forming a gate line and a bit line on the active region of the first substrate. The method of claim 1, wherein the second substrate is one of a silicon wafer, a glass substrate, and a plastic substrate. The method of claim 1, wherein the active region is patterned such that the active regions of each row are arranged side by side in accordance with a column.

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