KR100691144B1 - Sigma-delta modulator - Google Patents

Abstract

The present invention relates to a sigma-delta modulator capable of eliminating periodic components appearing at the output of a sigma-delta modulator and reducing noise levels by adding random bits to the input data of the sigma-delta modulator. According to the present invention, a sigma-delta modulator for receiving a predetermined input value and outputting a bit stream having a value between a (+) range and a (-) range includes a pseudo random bit that generates random bits in a predetermined sequence. A sequence (PRBS) generator; A summer for adding up the random bits generated by said random bit generating means with an input of said sigma-delta modulator; And a modulation circuit for sigma-delta modulating an input value obtained by adding the random bits by the adder.

Sigma-Delta Modulator, Fractional N Phase Locked Loop (PLL), Pseudo Random Bis Sequence (PRBS)

Description

Sigma-Delta Modulators {SIGMA DELTA MODULATOR}             

1 is a block diagram showing an example of a conventional sigma-delta modulator.

2A and 2B are diagrams showing the periodicity and noise characteristic test results of a conventional sigma-delta modulator.

3 is a block diagram illustrating a sigma-delta modulator according to the present invention.

4 illustrates an example of a PRBS generator included in a sigma-delta modulator according to the present invention.

5A and 5B illustrate the results of periodicity and noise characteristics test of a sigma-delta modulator according to the present invention.

* Explanation of symbols for main parts of drawings *

30: sigma-delta modulator 31: sigma-delta modulator

32: Pseudo Random Bit Sequence Generator (PRBS) 33: Adder

The present invention relates to a sigma-delta modulator, and more particularly, by adding random bits to the input data of the sigma-delta modulator to remove periodic components appearing at the output of the sigma-delta modulator and to reduce noise levels. A sigma-delta modulator.

In recent years, CDMA 2000 has provided high-speed data services in the conventional CDMA / PCS band so that service subscribers can receive not only high-speed Internet access but also image data in real time using mobile communication terminals. The frequency synthesizer, which is a programmable channel selector required for such a high speed data service, must have a phase locked loop (PLL) bandwidth of at least 10 kHz to meet the demand of fast settling time.

To meet these demands, fractional N PLL circuits are used. Unlike fractional N PLLs, this fractional N PLL allows frequency resolution down to the decimal point, further improving the phase noise characteristics of the PLL and improving switching time. In addition, the fractional N PLL dynamically changes the division values P and P + 1 through time division as the PLL progresses, and employs a high speed prescaler having an average division value to allow high frequency processing and Power consumption can be reduced.

In the case of such a fractional PLL, a high frequency prescaler is employed to obtain an average value while dynamically changing the divided value, thereby obtaining a divided value having a decimal point. One of the ways to dynamically change the division is to use a sigma-delta modulator. The sigma-delta modulator receives the value of the programmable counter and outputs a bit stream with a value between the range of (+) to (-) to change the value of the swallow counter.

1 shows an example of a conventional sigma-delta modulator. The sigma-delta modulator 10 shown in FIG. 1 illustrates one of the various embodiments as an example and is a cubic mesh type sigma-delta comprising three sigma-delta modulators 101, 102, 103. Modulator.

As shown in FIG. 1, the conventional mesh type sigma-delta modulator 10 includes a plurality of delayers 12a to 12h and a plurality of adder and subtractors 11a to 11e. The mesh type sigma-delta modulator 10 configured as described above has a structure in which three primary sigma-delta modulators 101, 102, and 103 are connected.

Briefly describing the operation, the input value inputted to the input terminal of the mesh type sigma-delta modulator 10 is subtracted from the subtractor 11a to a value delayed by the delay unit 12a of the primary sigma-delta modulator 101. do. Likewise, the value delayed in the primary sigma-delta modulator 101 is subtracted from the subtractor 11b to the value delayed again in the delay 12c of the primary sigma-delta modulator 102 and the primary sigma-delta modulator ( The value delayed in delay 12c of 102 is subtracted in subtractor 11c to the value delayed in delay 12e of primary sigma-delta modulator 103. In the subtractor 11d, the value output from the subtractor 11b of the primary sigma-delta modulator 102 is delayed by the delay unit 12d, and the subtractor 11c of the primary sigma-delta modulator 103. The value output from is added, and the value output from the subtractor 11c of the primary sigma-delta modulator 103 is delayed from the delayer 12f. The adder and subtractor 11e delays the value output from the subtractor 11a of the first sigma-delta modulator 101 from the delayers 12b and 12g twice and the value output from the adder and subtractor 11d. In addition, the value output from the adder-subtracter 11d is subtracted from the value delayed by the delayer 12h, and output as the output value of the mesh type sigma-delta modulator 101.

The conventional mesh type sigma-delta modulator 10 having the configuration as shown in FIG. 1 outputs the same data 21 at regular intervals when observing a large number of output samples as shown in FIG. 2A. That is, the conventional sigma-delta modulator 10 has a periodic component at its output. This periodic component of the output of the sigma delta modulator 10 generates a fractional spur during operation of the fractional N PLL in which the sigma delta modulator 10 is used. If the fractional spur is input into the fractional N PLL in-band, there is a problem of deteriorating the operating characteristics of the entire system.

In addition, the periodic component of the conventional sigma-delta modulator 10 has a problem of lowering the noise characteristics of the sigma-delta modulator. In particular, the problem that the noise characteristics are deteriorated in the band below 300kHz which is mainly used in the currently serviced digital communication system is a problem.

The present invention has been made to solve the problems of the prior art, the object of which is to add a random sequence to the input data of the sigma-delta modulator to remove the periodic components appearing at the output of the sigma-delta modulator, and to reduce the noise level It is to provide a sigma-delta modulator that can be reduced.

The present invention as a technical configuration for achieving the above object,

In a sigma-delta modulator that receives a predetermined input value and outputs a bit stream having a value between a (+) range and a (-) range,

A pseudo random bit sequence (PRBS) generation unit generating random bits in a predetermined sequence;

A summer for adding random bits generated by the pseudo random bit sequence generator to an input value of the sigma-delta modulator; And

A sigma-delta modulator including a modulation circuit for sigma-delta modulating an input value summed with random bits by the adder is provided.

In one embodiment of the present invention, the sum of bits generated by the pseudo random bit sequence generator is preferably 0, and the sequence of random bits generated is preferably equal to the operating clock frequency of the sigma-delta modulator.

Further, in one embodiment of the present invention, the sigma-delta modulation circuit may be a mesh type sigma-delta modulation circuit including a plurality of primary sigma-delta modulation circuits.

Hereinafter, a sigma-delta modulator according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a sigma-delta modulator according to the present invention. Referring to FIG. 1, the sigma-delta modulator 30 according to the present invention includes a pseudo random bit sequence (PRBS) generation unit 32 for generating random bits in a predetermined sequence; A summer 33 for adding the random bits generated by the pseudo random bit sequence (PRBS) generator 32 with the input values of the sigma-delta modulator; And a modulation circuit 31 for sigma-delta modulating an input value obtained by adding the random bits by the summer 33.

The pseudo random bit sequence (PRBS) generator 32 generates random bit data in a predetermined sequence. The bit data generated by the pseudo random bit sequence (PRBS) generator 32 is input to the sigma-delta modulation circuit 31 in addition to an input value input to the sigma-delta modulator 30, and the sigma-delta In order to keep the average of the output values of the modulation circuit 31 the same regardless of the random bit value generated by the pseudo random bit sequence (PRBS) generation unit 32, the sum of the random bits is equal to zero. desirable.

In addition, when the sigma-delta modulator 30 according to the present invention is used in a fractional N phase locked loop (PLL), the sigma-delta modulator 30 divides according to the division ratio determined in the modulus divider. Clocked voltage controlled oscillator (VCO) frequency signal. Therefore, the sequence of random bits generated by the pseudo random bit sequence generator 32 is preferably the same as the operating clock frequency of the sigma-delta modulator 30.

The pseudo random bit sequence (PRBS) generator may be implemented in various forms. 4 shows an example of the pseudo random bit sequence generator. As illustrated in FIG. 4, the pseudo random bit sequence generator 40 may include a plurality of flip-flops 41 and at least one XOR gates 42a and 42b connected to each other. Each flip-flop 41 moves the stored data to the next flip-flop 41 whenever the clock CLK is applied. The flip-flop 41 may be implemented as a shift register connecting a plurality of flip-flops. An example of the pseudo random bit sequence generator shown in FIG. 4 has a structure in which the output of some of the flip-flops 41 is applied to the XOR gates 42a and 42b and the output value is fed back to the first flip-flop. . The number of flip-flops 41, the number of XOR gates 42a and 42b, and the number of feedbacks may be variously changed as necessary.

Referring back to FIG. 3, the summer 33 adds the random bits generated by the pseudo random bit sequence generator 32 to the input values of the sigma-delta modulator 30.

The sigma-delta modulation circuit 31 sigma-delta modulates an input value obtained by adding the random bits by the summer 33. The sigma-delta modulation circuit 31 may be a mesh type sigma-delta modulation circuit including a plurality of primary sigma-delta modulators, such as the conventional sigma-delta modulator shown in FIG.

In particular, when the sigma-delta modulator 30 according to the present invention is used in a fractional N phase locked loop (PLL), the sigma-delta modulator 30 divides according to the division ratio determined in the modulus divider. Clocked voltage controlled oscillator (VCO) frequency signal. In addition, when the sigma-delta modulator 30 according to the present invention is used in a fractional N phase locked loop (PLL), the input value may be a counting value of a programmable counter, and this counting value and the A value obtained by adding random bit data, which is an output value of the pseudo random bit sequence (PRBS) generator 32, is input to the sigma-delta modulation circuit 31 to be sigma-delta modulated.

The input value input to the sigma-delta modulation circuit 31 includes random bit data which is an output value of the pseudo random bit sequence generator 32. Therefore, the input value input to the sigma-delta modulation circuit 31 is a value that is randomly changed from the original input value, thereby removing periodic components from the output value output from the sigma-delta modulation circuit 31. can do. In particular, since the sum of the random bit data added to the original input value is 0, the total average of the output values of the sigma-delta modulation circuit 31 is not changed.

5a and 5b show the results of measuring the periodicity and noise characteristics of the sigma-delta modulator according to the present invention.

As shown in FIG. 5A, the sigma-delta modulator according to the present invention does not have the same data output at regular intervals when the output samples are observed. This can be better understood compared to the output sample results of the conventional sigma-delta modulator shown in FIG. 2A. Thus, according to the present invention, by removing the periodic components present in the output of the conventional sigma-delta modulator, it is possible to eliminate the generation of fractional spurs during the operation of the fractional N PLL in which the sigma delta modulator is used. have.

In addition, as shown in FIG. 5B, the sigma-delta modulator according to the present invention causes the noise of its output to be significantly reduced compared to the conventional sigma-delta modulator shown in FIG. 2B. In particular, it can be seen that the noise characteristics are greatly improved in the band below 300kHz. Thus, according to the present invention, it is possible to significantly improve the noise characteristics compared to the conventional sigma-delta modulator.

The present invention is not limited by the above-described embodiment and the accompanying drawings, but is intended to be limited by the appended claims, and various forms of substitution and modification within the scope not departing from the technical spirit of the present invention described in the claims. And it will be apparent to those skilled in the art that changes are possible.

As described above, according to the present invention, by adding a random sequence to the input data of the sigma-delta modulator, there is an effect of removing the periodic components appearing at the output of the sigma-delta modulator and reducing the noise level. In addition, through this, it is possible to reduce the fractional spurs of the fractional N PLL in which the sigma-delta modulator is used, thereby preventing deterioration of operating characteristics of the entire system.

Claims (4)

In a sigma-delta modulator that receives a predetermined input value and outputs a bit stream having a value between a (+) range and a (-) range, Each time the clock CLK is applied, a plurality of flip-flops connected to each other to move the stored data to the next flip-flop and an output of some of the flip-flops are input and fed back to the first flip-flop. A pseudo random bit sequence (PRBS) generation unit comprising at least one XOR gate to generate random bits in a predetermined sequence; A summer for adding random bits generated by the pseudo random bit sequence generator to an input value of the sigma-delta modulator; And And a sigma-delta modulator for sigma-delta modulating an input value summed with random bits by the summer. The method of claim 1, Sigma-delta modulator, characterized in that the sum of the bits generated by the pseudo random bit sequence generator is zero. The method of claim 1, The sequence of the pseudo random bit sequence generator is the same as the operating clock frequency of the sigma-delta modulator. The method of claim 1, The modulation circuit is a sigma-delta modulator, characterized in that the mesh type sigma-delta modulation circuit comprising a plurality of primary sigma-delta modulation circuit.

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