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KR100702118B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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KR100702118B1
KR100702118B1 KR1020010037627A KR20010037627A KR100702118B1 KR 100702118 B1 KR100702118 B1 KR 100702118B1 KR 1020010037627 A KR1020010037627 A KR 1020010037627A KR 20010037627 A KR20010037627 A KR 20010037627A KR 100702118 B1 KR100702118 B1 KR 100702118B1
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film
semiconductor substrate
gate electrode
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KR20030001820A (en
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이병학
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 소자의 전기적 특성을 향상시키는데 적당한 반도체 소자의 제조방법에 관한 것으로, 반도체 기판 상에 폴리실리콘막, 텅스텐막을 포함하는 게이트 전극을 형성하는 단계; 상기 반도체 기판의 전면에 실리콘 질화막(SiNx)을 증착하는 단계; 패터닝된 폴리실리콘막의 좌우 측면 및 반도체 기판의 표면을 선택적으로 산화하는 단계; 상기 게이트 전극의 적층 구조 양측면에 측벽 절연막을 형성하는 단계; 상기 반도체 기판 표면내에 소오스/드레인을 형성하는 단계를 포함하여 형성함을 특징으로 한다.The present invention relates to a method for manufacturing a semiconductor device suitable for improving the electrical characteristics of the device, comprising the steps of: forming a gate electrode comprising a polysilicon film and a tungsten film on a semiconductor substrate; Depositing a silicon nitride film (SiNx) on the entire surface of the semiconductor substrate; Selectively oxidizing the left and right sides of the patterned polysilicon film and the surface of the semiconductor substrate; Forming sidewall insulating films on both sides of the stacked structure of the gate electrode; And forming a source / drain in the surface of the semiconductor substrate.

선택 산화막, 텅스텐 산화물질Oxide, tungsten oxide optional

Description

반도체 소자의 제조방법{METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

도 1a 내지 도 1c는 종래 반도체 소자의 제조방법을 나타낸 공정 단면도1A to 1C are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.

도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정 단면도2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 제 1 절연막21 semiconductor substrate 22 first insulating film

23 : 폴리실리콘막 23a : 선택 산화막23: polysilicon film 23a: selective oxide film

24 : 베리어막 25 : 텅스텐막 24: barrier film 25: tungsten film

26 : 제 2 절연막 27 : 실리콘 질화막26: second insulating film 27: silicon nitride film

28 : 측벽 절연막28: sidewall insulating film

본 발명은 반도체 소자에 관한 것으로, 소자의 전기적 특성을 향상시키는데 적당한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for improving electrical characteristics of the device.

이하에서 첨부된 도면을 참조하여 종래 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.

도 1a 내지 도 1c는 종래 반도체 소자의 제조방법을 나타낸 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.

도 1a에 나타낸 바와 같이, 액티브 영역 및 필드 영역이 정의된 반도체 기판(1)상에 게이트 절연막(2), 게이트 전극 형성을 위한 불순물이 도핑된 폴리실리콘막(3), 그리고 베리어막(4), 텅스텐막(5), 제 1 절연막(도시하지 않음), 제 2 절연막(6)을 차례로 증착한다.As shown in FIG. 1A, a gate insulating film 2, a polysilicon film 3 doped with impurities for forming a gate electrode, and a barrier film 4 are formed on a semiconductor substrate 1 having active and field regions defined therein. , A tungsten film 5, a first insulating film (not shown), and a second insulating film 6 are sequentially deposited.

이때, 상기 제 1 절연막은 질화물질을 이용하고, 제 2 절연막(6)은 산화물질을 이용하여 형성한다.In this case, the first insulating film is formed of a nitride material, and the second insulating film 6 is formed of an oxide material.

이어, 도 1b에 나타낸 바와 같이, 상기 제 2 절연막(6)의 상에 감광막(도시하지 않음)을 도포하고 노광 및 현상공정으로 패터닝하여 게이트 전극 영역을 정의한 후, 상기 패터닝된 감광막을 마스크로 이용하여 상기 제 2 절연막(6)을 선택적으로 제거한다. Subsequently, as shown in FIG. 1B, a photoresist film (not shown) is coated on the second insulating film 6 and patterned by exposure and development processes to define a gate electrode region, and then the patterned photoresist film is used as a mask. To selectively remove the second insulating film 6.

그리고, 제 1 절연막, 텅스텐막(5), 베리어막(4), 폴리실리콘막(3)을 선택적으로 제거하여 적층 구조로 이루어진 게이트 전극을 형성한다.The first insulating film, the tungsten film 5, the barrier film 4, and the polysilicon film 3 are selectively removed to form a gate electrode having a laminated structure.

이후, H2O/H2 분위기에서 열처리하여 실리콘만을 선택적으로 산화시키는 공정을 통해 패터닝된 상기 폴리실리콘막(3)의 좌우 측면 및 반도체 기판(1)의 표면에 선택 산화막(3a)을 형성한다.Thereafter, a selective oxide film 3a is formed on the left and right side surfaces of the polysilicon film 3 and the surface of the semiconductor substrate 1 through a process of selectively oxidizing silicon by heat treatment in an H 2 O / H 2 atmosphere. .

이어, 상기 제 2 절연막(6)을 마스크로 이용하여 상기 반도체 기판(1) 표면 내에 저농도 불순물을 이온주입한다.Subsequently, a low concentration of impurities are implanted into the surface of the semiconductor substrate 1 using the second insulating film 6 as a mask.

이후, 600∼900℃의 온도에서 N2, Ar 기체 등의 불활성 분위기나 O2, H2, NH3 등을 포함하는 활성분위기에서 열처리하여 주입된 이온의 활성화 및 확산을 일으킴으로써 LDD(Lightly Doped Drain)(도시하지 않음) 영역을 형성한다.Then, LDD (Lightly Doped) is caused by activation and diffusion of implanted ions by heat treatment in an inert atmosphere such as N 2 , Ar gas or O 2 , H 2 , NH 3 at a temperature of 600 to 900 ° C. Drain (not shown) areas are formed.

도 1c에 도시된 바와 같이, 상기 반도체 기판(1)의 전면에 산화막(도시 생략)을 형성한 후, 동일한 두께로 식각(etch)하여 상기 게이트 전극 적층 구조의 양측면에 측벽 절연막(8)을 형성한다.As shown in FIG. 1C, an oxide film (not shown) is formed on the entire surface of the semiconductor substrate 1 and then etched to the same thickness to form sidewall insulating films 8 on both sides of the gate electrode stack structure. do.

그리고, 상기 제 2 절연막(6) 및 측벽 절연막(8)을 마스크로 이용하여 상기 반도체 기판(1)내에 고농도로 이온주입(N+)을 실시하여 상기 측벽 절연막 하측의 상기 반도체 기판(1) 표면내에 LDD 영역을 갖는 소오스/드레인 영역(도시하지 않음)을 형성한다.Then, using the second insulating film 6 and the sidewall insulating film 8 as a mask, ion implantation (N +) is carried out in the semiconductor substrate 1 at a high concentration so as to be in the surface of the semiconductor substrate 1 under the sidewall insulating film. A source / drain region (not shown) having an LDD region is formed.

이후, 고농도로 주입된 불순물 이온의 활성화 및 확산을 위하여 600∼900℃의 온도에서 N2, Ar 기체 등의 불활성 분위기나 O2 등을 포함하는 산화성 분위기에서의 열처리를 실시한다.Thereafter, in order to activate and diffuse the impurity ions implanted at a high concentration, heat treatment is performed at an inert atmosphere such as N 2 , Ar gas, or an oxidizing atmosphere including O 2 at a temperature of 600 to 900 ° C.

그러나, 상기와 같은 종래의 반도체 소자의 제조방법은 다음과 같은 문제점이 있다.However, the conventional method of manufacturing a semiconductor device as described above has the following problems.

게이트 전극을 패터닝한 후 텅스텐막의 산화를 억제하며 폴리실리콘막의 측면을 선택적으로 산화하는 공정에서 산소분위기에서 급격한 텅스텐막의 산화로 인 한 부피 팽창으로 게이트 전극의 측면에 필링(Peeling)이 발생하고, 휘발성의 텅스텐 산화물에 의해 반도체 기판의 표면이 오염되는 문제가 발생하여 이로 인하여 소자 특성이 열화된다.In the process of inhibiting the oxidation of the tungsten film after the gate electrode is patterned and selectively oxidizing the side of the polysilicon film, peeling occurs on the side of the gate electrode due to the volume expansion caused by the rapid oxidation of the tungsten film in an oxygen atmosphere. The surface of the semiconductor substrate is contaminated by tungsten oxide, which causes deterioration of device characteristics.

또한, 선택 산화공정에서 게이트 전극의 측면부의 텅스텐막과 폴리실리콘막 사이의 계면에 산소가 확산해 들어가게 되므로 소자의 디자인 룰(Design rule)이 감소하게 된다.In addition, in the selective oxidation process, oxygen diffuses into the interface between the tungsten film and the polysilicon film on the side of the gate electrode, thereby reducing the design rule of the device.

따라서, 텅스텐막과 폴리실리콘막 사이의 계면 저항이 증가하여 소자의 전기적 특성을 악화시킨다.Therefore, the interface resistance between the tungsten film and the polysilicon film is increased, thereby deteriorating the electrical characteristics of the device.

본 발명은 상기의 문제점을 해결하기 위한 것으로, 실리콘 질화막을 이용하여 선택 산화공정을 진행함으로써 텅스텐의 산화를 방지하는데 적당한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method for manufacturing a semiconductor device suitable for preventing oxidation of tungsten by performing a selective oxidation process using a silicon nitride film.

이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은 반도체 기판 상에 폴리실리콘막, 텅스텐막을 포함하는 게이트 전극을 형성하는 단계; 상기 반도체 기판의 전면에 실리콘 질화막(SiNx)을 증착하는 단계; 패터닝된 폴리실리콘막의 좌우 측면 및 반도체 기판의 표면을 선택적으로 산화하는 단계; 상기 게이트 전극의 적층 구조 양측면에 측벽 절연막을 형성하는 단계; 상기 반도체 기판 표면내에 소오스/드레인을 형성하는 단계를 포함하여 형성함을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a gate electrode including a polysilicon film, a tungsten film on a semiconductor substrate; Depositing a silicon nitride film (SiNx) on the entire surface of the semiconductor substrate; Selectively oxidizing the left and right sides of the patterned polysilicon film and the surface of the semiconductor substrate; Forming sidewall insulating films on both sides of the stacked structure of the gate electrode; And forming a source / drain in the surface of the semiconductor substrate.

이하 , 첨부도면을 참조하여 본 발명에 따른 반도체 소자의 제조방법을 설명 하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

도 2a에 나타낸 바와 같이, 액티브 영역 및 필드 영역이 정의된 반도체 기판(21)상에 제 1 절연막(22), 불순물이 도핑된 폴리실리콘막(23), 그리고 베리어막(24), 텅스텐막(25), 제 2 절연막(26)을 차례로 증착한다.As shown in FIG. 2A, the first insulating film 22, the polysilicon film 23 doped with impurities, the barrier film 24, and the tungsten film (on the semiconductor substrate 21 having the active region and the field region defined therein) 25), the second insulating film 26 is deposited sequentially.

여기서, 상기 베리어막(24)은 텅스텐(W), 몰리브덴(Mo), 탄탈륨(Ta) 중에 어느 하나와 혼합된 비정질의 질화물질를 이용하며 30∼200Å의 두께로 증착하여 형성한다.Here, the barrier layer 24 is formed by depositing an amorphous nitride material mixed with any one of tungsten (W), molybdenum (Mo), and tantalum (Ta) and having a thickness of 30 to 200 kPa.

이어, 상기 제 2 절연막(26)의 상에 감광막(도시하지 않음)을 도포하고 노광 및 현상공정으로 패터닝하여 게이트 전극 영역이 정의된 감광막 패턴(도시하지 않음)을 형성한다.Subsequently, a photoresist (not shown) is coated on the second insulating layer 26 and patterned by an exposure and development process to form a photoresist pattern (not shown) in which a gate electrode region is defined.

도 2b에 나타낸 바와 같이, 상기 감광막 패턴을 마스크로 이용하여 상기 제 2 절연막(26)을 선택적으로 제거하고, 이어, 상기 텅스텐막(25), 베리어막(24), 폴리실리콘막(23)을 선택적으로 제거하여 적층 구조로 이루어진 게이트 전극을 형성한다.As shown in FIG. 2B, the second insulating film 26 is selectively removed using the photosensitive film pattern as a mask, and then the tungsten film 25, the barrier film 24, and the polysilicon film 23 are removed. It is selectively removed to form a gate electrode having a laminated structure.

이후, 상기 게이트 전극을 포함하는 반도체 기판(21)의 전면에 50Å 이하의 두께로 실리콘 질화막(SiNx)(27)을 증착한다.Thereafter, a silicon nitride layer (SiNx) 27 is deposited on the entire surface of the semiconductor substrate 21 including the gate electrode at a thickness of 50 μm or less.

이때, 상기 실리콘 질화막(27)은 x＜1.3 (Si-rich silicon nitride)인 조성비를 갖는다. In this case, the silicon nitride film 27 has a composition ratio of x <1.3 (Si-rich silicon nitride).                     

또한, 상기 실리콘 질화막(27) 대신 Si/Si3N4의 스택(Stack) 구조를 사용할 수 있는데, 이 경우 Si3N4막을 얇게 증착하여 텅스텐막(25)의 후속의 선택 산화공정에서 휘스커(Whisker) 발생을 억제시킨 후, 실리콘(Si)막을 증착한다.In addition, a stack structure of Si / Si 3 N 4 may be used instead of the silicon nitride film 27, in which case the Si 3 N 4 film is thinly deposited so that the whisker may be used in the subsequent selective oxidation of the tungsten film 25. After suppressing whisker generation, a silicon (Si) film is deposited.

이어, H2O/H2 분위기에서 열처리하여 실리콘만을 산화시키는 선택 산화공정을 이용하여 패터닝된 상기 폴리실리콘막(23)의 좌우 측면 및 반도체 기판(21)의 표면에 선택 산화막(23a)을 형성한다.Subsequently, a selective oxide film 23a is formed on the left and right side surfaces of the polysilicon film 23 and the surface of the semiconductor substrate 21 by using a selective oxidation process of oxidizing only silicon by heat treatment in an H 2 O / H 2 atmosphere. do.

이때, 상기 선택 산화공정은 0.01≤H2O/H2 ≤0.5, 700∼1100℃ 범의의 온도, 30초∼2시간의 조건에서 진행한다.At this time, the selective oxidation process is carried out under the conditions of 0.01 ≦ H 2 O / H 2 ≦ 0.5, a temperature of 700 to 1100 ° C., and 30 seconds to 2 hours.

또한, 상기 선택 산화공정은 실리콘 질화막(27)의 산화를 수반하며, 텅스텐막(25)의 오염은 0.1 ng/wafer 이하로 감소한다.Further, the selective oxidation process involves oxidation of the silicon nitride film 27, and the contamination of the tungsten film 25 is reduced to 0.1 ng / wafer or less.

도 2c에 나타낸 바와 같이, 반도체 기판(21)의 전면에 제 3 절연막(도시하지 않음)을 증착하고, 상기 반도체 기판(1) 표면내에 저농도 불순물을 이온주입한다.As shown in Fig. 2C, a third insulating film (not shown) is deposited on the entire surface of the semiconductor substrate 21, and low concentration impurities are implanted into the semiconductor substrate 1 surface.

이후, 열처리를 통해 주입된 이온의 활성화 및 확산을 일으킴으로써 LDD(Lightly Doped Drain)(도시하지 않음) 영역을 형성한다.Subsequently, an LDD (Lightly Doped Drain) (not shown) region is formed by activating and diffusing ions implanted through the heat treatment.

그리고, 상기 반도체 기판(21)의 전면에 절연물질을 증착한 후, 동일한 두께로 식각(etch)하여 상기 게이트 전극의 적층 구조의 양측면에 스페이서 형태의 측벽 절연막(28)을 형성한다.After the insulating material is deposited on the entire surface of the semiconductor substrate 21, the insulating material is etched to the same thickness to form sidewall insulating films 28 having a spacer shape on both sides of the stack structure of the gate electrodes.

그리고, 상기 제 2 절연막(26) 및 측벽 절연막(28)을 마스크로 이용하여 상기 반도체 기판(21)내에 고농도로 이온주입을 실시하여 상기 측벽 절연막(28) 하측 의 상기 반도체 기판(21) 표면내에 LDD 영역을 갖는 소오스/드레인 영역(도시하지 않음)을 형성한다.Then, the second insulating film 26 and the sidewall insulating film 28 are used as a mask, and ion implantation is performed in the semiconductor substrate 21 at a high concentration so as to be in the surface of the semiconductor substrate 21 below the sidewall insulating film 28. A source / drain region (not shown) having an LDD region is formed.

이후, 고농도로 주입된 불순물 이온의 활성화 및 확산을 위하여 산화성 분위기에서의 열처리를 실시한다.Thereafter, heat treatment is performed in an oxidizing atmosphere to activate and diffuse the impurity ions implanted at a high concentration.

이어, 도면에는 도시하지 않았지만, 상기 반도체 기판(21) 전면에 플러그 형성을 위한 폴리실리콘막을 증착하고, 화학적 기계적 연마법(Chemical Machanical Polishing : CMP)을 이용하여 상기 제 2 절연막(26)의 표면까지 평탄화하여 플러그를 형성한다.Subsequently, although not shown in the drawing, a polysilicon film for forming a plug is deposited on the entire surface of the semiconductor substrate 21, and then, to the surface of the second insulating film 26 using chemical mechanical polishing (CMP). Plane to form a plug.

상기와 같은 본 발명의 반도체 소자의 제조방법은 다음과 같은 효과가 있다.The method of manufacturing a semiconductor device of the present invention as described above has the following effects.

첫째, 실리콘 질화막을 증착한 후 선택 산화공정을 진행함으로써 텅스텐과 H2O의 반응에 기인하는 텅스텐 산화물(WOx)의 형성을 최소화할 수 있다.First, by depositing a silicon nitride film and then performing a selective oxidation process it is possible to minimize the formation of tungsten oxide (WOx) due to the reaction of tungsten and H 2 O.

이는 게이트 전극의 저항 증가 및 반도체 기판의 텅스텐 산화물에 의한 오염을 감소시킬 수 있다.This can reduce the resistance of the gate electrode and reduce the contamination by tungsten oxide of the semiconductor substrate.

둘째, 측벽 절연막 형성 후 폴리실리콘 플러그를 형성하는 공정에서 실리콘의 휘스커(Whisker) 형성을 방지할 수 있다.Second, whisker formation of silicon may be prevented in the process of forming the polysilicon plug after the sidewall insulating layer is formed.

셋째, 텅스텐막과 폴리실리콘막 사이의 계면에 산소(O) 침투로 인한 계면 저항의 억제할 수 있다.Third, the interface resistance due to oxygen (O) infiltration at the interface between the tungsten film and the polysilicon film can be suppressed.

Claims (4)

반도체 기판 상에 폴리실리콘막, 텅스텐막을 포함하는 게이트 전극을 형성하는 단계; Forming a gate electrode including a polysilicon film and a tungsten film on the semiconductor substrate; 상기 반도체 기판의 전면에 실리콘 질화막(SiNx)을 증착하는 단계; Depositing a silicon nitride film (SiNx) on the entire surface of the semiconductor substrate; 패터닝된 폴리실리콘막의 좌우 측면 및 반도체 기판의 표면을 선택적으로 산화하는 단계; Selectively oxidizing the left and right sides of the patterned polysilicon film and the surface of the semiconductor substrate; 상기 게이트 전극의 적층 구조 양측면에 측벽 절연막을 형성하는 단계; Forming sidewall insulating films on both sides of the stacked structure of the gate electrode; 상기 반도체 기판 표면내에 소오스/드레인을 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 제조방법.And forming a source / drain on the surface of the semiconductor substrate. 삭제delete 제 1 항에 있어서, 패터닝된 폴리실리콘막의 좌우 측면 및 반도체 기판의 표면을 선택적으로 산화하는 단계는 0.01≤H2O/H2 ≤0.5, 700∼1100℃의 온도, 30초∼2시간의 조건으로 열처리하여 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1 wherein patterning the polysilicon film left and right side surfaces and the step of selectively oxidizing the surface of the semiconductor substrate is 0.01≤H 2 O / H 2 ≤0.5, the temperature of 700~1100 ℃, 30 cho conditions for 2 hours Method for manufacturing a semiconductor device, characterized in that the heat treatment by. 제 1 항에 있어서, 상기 실리콘 질화막 전면에 실리콘(Si)막을 증착하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, further comprising depositing a silicon (Si) film on the entire silicon nitride film.
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