KR100710357B1 - Apparatus and method for processing main and enhanced multiplexed packets - Google Patents

Abstract

The present invention relates to a main and enhanced multiplex packet processing apparatus and method in an E8-VSB system for generating a plurality of enhanced data by encoding at different code rates, and multiplexing the same with main data. In particular, the present invention provides an input / output ratio of a buffer and a byte extension unit for an enhanced packet which is an input of a main / enhanced packet multiplexer by driving an enhanced data interleaver and a byte extension unit in the main and enhanced multiplex packet processing apparatus. It is possible to remove the buffer to solve the difference. This simplifies the implementation of the main and enhanced multiplex packet processing apparatus in the E8-VSB transmitter / receiver. In addition, even if the enhanced mode map information changes over time, the corresponding E8-VSB transmitter / receiver may be easily implemented.

E8-VSB, Enhanced Data Interleaver, Byte Expansion

Description

Main and enhanced MUX packet processor and its method

1 is a block diagram showing an embodiment of an E8-VSB transmitter according to the present invention;

FIG. 2 is a block diagram illustrating an embodiment of the E8-VSB processor of FIG. 1; FIG.

3 is a block diagram illustrating an embodiment of a main and enhanced multiplex packet processing unit of FIG. 2;

4 is a block diagram showing an embodiment of a main and enhanced multiplex packet processing unit according to the present invention;

5 is a timing diagram illustrating an example of an input / output signal of the enhanced packet controller of FIG. 4.

6 illustrates an example of an operation of the enhanced data interleaver of FIG. 4.

Explanation of symbols for main parts of the drawings

401-403: Buffer 404: Enhanced Packet Multiplexer

405: enhanced RS encoder 406: enhanced data interleaver

407: byte expansion unit 408: MPEG header inserter

409: M / E packet multiplexer 410: enhanced packet controller

411: enhanced interleaver control unit

The present invention relates to an E8-VSB system for transmitting / receiving a plurality of enhanced data encoded at different code rates. In particular, the present invention relates to generating a plurality of enhanced data by encoding at different code rates and to main data. The present invention relates to a main and enhanced multiplexing packet processing apparatus and a method for multiplexing and outputting the multiplexed output.

In the United States, the ATSC (Advanced Television Systems Committee) 8VSB (Vestigial Sideband) transmission method was adopted as a standard in 1995, and broadcasted since the second half of 1998.In Korea, the same ATSC 8VSB transmission method is used as the standard. Adopted and currently broadcasting.

The ATSC 8VSB transmission method is basically a standard for high-definition video. However, there is a demand for a system capable of data communication that requires a more stable reception than a video signal due to the characteristics of the system or the content which is accompanied by the deterioration of image quality. In addition, these additional transmission specifications do not adversely affect the system receiving the existing ATSC 8VSB signals, and the existing ATSC 8VSB signals and the new enhanced 8-VSB signals (E8-VSB) when passing through the receiver of the new specification. It defines the E8-VSB specification, a system that can receive all.

Therefore, the E8-VSB system accepts the existing 8VSB system as it is and adds a new service so that the newly added service can receive better reception than the existing service, and the existing service is also affected by the added service, resulting in more stable reception performance. It is a system that looks.

It is an object of the present invention to provide an apparatus and method for main and enhanced multiplex packet processing in an E8-VSB system which minimizes the use of a buffer.

In order to achieve the above object, the main and enhanced multiplexing packet processing apparatus of the E8-VSB system according to the present invention operates in synchronization with the EIE signal, and interleaved and outputs the enhanced data input in bytes. Interleaver; Byte extension and MPEG header which expands the interleaved enhanced data to two or four bytes according to the output data attribute of the enhanced data interleaver and outputs an enhanced MPEG packet in which an MPEG header is inserted according to an HBE / EBE signal. Insert; The multiplexing order of the main MPEG packet and the enhanced packet is determined according to the enhanced mode map information input, and the main MPEG packet is input by generating and outputting an MPE signal in the case of the current main packet, and generating an EPE signal in the enhanced packet. An M / E packet multiplexer for receiving an enhanced MPEG packet and outputting the same by outputting the received MPEG packet; An enhanced packet controller configured to generate an EBE signal and an HBE signal when the EPE signal is input from the M / E packet multiplexer, and output the byte extension and the MPEG header inserter; And an enhanced interleaver controller configured to generate an EIE signal according to an output data attribute of the enhanced data interleaver and output the EIE signal to the enhanced data interleaver when an EBE signal is input from the enhanced packet controller.

The main and enhanced multiplex packet processing apparatus of the E8-VSB system according to the present invention stores a main MPEG packet which is input, and outputs the stored main MPEG packet to the M / E packet multiplexer when the MPE signal is input. And a second buffer for storing the first enhanced data input in units of 188 bytes, and outputting the first enhanced data in units of 164 bytes when the HPE signal is input, and the second enhanced data input in units of 188 bytes. A second buffer configured to output second enhanced data in units of 164 bytes when the QPE signal is input, and operate in synchronization with the EIE signal, and according to the enhanced mode map information. Determine the multiplexing order of the data, and if the current data is the first enhanced data, generate an HPE signal to the second buffer to receive the first enhanced data, and the second enhanced data. If the data for is characterized in that the third buffer further comprising: an input multiplexer for receiving enhanced packet and outputs a second enhancement deuyong data and outputs the signal to the QPE.

If the enhanced interleaver controller receives an EBE signal from the enhanced packet controller and the output data (EIO) attribute of the enhanced data interleaver is a first enhanced byte, the enhanced interleaver controller operates on the next byte clock. In case of the second enhanced byte, the EIE signal is generated to control the three-byte clock to operate on the next byte clock.

When the EPE signal is input from the M / E packet multiplexer, the enhanced packet controller divides the position of the MPEG header and the enhanced data byte with respect to the enhanced packet and generates an HBE signal and an EBE signal corresponding to the position. The byte extension and the MPEG header inserter output the byte extension and the MPEG header inserter, and output the MPEG NULL header data in the HBE signal section and the extended enhanced data in the EBE section.

The main and enhanced multiplex packet processing method of an E8-VSB transmitter / receiver including an enhanced data interleaver according to the present invention,

And controlling to transition to any one of an initial state, an intermediate state 1, an enhanced data interleaver output receiving state, and an intermediate state 2 by operating every byte clock in the enhanced packet interval.

In the initial state generates a signal for operating the enhanced data interleaver and transitions to intermediate state 1,

In the intermediate state 1, the operation of the enhanced data interleaver stops at the next byte clock, and transitions to the enhanced data interleaver output receiving state.

In the interleaver output receiving state, if the attribute of the output data of the enhanced data interleaver at the next byte clock is the first enhanced, the enhanced data interleaver is operated again and transitions to the intermediate state 1, and if the second is enhanced, the enhanced data interleaver continues. Transitions to Intermediate state 2, leaving the behavior of

In the intermediate state 2, the transition to the initial state is performed while leaving the operation of the enhanced data interleaver stopped at the next byte clock.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described. At this time, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, by which the technical spirit of the present invention and its core configuration and operation is not limited.

The overall structure of the E8-VSB system conforming to the E8-VSB standard has been proposed by the applicant, and FIG. 1 shows a block diagram of a transmitter of the E8-VSB system.

That is, the E8-VSB transmitter can transmit the recently used MPEG-4 video or various additional data (eg program execution file, stock information, etc.) through the enhanced data, and also the existing MPEG-2 video and Dolby sound. You can also send data.

Hereinafter, for convenience of description, an existing MPEG-2 image is defined as main data or normal data. In this case, the enhanced data is subjected to additional error correction encoding compared to the main data. The enhanced data and the 1/2 enhanced data of the enhanced data mean data in which encoding is further performed at 1/2 code rate and 1/4 code rate, respectively, compared to the main data. Therefore, the enhanced data has a much better reception performance than the main data due to noise and multipath interference occurring in the channel. In particular, the 1/4 enhanced data coded at 1/4 code rate is 1/2. It has better performance than 1/2 enhanced data encoded at a code rate.

Referring to FIG. 1, the E8-VSB transmitter is schematically described as follows. That is, the quoted MPEG stream is output to the E8-VSB processor 114 as a main MPEG packet in units of 188 bytes through the first buffer 111. The 1/2 enhanced MPEG stream is output to the E8-VSB processing unit 114 as a 1/2 enhanced MPEG packet in units of 188 bytes through the second buffer 112. The 1/4 enhanced MPEG stream is output to the E8-VSB processor 114 as a 1/4 enhanced MPEG packet in units of 188 bytes through the third buffer 113.

The E8-VSB processor 114 further performs 1/2 encoding on the 1/2 enhanced MPEG packet in units of 188 bytes, and adds 1/4 to the 1/4 enhanced MPEG packet in units of 188 bytes. Perform the encoding. Then, according to the enhanced mode map, the 1/2 and 1/4 enhanced data are multiplexed in MPEG packet units to generate an enhanced MPEG packet, and the enhanced MPEG packets are multiplexed again in main data and segment units and are ATSC. After compatibility preprocessing, enhanced symbol processing, and ATSC compatibility postprocessing, the signal is output to the 8VSB channel coding unit 115. The 8VSB channel coding unit 115 generates an E8-VSB symbol by error correction coding the multiplexed MPEG packet and outputs the E8-VSB symbol to the 8VSB modulator 116. The 8VSB modulator 116 modulates the E8-VSB symbol by the ATSC 8VSB scheme and transmits the same.

FIG. 2 is a detailed block diagram of the E8-VSB processing unit 114 of FIG. 1, in which the main and enhanced multiplex packet processing unit 210 receives 1/2 enhanced data and 1/4 enhanced data, and performs E8-VSB preprocessing. (Pre-processor) is performed to output to the M / E packet multiplexer (212). The M / E packet multiplexer 212 multiplexes the enhanced data and the main data, which have undergone the E8-VSB preprocessing, into 188 bytes of MPEG packet units (also called segment units) according to the enhanced mode map information.

The MPEG packet multiplexed by the M / E packet multiplexer 212 undergoes a symbol-based encoding process through the enhanced symbol processing unit 230. Before and after symbol encoding to maintain compatibility with the existing 8VSB system, There is a need for an ATSC compatible preprocessor 220 and an ATSC compatible postprocessor 240 to perform the operation. In FIG. 2, the ATSC compatible preprocessor 220 includes a data renderer, an RS encoder, a data interleaver, and a 12-way symbol interleaver of the ATSC 8VSB, and the ATSC compatible preprocessor 230 is a 12-way symbol deinterleaver of the ATSC 8VSB. Data deinterleaver, RS byte remover, and derandomizer.

That is, in order to transmit the E8-VSB signal from the E8-VSB transmitter, the main and enhanced multiplex packet processing unit 210 performs byte unit encoding and generates byte attribute information according to the ATSC compatibility. Pre- and post-processing units 220 and 240 and the enhanced symbol processing unit 230 perform symbol unit encoding. Then, the ATSC 8VSB channel coding unit 115 generates an E8-VSB symbol and uses the 8VSB modulator 116 to transmit the E8-VSB signal.

3 is a detailed block diagram of the E8-VSB preprocessor 211. The main data output from the first buffer 111 is input to the M / E packet multiplexer 212, and the second, The 1/2 enhanced data and the 1/4 enhanced data output from the third buffers 112 and 113 are input to the first and second MPEG packet converters 301 and 302 of the E8-VSB preprocessor 211, respectively.

The first MPEG packet converter 301 of the E8-VSB preprocessor 211 receives 1/2 enhanced data output from the second buffer 112 in packets of 188 byte units and converts the data into 164 byte units without changing the data. The divided packets are output to the enhanced packet multiplexer 303. The second MPEG packet converter 302 receives 1/4 enhanced data output from the third buffer 113 in packets of 188 byte units, divides the data into 164 byte units without changing the enhanced packet multiplexer 303. Will output

The enhanced packet multiplexer 303 is configured to 164 the 1/2 enhanced data and the 1/4 enhanced data, which are output from the first and second MPEG packet converters 301 and 302, according to the enhanced mode map. The packet is multiplexed into a byte unit and output to the enhanced Reed-Solomon (RS) encoder 304.

The enhanced mode map information indicates whether a packet currently multiplexed in the enhanced packet multiplexer 303 is a packet transmitted in a 1/2 enhanced mode or a packet transmitted in a 1/4 enhanced mode.

The enhanced RS encoder 304 converts the enhanced data of 164 bytes into a packet of 184 bytes by adding a 20-byte parity code to the enhanced data multiplexed by the enhanced packet multiplexer 303. And output to the enhanced data interleaver 305. The enhanced data interleaver 305 performs convolutional interleaving on a byte basis for the enhanced data input from the enhanced RS encoder 304 to increase the performance against burst noise, and the buffer 306. After temporarily storing the data in the byte expander (Byte Expander) (307).

The byte expander 307 expands the packet by inserting null bits corresponding to 1/2 enhanced data or 1/4 enhanced data output from the buffer 306 according to the H / Q byte flag. That is, the byte expansion unit 307 expands to 2 bytes by inserting a null bit between each bit when the 1 / 2-enhanced data of 1 byte is input, and when the 1 / 4-enhanced data of 1 byte is input, each bit Repeat twice and insert a null bit between each bit to expand it to 4 bytes.

At this time, if one-byte 1/2 enhanced data passes through the byte extension unit 307, it becomes two bytes, and if one-quarter enhanced data passes through the byte extension unit 307, it becomes four bytes. In the enhanced symbol processor 230, additional 1/2 encoding and 1/4 encoding on the enhanced data are actually performed using the null bit inserted by the byte extension 307.

The data expanded by the byte expander 307 is output to an MPEG header adder 308.

The MPEG header inserter 308 inserts a 4-byte null MPEG header in front of every 184 byte units of the enhanced data in which the null bit is inserted in the byte extension unit 307 to create an MPEG-compatible packet of 188 byte units. The buffer 309 is then output to the M / E (Main / Enhanced) packet multiplexer 212. That is, a 188-byte enhanced MPEG packet consisting of 4 bytes of main byte and 184 bytes of enhanced byte.

The M / E packet multiplexer 212 uses a main MPEG packet of 188 bytes and an enhanced MPEG packet of 188 bytes (also referred to as a segment) output from the buffer 309 according to M / E packet attribute information. Multiplexing is performed and output to the ATSC compatible preprocessor 220.

Herein, the enhanced packet attribute information, the M / E packet attribute information, and the H / Q byte flag use enhanced mode map information (or E8-VSB map information) in an E8-VSB data attribute generator (not shown). E8-VSB data attribute information generated by

In FIG. 3, the dotted line indicates the flow of the buffer control signal and the solid line indicates the flow of the data signal. That is, the M / E packet multiplexer 212 multiplexes the main packet and the enhanced packet in the order determined in the enhanced mode map in synchronization with the field synchronization signal. In this case, the multiplexing order may determine whether the main packet is taken from the buffer 111 or the enhanced packet is taken from the buffer 309.

In this case, although the final output from the main and enhanced multiplex packet processing unit 210 is determined to be a packet of 188 byte units, 1/2 enhanced data packet and 1 unit of 164 bytes converted by the E8-VSB preprocessor 211 and 1 are used. The / 4 enhanced data packet does not extend to two packets and four packets at the input of the M / E packet multiplexer 212, respectively. The reason for this is as follows.

That is, the enhanced data interleaver 305 mixes the 1/2 enhanced packet data and the 1/4 enhanced packet data with each other in units of bytes, and the bytes of the 1/2 enhanced packet and the 1/4 enhanced packet are mixed with each other. This is because the bytes of the packet are expanded at different rates in the byte extension unit 307. In other words, the amount of expansion in the byte expansion unit 307 is different depending on the attribute of 1/2 or 1/4 every input byte, and the input of the byte expansion unit 307 is an enhanced data interleaver ( 305). However, since the attributes of the input byte and the output byte of the enhanced data interleaver 305 do not coincide with each other, the enhanced data interleaver 305 and the byte expander 307 are difficult to synchronize, which causes different speeds. There is a problem of exchanging data with a clock or using an additional buffer 306.

Accordingly, the present invention provides the input / output of the buffer 309 and the byte extension unit for the enhanced packet which is the input of the M / E packet multiplexer by driving the enhanced data interleaver and the byte extension unit in the main and enhanced multiplex packet processing unit. Remove buffer 306 to address the difference in rate. This makes it simple and efficient to implement the main and enhanced multiplex packet processing units.

The main and enhanced multiplex packet processing units are used in both the E8-VSB transmitter and the E8-VSB receiver. In this case, the E8-VSB transmitter should process data and its attribute information together, and the E8-VSB receiver is used to obtain the attributes of each byte and symbol of the E8-VSB.

Here, the byte attribute represents information on whether the current byte is a general 8VSB byte or an enhanced byte, and if it is an enhanced byte, it is a 1/2 enhanced byte or a 1/4 enhanced byte. In addition, the symbol attribute is determined by the ATSC randomizer if the current symbol is a regular 8VSB symbol or an enhanced symbol, a 1/2 enhanced symbol or a 1/4 enhanced symbol, or a 1/4 enhanced symbol. Information on whether the symbols have the same polarity, and information on whether the polarity of the following enhanced symbol can be changed if the general VSB symbol.

4 is a detailed block diagram of a main and enhanced multiplex packet processing unit according to the present invention. The basic operation of each unit is the same as that of FIG. 3, but since the control signals for data input / output are different from each other, the same names are assigned differently. have.

4, the first to third buffers 401 to 403, the enhanced packet multiplexer 404, the enhanced RS encoder 405, the enhanced data interleaver 406, the byte expander 407, MPEG Header inserter 408, M / E packet multiplexer 409, enhanced packet control unit 410, and enhanced interleaver control unit 411.

The first buffer 401 outputs a main packet in units of 188 bytes. The second and third buffers 402 and 403 include a function of converting an enhanced packet of 188 bytes into an enhanced packet of 164 bytes.

5 is a timing diagram illustrating an example of an input / output signal of the enhanced packet controller 410.

That is, the E8-VSB system can simultaneously transmit / receive main data and enhanced data. In addition, since the enhanced data can simultaneously transmit enhanced data of 1/2 code rate and enhanced data of 1/4 code rate, the transmission data of the E8-VSB method take these three different data as inputs. . Therefore, the main MPEG packet, the 1/2 enhanced packet, and the 1/4 enhanced packet are received through the first to third buffers 401, 402, and 403, respectively. In this case, three streams may be selectively received according to an enhanced mode map (also called an E8-VSB map), and the data rate may also be changed.

Although the flow of data indicated by solid lines in FIG. 4 flows from the input terminal on the left side to the output terminal on the right side, the flow of control signals indicated by dotted lines is reversed from the right side to the left side. When the VSB signal is output, the transmission is performed in accordance with the VSB frame because the blocks of FIG. 4 operate in accordance with the field synchronization signal used.

In this case, the M / E packet multiplexer 409 determines the multiplexing order of the main packet and the enhanced packet according to the enhanced mode map in accordance with the field synchronization signal of FIG. 5A, and the current data segment is configured as the main packet. When a main packet enable (MPE) signal is sent to the first buffer 401, the main packet is received from the first buffer 401 and output to the ATSC compatible preprocessor 220.

Similarly, when the current data segment is configured as an enhanced packet, the M / E packet multiplexer 409 generates an enhanced packet enable (EPE) signal as shown in FIG. By outputting to the control unit 410, the enhanced packet is provided through the MPEG header inserter 408.

Therefore, in the M / E packet multiplexer 409, except for the field sync segment section shown in FIG. 5 (a) and the ATSC RS parity section shown in FIG. 5 (d), the M / E packet multiplexer 409 is defined in the enhanced mode map in the remaining data segment sections. The main packet and the enhanced packet are output according to the multiplexing rule and order, and the attribute information of each byte is output accordingly.

The enhanced packet controller 410 receives a header packet enable (EPE) signal from the M / E packet multiplexer 409 and sends a header byte to the MPEG header inserter 408. Enable; HBE signal, Enhanced Byte Enable (EBE) signal, and Enhanced Interleaver Control Unit 411 outputs the EBE signal.

That is, when the EPE signal is input, the enhanced packet controller 410 divides the position of the MPEG header and the enhanced data byte with respect to the enhanced packet, generates an HBE signal and an EBE signal, and outputs the HBE signal and the EBE signal to the MPEG header inserter 408. . The HBE is an enable signal indicating an initial 4 byte section for an MPEG NULL header as shown in (e) of FIG. 5, and the EBE indicates an 184 byte section including enhanced data which is continued as shown in (d) of FIG. 5. Enable signal.

The MPEG header inserter 408 outputs 4 bytes for the MPEG null header and attribute information indicating that the bytes are the main data bytes in the HBE signal section (ie, the header section), and the EBE signal section (ie, the header section). In the section corresponding to the enhanced data byte, the byte output of the byte expansion unit 407 and its attribute information are output together.

Meanwhile, the enhanced interleaver controller 411 receives an enhanced interleaver output (EIO) signal from the enhanced data interleaver 406 and receives an EBE signal from the enhanced packet controller 410. An Enhanced Interaver Enable (EIE) signal is output to the Enhanced Packet Multiplexer 404, Enhanced RS Encoder 405, and Enhanced Data Interleaver 406.

The enhanced data interleaver 406 may include an enhanced interleaver input including an enhanced data byte and byte attribute information indicating whether the byte is 1/2 enhanced data or 1/4 enhanced data. ) To receive an interleaved signal and output an enhanced interleaver output (EIO) signal to the byte expander 407.

At this time, the operation of the enhanced data interleaver 406 is not performed every byte clock, but interleaving is performed in accordance with the EIE signal output from the enhanced interleaver controller 411. That is, if the output (EIO) of the enhanced data interleaver (406) is 1/2 enhanced byte, the EIE signal is skipped one byte clock, and the enhanced data interleaver (406) output (EIO) is expanded again at the next byte clock. Enable to control input such that the output of the enhanced data interleaver 406 is inputted to the byte expansion unit 407 at the next byte clock if it is 1/4 enhanced data. It is a signal.

This is for the byte expansion unit 407 to expand the EIO byte according to its attributes. That is, when the attribute of the EIO byte is 1/2 code rate, since the EIO byte is output from the enhanced data interleaver 406 once every two byte clock, the byte expansion unit 407 expands the EIO byte to two bytes. To the MPEG header inserter 408.

Similarly, if the attribute of the EIO byte is 1/4 code rate, the EIO byte is output from the enhanced data interleaver 406 once every 4 byte clock. Thus, the byte expansion unit 407 expands the EIO byte to 4 bytes. Output to MPEG header inserter 408. At this time, the input EII of the enhanced data interleaver 406 is simultaneously made with the output EIO.

As a result, the enhanced data interleaver 406 and the byte expansion unit 407 are integrated to operate. That is, since the enhanced data interleaver 406 and the byte expander 407 are operated in operation and no conventional buffer management is required, the main and enhanced multiplex packet processing units have a simple structure.

6 shows a state transition diagram for the operation of the enhanced interleaver control unit 411.

The enhanced interleaver control unit 411 receives an EBE signal from the enhanced packet control unit 410 and operates every byte clock and performs a state transition at each enhanced byte interval of the enhanced packet. That is, the synchronization for the initial state is matched by the field synchronization signal, and generates a signal for initially operating the enhanced data interleaver 406 in the enhanced packet interval and transitions to intermediate state 1. In the intermediate state 1, the operation of the enhanced data interleaver 406 is stopped at the next clock and transitions to the enhanced data interleaver 406 output receiving state.

In the interleaver output receiving state, when the attribute of the output byte of the enhanced data interleaver 406 is input to the next clock, and it is determined that the data has 1/2 code rate, the enhanced data interleaver 406 is operated again, and the intermediate state 1 is set. Metastasize. However, if the attribute of the output data of the enhanced data interleaver 406 input to the next clock in the interleaver output reception state is 1/4 code rate data, the intermediate data state is maintained while the operation of the enhanced data interleaver 406 is stopped. Transition to 2. In the intermediate state 2, the enhanced data interleaver 406 continues to be stopped at the next clock while transitioning to the initial state.

Through this state transition, the operation of the enhanced data interleaver 406 may be controlled by the attribute of the output byte of the enhanced data interleaver 406.

This is possible because the main data byte, which is the basis of the E8-VSB system, is twice as large as the enhanced data byte and twice as large as the 1/2 code rate.

The EIE signal generated by the enhanced interleaver control unit 411 continues to be used as a signal for operating the enhanced data interleaver 406 and its data processing.

The input of the enhanced data interleaver 406 comes from the output of the enhanced RS encoder 405. The enhanced RS encoder 405 operates in synchronization with an EIE signal. The enhanced RS encoder 405 receives an unencoded enhanced packet (UEP) of 164 bytes and adds 20 bytes for RS parity to output a packet of 184 bytes. do. The input UEP may be a packet for encoding 1/2 enhanced data or may be a packet for encoding 1/4 enhanced data. The output of the enhanced RS encoder 405 includes RS-coded data and attribute information indicating whether the enhanced packet is a packet for 1/2 or 1/4 enhanced.

The EIE signal of the enhanced interleaver control unit 411 is also used to operate the enhanced packet multiplexer 404. The enhanced packet multiplexer 404 is initialized by the field synchronization signal and determines the multiplexing order of the enhanced packet of 164 bytes according to the enhanced mode map information to generate a 1/2 enhanced packet or a 1/4 enhanced packet. The packet is output to the enhanced RS encoder 405 together with the packet attribute information. In addition, the enhanced packet multiplexer 404 receives Uncoded enhanced data in units of 164 bytes from the second buffer 402 or the third buffer 403 according to which enhanced packet is output for each enhanced packet. That is, in order of the 1/2 enhanced packet, a half-rate packet enable (HPE) signal is output to the second buffer 402, and the uncoded 1/2 enhanced packet (164 bytes unit) is transmitted from the second buffer 402. Receive Half-rate Packet Data (HPD). In addition, a quarter-enhanced packet enable (QPE) signal is output to the third buffer 403 in the order of the 1/4 enhanced packet, and the uncoded 1/4 enhanced packet (164 bytes unit) is transmitted from the third buffer 403. Quarter-rate Packet Data (QPD) is received. The input 164 bytes of the uncoded enhanced packet and the attribute information of the packet are outputted to the enhanced RS encoder 405.

The second and third buffers 402 and 403 for the enhanced packet receive 188 bytes of MPEG packets, and are uncoded in 164 byte units by HPE and QPE signals respectively output from the enhanced packet multiplexer 404. The packet is output to the enhanced packet multiplexer 404.

The above description is for the transmitter of the E8-VSB system, but the same processing is required for the receiver. In other words, the main and enhanced multiplex packet processing units including the E8-VSB preprocessor and the M / E packet multiplexer require the same processing as the transmitter to determine the attributes of each E8-VSB byte and symbol at the receiver.

However, it is different from the transmitter that the main data and the enhanced data are not actually processed, but are generated by processing only the attribute information of the data.

In FIG. 4, the processing flow of attribute information is shown in the flow of data information for convenience. In addition, the processor necessary for generating the attribute information in the receiver may be implemented without the need for the first to third buffers 401 to 403 of FIG. 4, and the enhanced RS encoder 405 may also be simply provided without undergoing an RS encoding function. Its role can be reduced by extending the byte attribute for an enhanced packet of 164 bytes to an attribute for 184 bytes. Furthermore, it is possible to implement an enhanced RS encoder and an enhanced packet multiplexer to generate an attribute for an enhanced packet of 184 bytes.

On the other hand, the terms used in the present invention (terminology) are terms defined in consideration of the functions in the present invention may vary according to the intention or practice of those skilled in the art, the definitions are the overall contents of the present invention It should be based on.

The present invention is not limited to the above-described embodiments, and as can be seen in the appended claims, modifications can be made by those skilled in the art to which the invention pertains, and such modifications are within the scope of the present invention.

The effects of the main and enhanced multiplex packet processing apparatus and method according to the present invention described above are as follows.

First, it is possible to simplify the implementation of the main and enhanced multiplex packet processing apparatus in the E8-VSB transmitter and receiver.

Second, since the implementation of the main and enhanced multiplex packet processing apparatus in the E8-VSB transmitter / receiver is performed without buffer management, the implementation of the corresponding E8-VSB transmitter / receiver is improved even if the enhanced mode map information changes with time. It has an easy effect.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (13)

An enhanced data interleaver operating in synchronization with the EIE signal and interleaving and outputting the enhanced data input in units of bytes; A byte extension unit for performing bit repetition or null data insertion on the interleaved enhanced data byte according to an output data attribute of the enhanced data interleaver to expand the data into two or four bytes; And If the enhanced data interleaver's output data (EIO) attribute is the first enhanced byte, it operates on the next byte clock after one byte clock. If the second enhanced byte, the three bytes clock is off and then on the next byte clock. And an enhanced interleaver control unit configured to generate an EIE signal for controlling operation and to output the EIE signal to the enhanced data interleaver. delete delete The method of claim 1, wherein the enhanced interleaver control unit Operates every byte clock in the enhanced packet interval to control transition to any of the initial state, intermediate state 1, enhanced data interleaver output receive state, and intermediate state 2. In the initial state generates a signal for operating the enhanced data interleaver and transitions to intermediate state 1, In the intermediate state 1, the operation of the enhanced data interleaver stops at the next byte clock, and transitions to the enhanced data interleaver output receiving state. In the interleaver output receiving state, if the attribute of the output data of the enhanced data interleaver at the next byte clock is the first enhanced, the enhanced data interleaver is operated again and transitions to the intermediate state 1, and if the second is enhanced, the enhanced data interleaver continues. Transitions to Intermediate state 2, leaving the behavior of In the intermediate state 2, the main and enhanced multiplexing packet processing apparatus, characterized in that the transition to the initial state while continuing to stop the operation of the enhanced data interleaver at the next byte clock. delete delete delete In the main and enhanced multiplex packet processing method of an E8-VSB transceiver comprising an enhanced data interleaver for interleaving and outputting the input enhanced data, And controlling to transition to any one of an initial state, an intermediate state 1, an enhanced data interleaver output receiving state, and an intermediate state 2 by operating every byte clock in the enhanced packet interval. In the initial state generates a signal for operating the enhanced data interleaver and transitions to intermediate state 1, In the intermediate state 1, the operation of the enhanced data interleaver is stopped and transitioned to the enhanced data interleaver output receiving state at the next byte clock. In the interleaver output receiving state, if the attribute of the output data of the enhanced data interleaver at the next byte clock is the first enhanced, the enhanced data interleaver is operated again and transitions to the intermediate state 1, and if the second is enhanced, the enhanced data interleaver continues. Transitions to Intermediate state 2, leaving the behavior of In the intermediate state 2, the main and enhanced multiplexing packet processing method, characterized in that the transition to the initial state while continuing to stop the operation of the enhanced data interleaver at the next byte clock. The method of claim 1, An MPEG header inserter for inserting an MPEG header into the enhanced data extended by the byte expander and outputting the enhanced MPEG packet according to an HBE / EBE signal; If the order of the packet to be multiplexed is the main packet, the main MPEG packet is inputted by generating and outputting the MPE signal. If the enhanced packet is an enhanced packet, the M / E packet receives and outputs the enhanced MPEG packet by generating and outputting the EPE signal. Multiplexer; When the EPE signal is input from the M / E packet multiplexer, the apparatus further comprises an enhanced packet control unit for generating an EBE signal and an HBE signal and outputting the EBE signal to the MPEG header inserter. . The method of claim 9, A first buffer for storing an input main MPEG packet and outputting the stored main MPEG packet to the M / E packet multiplexer when the MPE signal is input; A second buffer for storing first enhanced data input in units of 188 bytes, and outputting first enhanced data in units of 164 bytes when an HPE signal is input; A third buffer which stores second enhanced data input in units of 188 bytes, and outputs second enhanced data in units of 164 bytes when a QPE signal is input; In operation in synchronization with the EIE signal, if the order of the enhanced data to be currently multiplexed is the first enhanced data, an HPE signal is generated in the second buffer to receive the first enhanced data, and if the second enhanced data is the second enhanced data, And an enhanced packet multiplexer configured to output a QPE signal to a third buffer to receive and output second enhanced data. 10. The apparatus of claim 9, wherein the enhanced packet controller is When the EPE signal is input from the M / E packet multiplexer, the MPEG header and the enhanced data byte are divided for the enhanced packet, and an HBE signal and an EBE signal corresponding to the position are generated and output to the MPEG header inserter. , And the MPEG header inserter outputs MPEG NULL header data in the HBE signal section and outputs enhanced enhanced data in the EBE signal section. The method according to any one of claims 1 to 9, When the main and enhanced multiplexing packet processing apparatus is applied to the transmitter, each operation block outputs the actual processing data and the attribute information of the data together, main and enhanced multiplexing packet processing apparatus. The method according to any one of claims 1 to 9, When the main and enhanced multiplexing packet processing apparatus is applied to a receiver, each operation block processes and outputs only attribute information of the corresponding data, and outputs the main and enhanced multiplexing packet processing apparatus.

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