KR100720091B1 - Thin film transistor substrate and its manufacturing method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method of manufacturing the same. In order to have high light transmittance and achieve high brightness, an insulating film made of a resin containing a negative photosensitive agent is employed in the thin film transistor substrate. In the thin film transistor substrate according to the present invention, a gate wiring including a gate line and a gate electrode is formed on the substrate, and the gate insulating film covers the gate wiring. A data line is formed to insulate and intersect the gate line, and the thin film transistor including the gate electrode is electrically connected to the gate line and the data line. A pixel electrode is electrically connected to the thin film transistor, and an organic insulating film made of a resin containing a negative photosensitive agent is formed between the pixel electrode and the data line. In this case, the pixel electrode is preferably formed to overlap the data line.

Negative photoresist, organic insulating film, transmittance, high brightness

Description

Thin film transistor substrate and its manufacturing method {THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF}

1 is a graph showing the absorbance for each wavelength of the positive photosensitive agent and the negative photosensitive agent,

2 is a graph showing the transmittance of the negative acrylic,

3A to 3G are voltage-current graphs showing electrical characteristics of a thin film transistor after removing or cleaning a photoresist using a KOH base or NaOH base developer in a commonly used thin film transistor manufacturing process.

4 is a diagram illustrating an arrangement structure of a thin film transistor substrate according to a first exemplary embodiment of the present invention.

5 and 6 illustrate cross-sectional structures along cutting lines V-V ′ and VI-VI ′ in the substrate illustrated in FIG. 4.

7A to 13C are views illustrating a manufacturing process of the thin film transistor substrate according to the first embodiment of the present invention,

14 is a view showing an arrangement of a thin film transistor substrate according to a second embodiment of the present invention;

FIG. 15 is a view showing a cross-sectional structure along a cutting line XV-VV ′ in the substrate shown in FIG. 14.

16A through 19B are diagrams illustrating a manufacturing process of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

20 is a diagram illustrating an arrangement structure of a thin film transistor substrate according to a third exemplary embodiment of the present invention.

21 is a view showing a cross-sectional structure along the cutting line VI-XI 'in the substrate shown in FIG.

FIG. 22 is a view showing a layout structure of a substrate when the pattern of the data line and the color organic film is changed in the thin film transistor substrate according to the third embodiment of the present invention.

23A through 28B are diagrams illustrating a manufacturing process of a thin film transistor substrate according to a third exemplary embodiment of the present invention.

29 is a view showing an arrangement of a thin film transistor substrate according to a fourth embodiment of the present invention;

30 is a view showing a cross-sectional structure along the cutting line VII-VIII 'in the substrate shown in FIG.

31A to 33B are diagrams illustrating a manufacturing process of a thin film transistor substrate according to a third exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and more particularly, to a thin film transistor substrate used in a liquid crystal display device and a method of manufacturing the same.

In the liquid crystal display, a liquid crystal material is injected between a lower substrate on which a thin film transistor and a pixel electrode are formed and an upper substrate on which an opposing electrode and a color filter are formed, and different potentials are applied to the pixel electrode and the opposite electrode. By applying to form an electric field to change the arrangement of the liquid crystal molecules, and through this to adjust the transmittance of light to express the image.

A general fabrication processor used in the manufacturing process of a thin film transistor substrate is to form an active layer with a three-layer film of a gate insulating film, a semiconductor layer, and an ohmic contact layer on a gate wiring, and then form a data wiring thereon, and then to form a pixel electrode. In the previous step, a protective film is formed of silicon nitride to prevent a short between the pixel electrode and the data wiring.

However, in the manufacture of a liquid crystal display device in pursuit of high opening ratio, a protective film is formed of a thick organic insulating film instead of a silicon nitride film. For this purpose, an organic insulating material such as acrylic resin (BcryCycloButene) or SOB (Spin On) is used. It is used by coating by glass method. In addition, the organic insulating layer is manufactured and formed in the form of a photo definable material, and is mainly formed of a positive photosensitive resin by the addition of a positive type photosensitive agent.

However, such a positive photosensitive organic insulating layer has a very low transmittance, causing a problem of reducing the brightness of the thin film transistor substrate. In order to increase the transmittance of the positive photosensitive organic insulating layer, the entire surface exposure is performed, but there is a disadvantage in that an additional process called the front surface exposure is required, and furthermore, there is a limit in increasing the transmittance even in this method.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor substrate capable of achieving high brightness with high light transmittance and a method of manufacturing the same.

In order to solve this problem, the present invention employs an insulating film made of a resin containing a negative photosensitive agent in a thin film transistor substrate.

In detail, in the thin film transistor substrate according to the present invention, a gate wiring including a gate line and a gate electrode is formed on the substrate, and the gate insulating film covers the gate wiring. A data line is formed to insulate and intersect the gate line, and the thin film transistor including the gate electrode is electrically connected to the gate line and the data line. A pixel electrode is electrically connected to the thin film transistor, and an organic insulating film made of a resin containing a negative photosensitive agent is formed between the pixel electrode and the data line. In this case, the pixel electrode is preferably formed to overlap the data line.

 Here, a gate wiring is formed on the substrate, and the thin film transistor is a semiconductor pattern formed on the gate insulating film, a source electrode protruding from the data line and electrically connected to the semiconductor pattern, and electrically connected to the semiconductor pattern corresponding to the source electrode. An organic insulating layer may cover the data line and the thin film transistor. The contact hole may be formed in the organic insulating layer to expose the drain electrode, and the pixel electrode may be connected to the drain electrode through the contact hole.

In this case, the semiconductor pattern may be located along the data line, the source electrode and the drain electrode, and may further include a region located between the source electrode and the drain electrode, and the semiconductor pattern may be formed in an island shape.

Further, a data line is formed on the substrate, and further includes a color filter formed to overlap the data line on the substrate, wherein the organic insulating film covers the data line and the color filter, a gate line is formed over the organic insulating film, and the gate insulating film is organic. A gate hole is formed over the insulating layer, and contact holes for exposing data lines are formed in the organic insulating layer and the gate insulating layer. The thin film transistor is connected to the data line through a contact hole and a semiconductor pattern formed on the gate insulating layer. A source electrode may include a drain electrode in contact with the semiconductor pattern corresponding to the source electrode, and the pixel electrode may be integrally formed with the drain electrode.

In this case, the source electrode and the drain electrode may be formed of ITO or IZO, and may further include a protective film covering the thin film transistor and a colored organic film formed on the protective film. The data line may extend along the gate line to cover a gap between the gate line and the pixel electrode, and the colored organic layer may be formed to cover the gap between the data line and the neighboring data line. The light blocking part may be further formed on the substrate to overlap the semiconductor pattern, and the light blocking part may extend from the data line.                     

In addition, the gate wiring is formed on the substrate, and the thin film transistor is a semiconductor pattern formed on the gate insulating film, a source electrode protruding from the data line and electrically connected to the semiconductor pattern, and a drain corresponding to the source electrode and electrically connected to the semiconductor pattern. An electrode, an insulating film covering the thin film transistor and the gate insulating film, and a color filter formed on the insulating film, wherein the organic insulating film covers the color filter, and contact holes for exposing the drain electrode are formed in the organic insulating film, the color filter, and the insulating film. The pixel electrode may be connected to the drain electrode through the contact hole.

In order to manufacture the thin film transistor substrate according to the present invention, a gate wiring including a gate line and a gate electrode is formed on the substrate, and a gate insulating film covering the gate wiring is formed. Next, a semiconductor pattern is formed on the gate insulating layer, and a data line including a data line crossing the gate line, a source electrode in contact with the semiconductor pattern, and a drain electrode corresponding to the source electrode and in contact with the semiconductor pattern is formed. Next, an organic insulating film made of a negative photosensitive resin is formed so as to cover the data wirings and the semiconductor pattern, and a contact hole for exposing a drain electrode is formed in the organic insulating film. Next, a pixel electrode connected to the drain electrode through the contact hole is formed on the organic insulating layer.

In addition, before forming the organic insulating film, an insulating film covering the data line and the substrate is formed, a color filter overlapping the data line is formed on the insulating film, and contact holes exposing the drain electrode are formed in the organic insulating film, the color filter, and the insulating film. can do.

Here, the semiconductor pattern and the data line may be formed together by a photolithography process using a photoresist pattern having a different thickness. The photoresist pattern may include a first portion having a first thickness on the upper portion of the data line and between the source electrode and the drain electrode. It may be formed as a second portion having a second thickness thinner than the first thickness at the top of.

The formation of the semiconductor pattern and the data wiring includes depositing a semiconductor layer and a conductive layer on a gate insulating film, forming a photoresist pattern, etching a conductive layer using the photoresist pattern as a mask, and exposing a part of the semiconductor layer. Removing the exposed portion and the second portion of the photoresist pattern to complete the semiconductor pattern, exposing a portion of the conductive layer between the source electrode and the drain electrode, removing the exposed portion of the conductive layer to complete the data wiring, It may be through the step of removing the first portion of the photosensitive film pattern. In this case, the photoresist pattern may be formed using a photomask including a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region.

In addition, in order to manufacture a thin film transistor substrate according to the present invention, after forming a data wiring including a data line on the insulating substrate, and forming a color filter of red, green, blue on the substrate, the organic material consisting of a negative photosensitive resin The insulating film covers the data line and the color filter. Next, a gate wiring including a gate line and a gate electrode is formed on the organic insulating film, and a gate insulating film covering the gate wiring is formed. Subsequently, a semiconductor pattern is formed on the gate insulating film, and contact holes for exposing a portion of the data lines are formed in the gate insulating film and the insulating film, and then a source electrode and a drain electrode contacting the semiconductor pattern, respectively, and a pixel electrode connected to the drain electrode. To form a pixel wiring including a.

The gate insulating layer, the contact hole, and the semiconductor pattern may be formed by sequentially depositing a gate insulating layer and a semiconductor layer covering the gate wiring, and forming a gate insulating layer, a contact hole, and a semiconductor layer on the semiconductor layer. Forming a photoresist pattern including a second portion thinner than the first portion in portions other than the portions where the contact holes are to be formed, and using the first and second portions of the photoresist as masks for semiconductor layers, gate insulating films, and organic insulating films Etching to form contact holes, removing the second portion of the photoresist pattern, forming a semiconductor pattern by etching the semiconductor layer using the first portion of the photoresist pattern as a mask, and forming the first portion of the photoresist pattern It can be made through the step of removing.

In this case, the data line may be formed to extend to the data line to form a light blocking portion positioned at a portion corresponding to the semiconductor layer pattern, and the light blocking portion may be extended to cover the light leakage region between the gate line and the pixel electrode. Can be.

Next, the present invention will be described with reference to the drawings.

As mentioned, the organic insulating film in the existing thin film transistor substrate is formed of a positive photosensitive resin containing a positive photosensitive agent. However, such a positive photosensitive resin has a low transmittance because it contains a positive photosensitive compound having a high light absorption property.

1 is a graph showing absorbance for each wavelength of a positive photosensitive agent and a negative photosensitive agent.                     

In the case of the positive photosensitive agent, the absorbance is very low at the long wavelength of 500 nm or more, but the absorbance is high at the short wavelength (450 nm or less). Since the positive photosensitive resin containing such a positive photosensitive agent lowers the transmittance of short wavelength light, it acts as a factor of lowering the light transmittance of the substrate when implementing color.

On the other hand, in the case of a negative type photosensitive agent, the absorbance is very low in the entire visible light range (400-800 nm). The negative photosensitive resin containing such a negative photosensitive agent makes it possible to achieve high brightness by increasing the light transmittance of the substrate when implementing color. As such, the high transmittance of the negative photosensitive resin is associated with the absorbance of the negative photosensitive agent.

The negative photosensitive resin is prepared by mixing a negative photosensitive agent with ordinary resin. That is, a negative photosensitive agent is mixed in acrylic resin or BCB which is a normal organic insulating material, and is manufactured. In this case, the acrylic resin or BCB is 10W% to 20W%, the negative photosensitive agent is 10W% to 20W%, and the solvent is preferably 60W% to 70W% with respect to the total content of the composition.

FIG. 2 is a graph showing the transmittance of the negative acrylic after applying and baking the negative acrylic.

Negative acrylic shows high transmittance of more than 95% over the entire wavelength range, including short wavelengths.

In the development process for patterning such a negative photosensitive resin, a developer of KOH base or NaOH base is used. In general, metal ions such as K + and Na + in the thin film transistor manufacturing process deteriorate the electrical properties of the thin film transistor, but the experimental results, it was confirmed that it is not. This is due to the fact that metal ions such as K + and Na + are present in the channel portion of the thin film transistor, but they do not have deterioration characteristics, but that the metal ions are washed out in the cleaning process after developing with the above KOH base or NaOH base developer. do.

3A to 3G each show voltage-current graphs showing electrical characteristics of thin film transistors after photoresist removal or cleaning using a KOH base inorganic alkali solution developer in a generally applied thin film transistor manufacturing process. will be.

FIG. 3A shows that when the above developer is cleaned before the deposition of SiN _x / a-Si / n + a-Si triple layer, FIG. 3B illustrates when the photoresist used to form the semiconductor pattern is removed with the above developer, FIG. When the photoresist used to form the drain electrode is removed with the above developer, FIG. 3D shows that n + a-Si, i.e., the ohmic contact layer on the upper portion of the channel, is cleaned with the above developer, and FIG. 3E shows a contact hole in the protective film. 3F shows that when the aluminum developer exposed through the contact hole of the protective film is etched and then cleaned with the above developer, FIG. 3G shows that when the pixel electrode is developed and then cleaned with the above developer The voltage-current characteristics of the thin film transistors are respectively shown.

As shown in each graph, it can be seen that the on / off current of the thin film transistor is normally formed. In other words, even when NaOH base or KOH base developer is used in the thin film transistor manufacturing process, the electrical properties of the thin film transistor are not affected. That is, even when the KOH base or NaOH base developer is applied to the thin film transistor manufacturing process, it can be seen that there is no change in on / off current characteristics.

In the present invention, an organic insulating film formed of a negative photosensitive resin capable of ensuring high transmittance is intended to be employed in a thin film transistor substrate.

4 is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention, and FIGS. 5 and 6 are cross-sectional views respectively taken along the cutting lines VV 'and VI-VI' shown in FIG.

On the insulating substrate 10, a low resistance characteristic is formed on the lower metal layer 201 of a thickness of 500 to 1000 ∼ made of a conductive material such as chromium-based such as chromium or chromium alloy, molybdenum-based such as molybdenum or molybdenum alloy, chromium nitride or molybdenum nitride. The gate wirings 22, 24, 26, 28 of the double layer structure which consist of the upper metal layer 202 of 1500-2500 micrometers thick which consist of aluminum series, such as aluminum or aluminum alloys, such as aluminum-neodymium, are formed. The gate wirings 22, 24, 26, and 28 may be formed as a single layer or a triple layer or more in addition to the double layer structure.

The gate wires 22, 24, 26, and 28 are parallel to the gate line portions 22, 24, 26 and the gate line 22 formed of the gate line 22, the gate pad 24, and the gate electrode 26, and are formed on the upper plate. And a sustain electrode 28 for a storage capacitor that receives a voltage such as a common electrode voltage input to the common electrode of the external device.

The storage electrode 28 overlaps with the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82, which will be described later, to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line, which will be described later, If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

On the gate wirings 22, 24, 26, 28, a gate insulating film 30 of 2500 to 4000 micrometers thick, made of silicon nitride, covers the gate wirings 22, 24, 26, 28.

On the gate insulating film 30, semiconductor patterns 42 and 48 having a thickness of 800 to 1500 Å made of a semiconductor material such as amorphous silicon are formed. Amorphous silicon is heavily doped with n-type impurities on the semiconductor patterns 42 and 48. The resistive contact layer patterns 55, 56, and 58 having a thickness of about 500 to about 800 microns are formed of a semiconductor material doped with an impurity.

The semiconductor patterns 42 and 48 include a semiconductor pattern 42 for a thin film transistor and a semiconductor pattern 48 for a storage capacitor, which are regions between the source electrode 65 and the drain electrode 66, that is, the channel region of the thin film transistor. Except for the above, the data lines 62, 64, 65, 66, 68 and the ohmic contact layer patterns 55, 56, 58 have the same shape. That is, the semiconductor capacitor pattern 48 for the storage capacitor is the same as the conductor pattern 68 for the storage capacitor and the contact layer pattern 58 for the storage capacitor, whereas the semiconductor pattern 42 for the thin film transistor has the data line 62 described later. ), The same as the data line portions 62, 64, 65, 66 formed by the data pad 64, the source electrode 65, and the drain electrode 66, but between the source electrode 65 and the drain electrode 66. It further includes a region defined as a channel of the thin film transistor located.

On the resistive contact layer patterns 55, 56 and 58, a lower metal layer 601 of 500 to 1000 Å thickness consisting of a conductive material such as chromium-based such as chromium or chromium alloy, molybdenum-based such as molybdenum or molybdenum alloy, chromium nitride or molybdenum nitride Data layer 62, 64, 65, 66, 68 consisting of an upper metal layer 602 having a thickness of 1500-2500 이루어진 made of aluminum series such as aluminum having low resistance or aluminum alloy such as aluminum-neodymium. Is formed. The data lines 62, 64, 65, 66, and 68 may also be formed of a single layer like the gate lines 22, 24, 26, and 28.

The data lines 62, 64, 65, 66, and 68 are formed of data lines 62 formed in the vertical direction, data pads 64, source electrodes 65 and drain electrodes 66 of the thin film transistors. (62, 64, 65, 66) and a conductor pattern 68 for a storage capacitor which are located on the storage electrode 28 are included.

The ohmic contact layer patterns 55, 56, and 58 lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has the same form as the wirings 62, 64, 65, 66 and 68. At this time, one ohmic contact layer pattern 55 is in contact with the integral data line 62, the data pad 64, and the small electrode 65, and the other ohmic contact layer pattern is formed by draining 56 of the substrate. In contact with the electrode 66, another contact layer pattern 58 is in contact with the conductor pattern 68 for the storage capacitor.

On the data lines 62, 64, 65, 66, 68 and the gate insulating film 30, a protective film 70 having a thickness of 2.5 to 3.0 mu m made of a negative photosensitive resin is formed. Negative photosensitive resins are prepared by incorporating negative photosensitive agents in resins such as acrylic series, BenzoCycloButane (BCC) and polyimide. In this case, the acrylic resin or BCB is 10W% to 20W%, the negative photosensitive agent is 10W% to 20W%, and the solvent is preferably 60W% to 70W% with respect to the total content of the composition.

As described above, when the protective film 70 is formed of a negative photosensitive resin, the light transmittance can be increased and high brightness can be achieved as compared with the case of forming a positive photosensitive resin having a small light absorption characteristic. In addition, the entire surface exposure work for increasing the transmittance of the protective film can be omitted.

The passivation layer 70 includes a contact hole 72 exposing the upper conductive layer 602 of the drain electrode 66, a contact hole 76 exposing the upper conductive layer 602 of the data pad 64, and the gate insulating layer 30. The contact hole 74 which exposes the gate pad 24 is formed. In the protective film 70, a contact hole 78 exposing the upper conductive layer 602 of the conductive capacitor pattern 68 for the storage capacitor is formed.

On the passivation layer 70, a pixel electrode 82 having a thickness of 500 to 1500 mW is formed to receive an image signal from a thin film transistor and generate an electric field together with the electrodes of the upper plate. The pixel electrode 82 may be formed of an IZO series and is connected to the drain electrode 66 through a contact hole 72 to receive an image signal. In addition, the pixel electrode 82 is connected to the conductive capacitor conductor 68 through the contact hole 78 to transmit an image signal to the conductive capacitor conductor 68.

Between the pixel electrode 82 and the data line 62, a thick protective film 70 made of an organic insulating material having a low dielectric constant, such as a negative photosensitive resin, is formed. Thus, the parasitic capacitance caused by the overlap of the pixel electrode 82 and the data line 62 is sufficiently small. Accordingly, the pixel electrode 82 may overlap the data line 62, thereby reducing the width of the black matrix covering the light leaking region between the pixel electrode 82 and the data line 62. Thus, there is an advantage that can increase the aperture ratio.

In addition, an auxiliary gate pad 84 and an auxiliary data pad 86 made of an IZO series connected to the gate pad 24 and the data pad 64 through the contact holes 74 and 76 are formed on the passivation layer 70. have.

Here, the pixel electrode 82, the auxiliary gate pad 84, and the auxiliary data pad 86 may also be formed of an ITO series. In this case, the pixel electrode 82, the auxiliary gate pad 84, and the auxiliary data pad 86 may not be in contact with the metal layer having poor contact properties with the ITO series. It is preferable. That is, the upper metal layers 202 and 602 made of aluminum exposed through the contact holes 72, 74 and 76 exposing the drain electrode 66, the gate pad 24 and the data pad 64 are removed or made of aluminum. The metal layers 202 and 602 are formed below the double layer wiring structure.

Next, a method of manufacturing the thin film transistor substrate according to the first embodiment of the present invention will be described with reference to FIGS. 4 to 6 and FIGS. 7A to 13C.

First, as shown in FIGS. 7A, 7B, and 7C, a lower metal layer 201 is deposited, and an upper metal layer 202 made of aluminum is deposited thereon.

Subsequently, the two metal layers 201 and 202 are etched by a photolithography process using a mask to form the gate wirings 22, 24, 26, and 28 having a double layer structure on the substrate 10. At this time, the gate wirings 22, 24, 26, 28 are formed with gate lines 22, 24, 26 made of gate lines 22, gate pads 24, gate electrodes 26, and storage electrodes for storage capacitors ( 28).                     

Next, as shown in FIGS. 8A, 8B, and 8C, the gate insulating film 30 is formed, and the semiconductor patterns 42 and 48 and the ohmic contact layer patterns 55, 56, and 58 are formed on the gate insulating film 30. And a double layer data line 62, 64, 65, 66, and 68 formed of a lower metal layer 601 and an upper metal layer 602 made of aluminum.

At this time, the data lines 62, 64, 65, 66, and 68 are formed of the data line 62, 64, 65 consisting of the data line 62, the data pad 64, the source electrode 65, and the drain electrode 66. 66 and a conductor pattern 68 for the storage capacitor.

The ohmic contact layer patterns 55, 56, and 58 having the same pattern are in contact with the lower end of the data wires 62, 64, 65, 66, and 68, and the ohmic contact layer patterns 55, 56, and 58 are in contact with the bottom of the data line 62, 64, 65, 66, and 68. The semiconductor patterns 42 and 48 including the thin film transistor semiconductor pattern 42 and the storage capacitor semiconductor pattern 48 are in contact with each other. The thin film transistor semiconductor pattern 42 is the same as the data line portions 62, 64, 65, and 66, and further includes a region defined as a channel of the thin film transistor positioned between the source electrode 65 and the drain electrode 66. Include.

The data lines 62, 64, 65, 66, and 68, the ohmic contact layers 55, 56, and 58, and the semiconductor patterns 42 and 48 may be formed using only one mask. This will be described in detail with reference to FIGS. 9A to 12B.

First, as shown in FIGS. 9A and 9B, a gate insulating film 30 made of silicon nitride, a semiconductor layer 40, and impurities are doped on an exposed entire surface including the gate wirings 22, 24, 26, and 28. The deposited semiconductor layer 50 is continuously deposited by chemical vapor deposition. Then, the lower metal layer 601 and the upper metal layer 602 are deposited thereon, and a photoresist film is applied thereon.

Subsequently, light is irradiated to the photoresist film through a mask, and then developed to form the photoresist patterns 112 and 114. In this case, the photoresist patterns 112 and 114 may have a first portion 112 of the photoresist layer positioned at the data line portion A between the channel portion C of the thin film transistor, that is, between the source electrode 65 and the drain electrode 66. It is formed to be thicker than the second portion 114 of the positioned photosensitive film, and the other portion (B) is formed so as not to remain. The ratio of the thickness of the first portion 112 of the photosensitive film of the second portion 114 of the photosensitive film should be different depending on the process conditions in the etching process, which will be described later, but the thickness of the second portion 114 is determined by the first portion 112. It is preferable to set it as 1/2 or less of thickness.

As such, photoresist patterns having partially different thicknesses are formed using one mask having partially different transmittance. In order to control the light transmission, a slit or lattice pattern or a mask with a translucent film is used. In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the photosensitive film is irradiated with light through such a mask, the polymers are completely decomposed at the portion (C) directly exposed to the light, and the polymers are completely decomposed because the amount of light is less at the portion (B) corresponding to the slit pattern or translucent film. The polymer is hardly decomposed in the part A covered by the light shielding film. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

When the selective exposed photoresist is developed, only portions where polymer molecules are not decomposed remain, and a photoresist having a thickness thinner than a portion that is not irradiated with light is left in the central portion irradiated with little light.

Next, as shown in FIGS. 10A and 10B, the aluminum-based upper conductive layer 602 and the lower conductive layer 601 of the other portion B are exposed using the photoresist patterns 112 and 114 as masks. It removes and exposes the semiconductor layer 50 doped with impurities below it.

In this way, only the conductor patterns 67 and 68 in the channel portion C and the data wiring portion A remain, and the conductive layer in the other portion B is removed, and the semiconductor layer doped with impurities located thereunder. 50 is revealed. The conductor pattern 68 is a conductor pattern for the storage capacitor, and the conductor pattern 67 is a data wiring metal layer in which the source electrode 65 and the drain electrode 66 are not separated yet and exist in an integrated state.

Next, as shown in FIGS. 11A and 11B, the semiconductor layer 50 doped with the exposed impurities of the other portion B and the semiconductor layer 40 thereunder together with the second portion 114 of the photoresist film. Simultaneously removed by dry etching. The etching may be performed under the condition that the photoresist patterns 112 and 114, the semiconductor layer 50 and the semiconductor layer 40 doped with impurities are simultaneously etched, and the gate insulating layer 30 is not etched. It is preferable to etch under the conditions in which the etching ratio with respect to (112, 114) and the semiconductor layer 40 is about the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness.

When the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the second portion 114 of the photoresist layer is the sum of the thicknesses of the semiconductor layer 40 and the semiconductor layer 50 doped with impurities. It must be less than or equal to

In this case, the second portion 114 of the photoresist film positioned in the channel portion C is removed to expose the conductor pattern 67 of the channel portion C, and the semiconductor layer 50 doped with impurities in the other portion B. ) And the semiconductor layer 40 are removed to reveal the gate insulating film 30 thereunder. On the other hand, since the first portion 112 of the photosensitive film of the data wiring portion A is also etched, the thickness becomes thin.

In this step, the semiconductor patterns 42 and 48 including the thin film transistor semiconductor pattern 42 and the storage capacitor semiconductor pattern 48 are completed.

The ohmic contact layer 57 is formed on the thin film transistor semiconductor pattern 42 in the same pattern as the semiconductor pattern 42. The ohmic contact layer 58 is also formed on the semiconductor capacitor 48 for the storage capacitor. It is formed in the same pattern as 48).

Subsequently, ashing removes residues of the second portion of the photoresist film remaining on the surface of the conductor pattern 67 of the channel portion C.

Next, as shown in FIGS. 12A and 12B, a double layer conductor pattern 67 positioned in the channel portion C using the first portion 112 of the remaining photoresist pattern as a mask and the ohmic contact layer thereunder. The pattern 57 is removed by etching.

In this case, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the first portion 112 of the photoresist pattern may also be etched to a certain thickness. At this time, the etching must be performed under the condition that the gate insulating layer 30 is not etched, and the first portion 112 of the photoresist pattern is etched to expose the lower data lines 62, 64, 65, 66, and 68. It is a matter of course that the photosensitive film pattern is thick so that there is no.

In this way, the source electrode 65 and the drain electrode 66 are separated from the conductor pattern 67 to complete the data line 62, the source electrode 65, and the drain electrode 66. The patterns 55, 56 and 58 are completed.

Finally, when the first portion 112 of the photosensitive film pattern remaining in the data wiring portion A is removed by an ashing operation, a cross-sectional structure as shown in FIGS. 8B and 8C can be obtained.

Next, as shown in FIGS. 13A, 13B, and 13C, a negative photosensitive resin is thickly coated on the data lines 62, 64, 65, 66, and 68 to form a protective film 70. At this time, the protective film 70 may be formed by applying an acrylic series containing a negative photosensitive agent by SOG method.

Subsequently, contact holes 72, 76, and 78 are formed in the protective film 70 to expose the upper electrode layer 602 of the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor. A contact hole 74 exposing the gate pad 24 is formed in the passivation layer 70 and the gate insulating layer 30.                     

Since the protective film 70 in the present invention contains a photosensitive agent, the pattern may be formed by directly exposing and developing the protective film 70 without forming a separate photosensitive film pattern. After the protective film 70 is selectively exposed and developed, the drain electrode 66, the data pad 64, and the conductive capacitor conductor 68 for the storage capacitor are exposed through the contact holes 72, 74, and 78. In the process of developing the protective film 70, a NaOH base developer or a KOH base developer may be used. Even when the protective film 70 is patterned using a developer containing such metal ions, the electrical properties of the thin film transistor are not changed. .

Subsequently, when the portion of the gate insulating layer 30 exposed through the contact hole 76 is etched, the gate pad 24 is exposed.

In the case where the pixel electrode 82 is formed of ITO, it is preferable that the portions of the aluminum layers 202 and 602 exposed through the contact holes 72, 74, 76 and 78 are etched and removed to expose the lower metal layers 201 and 601. Do.

Subsequently, as shown in FIGS. 4, 5, and 6, the conductive pattern for the drain electrode 66 and the storage capacitor is deposited through a photolithography process using a mask by depositing a transparent material layer made of ITO or IZO. An auxiliary gate pad 84 and an auxiliary data pad 86 connected to the pixel electrode 82, the gate pad 24, and the data pad 64 connected to the 68 are formed.

As described above, the thin film transistor substrate according to the first embodiment of the present invention manufactured using four masks forms a protective film 70 using an organic insulating material such as a negative photosensitive resin, thereby providing a light transmittance of the substrate. Can be increased, and high brightness can be secured.

FIG. 14 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention, and FIG. 15 is a cross-sectional view of the thin film transistor substrate taken along the cutting line XV-VV ′ shown in FIG. 14.

On the insulating substrate 10, a low resistance property is formed on the lower metal layer 201 having a thickness of 500 to 1500 Å made of a conductive material such as chromium-based such as chromium or chromium alloy, molybdenum-based such as molybdenum or molybdenum alloy, chromium nitride or molybdenum nitride. The gate wirings 22, 24, and 26 of the double layer structure which consist of the upper metal layer 202 of 1500-2500 micrometers thick which consist of aluminum series, such as aluminum or an aluminum alloy, are formed. In this case, the gate wirings 22, 24, and 26 may be formed as a single layer or a triple layer or more in addition to the double layer structure.

The gate lines 22, 24, and 26 include a gate line 22, a gate line 22, a gate pad 24, and a gate electrode 26 extending in the horizontal direction.

On the insulating substrate 10, a gate insulating film 30 having a thickness of 1500 to 4000 μm made of an insulating material such as silicon nitride or silicon oxide covers the gate wirings 22, 24, and 26.

On the gate insulating layer 30, a semiconductor pattern 42 of 800 to 1500 Å thickness made of a semiconductor material such as amorphous silicon overlapping with the gate electrode 26 is formed, and on the semiconductor pattern 42, n-type impurities are heavily doped. An ohmic contact layer 55, 56 of 500 to 800 Å thickness is formed of a semiconductor material doped with an impurity such as amorphous silicon.

On the ohmic contact layers 55 and 56 and the gate insulating film 30, a lower portion of 500 to 1500 Å thick consisting of a conductive material such as chromium-based such as chromium or chromium alloy, molybdenum-based such as molybdenum or molybdenum alloy, chromium nitride or molybdenum nitride On the metal layer 601, a data layer 62, 64, 65, 66 having a double layer structure formed of an upper metal layer 602 having a thickness of 1500 to 2500 Å made of an aluminum series such as aluminum or an aluminum alloy having low resistance is formed. . The data lines 62, 64, 65, and 66 may also be formed as a single layer or a triple layer like the gate lines 22, 24, and 26.

The data wires 62, 64, 65, and 66 protrude from the data line 62, the data pad 64, and the data line 62 formed in the vertical direction to contact a single ohmic contact layer 55 to form a thin film. A source electrode 65 constituting part of the transistor and a drain electrode 66 constituting part of the thin film transistor in contact with the other ohmic contact layer 56 corresponding to the source electrode 65 are included.

On the exposed front surface of the substrate including the data lines 62, 64, 65 and 66, a protective film 70 having a thickness of 2.5 to 3.0 mu m made of a negative photosensitive resin is formed. Negative photosensitive resins are prepared by incorporating negative photosensitive agents in resins such as acrylic series, BenzoCycloButane (BCC) and polyimide. In this case, the acrylic resin or BCB is 10W% to 20W%, the negative photosensitive agent is 10W% to 20W%, and the solvent is preferably 60W% to 70W% with respect to the total content of the composition.

As described above, when the protective film 70 is formed of the negative photosensitive resin, the light transmittance can be higher than that of the positive photosensitive resin, and high luminance can be achieved. In addition, the entire surface exposure work for increasing the transmittance of the protective film can be omitted.

The passivation layer 70 includes a contact hole 72 exposing the upper conductive layer 602 of the drain electrode 66, a contact hole 76 exposing the upper conductive layer 602 of the data pad 64, and the gate insulating layer 30. The contact hole 74 which exposes the gate pad 24 is formed.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 may be formed of an IZO series, and is electrically connected to the drain electrode 66 through the contact hole 72 to receive an image signal.

A thick protective film 70 made of an organic insulating material having a low dielectric constant, such as a negative photosensitive resin, is formed between the pixel electrode 82 and the data line 62. Thus, the parasitic capacitance caused by the overlap of the pixel electrode 82 and the data line 62 is sufficiently small. Therefore, it is possible for the pixel electrode 82 to overlap the data line 62, thereby reducing the width of the black matrix covering the light leakage region between the pixel electrode 82 and the data line 62. This has the advantage of increasing the aperture ratio.

On the gate pad 24 and the data pad 64, an auxiliary gate pad 84 and an auxiliary data pad 86 made of an IZO series, which are connected to each other through contact holes 74 and 76, are formed.                     

Here, the pixel electrode 82, the auxiliary gate pad 84, and the auxiliary data pad 86 may also be formed of an ITO series. In this case, the pixel electrode 82, the auxiliary gate pad 84, and the auxiliary data pad 86 may not be in contact with the metal layer having poor contact properties with the ITO series. It is preferable. That is, the upper metal layers 202 and 602 made of aluminum exposed through the contact holes 72, 74 and 76 exposing the drain electrode 66, the gate pad 24 and the data pad 64 are removed or made of aluminum. The metal layers 202 and 602 are formed below the double layer wiring structure.

Next, a method of manufacturing the thin film transistor substrate according to the second embodiment of the present invention will be described in detail with reference to FIGS. 14 and 15 and FIGS. 16A to 22B.

First, as shown in FIGS. 16A and 16B, a lower metal layer 201 is deposited on a substrate 10, and an upper metal layer 202 made of aluminum is deposited thereon. Subsequently, the two metal layers 201 and 202 are etched by a photolithography process using a mask to form gate wirings 22, 24, and 26 having a double layer structure on the substrate 10. The gate wirings 22, 24, and 26 include a gate line 22, a gate pad 24, and a gate electrode 26.

17A and 17B, the gate insulating layer 30, the semiconductor layer, and the semiconductor layer doped with impurities are sequentially stacked. Subsequently, the semiconductor layer and the semiconductor layer doped with impurities are etched by a photolithography process using a mask to form an island-shaped semiconductor pattern 42 and an ohmic contact layer 52.

Next, as shown in FIGS. 18A and 18B, a lower metal layer 601 is deposited, and an upper metal layer 602 made of aluminum is deposited thereon. Subsequently, the two metal layers 601 and 602 are etched by a photolithography process using a mask to form the data lines 62, 64, 65 and 66. The data lines 62, 64, 65, and 66 include a data line 62, a data pad 64, a source electrode 65, and a drain electrode 66.

Subsequently, the island-like ohmic contact layer 52 integrally formed using the source electrode 65 and the drain electrode 66 as a mask is etched to contact the source electrode 65 with the ohmic contact layer 55 and the drain electrode ( 66 into a resistive contact layer 56 in contact with it.

Next, as shown in FIGS. 19A and 19B, the negative photosensitive resin is thickly coated on the data lines 62, 64, 65, and 66 to form a protective film 70. At this time, the protective film 70 may be applied by the SOG method. And the negative photosensitive resin preferably contains acrylic resin or BCB, 10B% to 20W%, negative photoresist, 10W% to 20W% solvent, 60W% to 70W% solvent relative to the total content of the composition. Do.

Subsequently, contact holes 72 and 76 exposing the drain electrode 66 and the aluminum based wiring layer, which is the upper wiring layer 602 of the data pad 64, are formed in the protective film 70, and at the same time, the protective film 70 and the gate insulating film are formed. A contact hole 74 exposing the gate pad 24 is formed in 30.

Since the protective film 70 contains a photosensitive agent, a pattern may be formed by directly exposing and developing the protective film 70 without forming a separate photoresist pattern. After the protective film 70 is selectively exposed and developed in this manner, the drain electrode 66 and the data pad 64 are exposed through the contact holes 72 and 76. In the process of developing the protective film 70, a NaOH base developer or a KOH base developer may be used. Even when the protective film 70 is patterned by using a developer containing such metal ions, the electrical properties of the thin film transistor do not change. none.

Subsequently, when the portion of the gate insulating layer 30 exposed through the contact hole 74 is etched, the gate pad 24 is exposed.

When the pixel electrode 82 is formed of ITO, the portions of the aluminum layers 202 and 602 exposed through the contact holes 72, 74, and 76 are etched and removed to expose the lower metal layers 201 and 601. You can proceed.

Next, as shown in FIGS. 14 and 15, the pixel electrode 82 and the gate, which are connected to the drain electrode 66 through a photolithography process using a mask by depositing a transparent material layer made of ITO or ITO, are used. An auxiliary gate pad 84 and an auxiliary data pad 86 connected to the pad 24 and the data pad 64, respectively, are formed.

As described above, in the thin film transistor substrate according to the second embodiment of the present invention manufactured using five masks, the protective film 70 is formed by using an organic insulating material such as a negative photosensitive resin, thereby forming light of the substrate. Transmittance can be increased and high brightness can be ensured.

20 is a layout view of a thin film transistor substrate according to a third exemplary embodiment of the present invention, and FIG. 21 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 20 along a cutting line XXXI ′. The drawings show a lower substrate on which a thin film transistor and the like are formed, and an upper substrate on which a common electrode and the like are formed.

The lower substrate is described as follows.                     

Data wirings 21, 23, 25 having a double layer structure of the lower metal layer made of aluminum series such as aluminum or aluminum alloy and the upper metal layer made of chromium or molybdenum or molybdenum alloy or chromium nitride or molybdenum nitride on the insulating substrate 100 Is formed.

The data lines 21, 23, and 25 are connected to the data lines 21 extending in the vertical direction and to the ends of the data lines 21, and receive data signals from the outside and transmit them to the data lines 21. And a light blocking portion 23 protruding from the data line 21 and blocking light incident from the lower portion of the substrate 100 to the semiconductor pattern 71 of the thin film transistor, which will be described later. Here, the light blocking unit 23 also has a function of a black matrix to block light leakage, and may be formed by disconnecting the data line 21 and disconnected wiring.

Here, considering that the pixel wirings 110, 111, 112, 113, and 115 formed thereafter are indium tin oxide (ITO), the lower metal layer is formed of a material having a low resistance, aluminum, aluminum alloy, or copper (Cu), Although the upper metal layer is formed of chromium, which is a material having good contact properties with other materials, when the pixel wirings 110, 111, 112, 113, and 115 are indium zinc oxide (IZO), a single film of aluminum or an aluminum alloy is used. It is preferable to make it, and when copper is excellent in contact property with IZO and ITO, it is preferable to form by a single film of copper.

Color filters 31, 32, and 33 of red (R), green (G), and blue (B), whose edges cover the data lines 21, are formed in the pixel region above the insulating substrate 100, respectively. . Here, the edges of the color filters 31, 32, 33 overlap the data line 21.

On the exposed front surface of the substrate including the data lines 21, 23, 25 and the color filters 31, 32, 33, an organic insulating film 41 having a thickness of 2.5 to 3.0 mu m made of a negative photosensitive resin is formed. Negative photosensitive resins are prepared by incorporating negative photosensitive agents in resins such as acrylic series, BenzoCycloButane (BCC) and polyimide. In this case, the acrylic resin or BCB is 10W% to 20W%, the negative photosensitive agent is 10W% to 20W%, and the solvent is preferably 60W% to 70W% with respect to the total content of the composition.

As described above, when the organic insulating film 41 is formed of the negative photosensitive resin, the light transmittance can be higher than that of the positive photosensitive resin, whereby high luminance can be achieved. In addition, the entire surface exposure work for increasing the transmittance of the organic insulating film can be omitted.

The gate wirings 50, 52, and 54 having a double layer structure formed on the organic insulating layer 41 include a lower metal layer made of aluminum, such as aluminum or an aluminum alloy, and an upper metal layer made of chromium, molybdenum or molybdenum alloy, chromium nitride, molybdenum nitride, or the like. ) Is formed.

The gate lines 50, 52, and 54 extend in the horizontal direction and are connected to the gate line 50 and the gate line 50 that define the unit pixel by crossing the data line 21 to apply a scan signal from the outside. And a gate pad 52 which receives the transfer to the gate line 50 and a gate electrode 54 of the thin film transistor that is part of the gate line 50.

Here, the gate line 50 overlaps with the pixel electrode 110 to be described later to form a sustain capacitor which improves the charge retention capability of the pixel, and the sustain is generated by the overlap of the pixel electrode 110 and the gate line 50 to be described later. If the capacitance is not sufficient, a common electrode for the storage capacitance may be formed.

The gate insulating film 60 made of silicon nitride is formed on the gate wirings 50, 52, 54 and the organic insulating film 41. At this time, the gate insulating film 60 is advantageously deposited at a low temperature in order to prevent damage caused by the high temperature of the color filters 31, 32, 33 formed under the substrate. In the case where the gate insulating film 60 is formed by high temperature deposition, which is a conventional method, it is advantageous to make the color filters 31, 32, 33 formed of a material having a high heat resistance that does not change color characteristics even at high temperatures.

The gate insulating film 60 includes contact holes 62 exposing the gate pads 52 and contact holes 61 and 63 exposing the data line 21 and the data pad 25, respectively, together with the organic insulating film 41. Each is formed.

A semiconductor pattern 71 made of a semiconductor material such as hydrogenated amorphous silicon is formed in an island shape on the gate insulating layer 60 on the gate electrode 54. On the semiconductor pattern 71, ohmic contact layers 81 and 83 made of a semiconductor material doped with impurities, such as amorphous silicon doped with a high concentration of n-type impurities, are formed.

Source and drain electrodes 112 and 111 made of ITO or IZO are formed on the contact layers 81 and 83, respectively. The source electrode 112 is connected to the data line 21 through the contact hole 61 formed in the gate insulating film 60 and the organic insulating film 41. The drain electrode 111 is connected to a pixel electrode 110 that receives an image signal from the thin film transistor and generates an electric field together with the electrode of the upper plate. The pixel electrode 110 is made of a transparent conductive material such as ITO or IZO, and is integrally formed with the drain electrode 111.

The organic insulating layer 41 made of an organic insulating material having a low dielectric constant, such as a negative photosensitive resin, is formed between the pixel electrode 110 and the data line 21. Thus, the parasitic capacitance caused by the overlap between the pixel electrode 110 and the data line 21 is sufficiently small. Accordingly, the pixel electrode 110 may overlap the data line 21, thereby reducing the width of the black matrix covering the light leakage region between the pixel electrode 110 and the data line 21. This has the advantage of increasing the aperture ratio.

In addition, the auxiliary gate pad 113 and the auxiliary data pad 115, which are connected to the gate pad 52 and the data pad 25 through the contact holes 62 and 63, are formed in the same layer as the pixel electrode 110. Formed.

A passivation layer pattern 120 is formed on the source electrode 112 and the drain electrode 111 to protect the semiconductor pattern 71. A color organic layer 130 having a dark color having excellent light absorption is formed thereon. Formed. At this time, the colored organic layer 130 serves to block light incident on the semiconductor pattern 71 of the thin film transistor, and adjusts the height of the colored organic layer 130 to face the lower insulating substrate 100. It is used as a gap retaining material having a function of maintaining the gap between the insulating substrate 200. Here, the passivation layer pattern 120 and the colored organic layer 130 may be formed along the gate line 50 and the data line 21. In this case, leakage occurs around the gate line 50 and the data line 21. It also has the function of a black matrix, which serves to block out light.

In this case, when the colored organic layer 130 is patterned to cover the gap between the pixel electrode 110 and the gate line 50, it is not necessary to design a separate black matrix for light blocking on the upper substrate. There is an advantage.

This will be described with reference to FIG. 22.

As shown in FIG. 22, when the gate line 50 and the pixel electrode 110 are formed at predetermined intervals, it is necessary to cover the light leaking portion between the pixel electrode 110 and the gate line 50. There is. To this end, a portion of the data line 21 formed under the color filters 31, 32, and 33 extends to protrude in the direction of the gate line 50, but there is a gap between the gate line 50 and the pixel electrode 110. Form to cover up. At this time, the colored organic layer 130 covers the portion that cannot be covered by the data line 21, that is, the gap between two adjacent data lines 21.

On the other hand, although not shown in the drawing, a black matrix for blocking light leaking around the edge of the screen display with a material for forming the gate wirings 50, 52, and 54 on the same layer as the gate wirings 50, 52, and 54. The vertical portion of the black matrix is formed on the same layer as the data lines 21, 23, and 25 to block light leaking around the edge of the screen display with a metal material for forming the data lines 21, 23, and 25. An addition can be formed.

As such, the horizontal and vertical portions of the black matrix are formed of a material forming the gate lines 50, 52, 54 and the data lines 21, 23, 25 to block light leaking around the edges of the screen display. The light leakage region between the gate line 50 and the pixel electrode 110 is covered by the data wirings 21, 23, and 25, and the light leakage between the two data wirings 50 adjacent to the colored organic film 130 is leaked. In the case of covering the region, the data wiring, the gate wiring and the spacer may cover all the areas where light leaks from the thin film transistor substrate, so that a separate black matrix does not need to be formed on the upper substrate. Therefore, it is not necessary to consider the alignment error between the upper substrate and the lower substrate can improve the aperture ratio. In addition, the gate insulating film 60 and the organic insulating film 40 having a low dielectric constant are formed between the data line 21 and the pixel electrode 110, so that the coupling capacitance generated between them can be minimized. It is possible to improve the characteristics of, and at the same time there is no need to space between them to ensure the maximum aperture ratio.

Next, a method of manufacturing the thin film transistor substrate according to the third exemplary embodiment of the present invention will be described in detail with reference to FIGS. 23A to 28B.

First, as shown in FIGS. 23A and 23B, a lower metal layer made of aluminum is deposited, and an upper metal layer made of a conductive material having excellent contact properties with ITO is deposited thereon.

Subsequently, the metal layer is etched by a photolithography process using a mask to include a data line 21, a data pad 25, and a light blocking part 23 having a double layer structure of a lower metal layer and an upper metal layer on the insulating substrate 100. The data wirings 21, 23, and 25 are formed.                     

Next, a photosensitive material containing pigments of red (R), green (G), and blue (B) is applied in sequence, exposed and developed by a photo process using a mask, and then red (R), green (G), and blue (B). ), Color filters 31, 32, and 33 are sequentially formed. At this time, the red (R), green (G), and blue (B) color filters 31, 32, and 33 are formed using three masks, but in order to reduce manufacturing costs, one mask is used while moving. It may be formed. In addition, using a laser transfer method or a print method can be formed without using a mask, thereby minimizing the manufacturing cost. In this case, the edges of the color filters 31, 32, and 33 of red (R), green (G), and blue (B) may be formed to overlap the data line 21.

Next, as shown in FIGS. 24A and 24B, a negative photosensitive resin is thickly coated on the data lines 21, 23, 25, and the color filters 31, 32, 33 to form an organic insulating film 41. At this time, the organic insulating film 41 can be applied by the SOG method. And the negative photosensitive resin preferably contains acrylic resin or BCB, 10B% to 20W%, negative photoresist, 10W% to 20W% solvent, 60W% to 70W% solvent relative to the total content of the composition. Do.

Since the organic insulating film 41 in the present invention contains a negative photosensitive agent, the organic insulating layer 41 has a lower absorbance than the positive photosensitive resin containing the positive photosensitive agent, thereby increasing the transmittance of light from the lower part of the substrate.

Subsequently, an upper metal layer is deposited, and an upper metal layer made of aluminum is deposited thereon, and then, by etching using a photolithography process using a mask, the gate line 50, the gate pad 52, and the gate electrode 51 having a double layer structure are etched. To form the gate wiring (50, 52, 54) including.                     

Next, as shown in FIG. 25, the gate insulating film 60, the semiconductor layer 70, and the semiconductor layer doped with impurities are formed on the gate wirings 50, 52, 54 and the organic insulating film 41. 80) are deposited successively.

Next, as shown in FIGS. 26A and 26B, the gate insulating layer 60, the semiconductor layer 70, and the semiconductor layer 80 doped with impurities are etched by a photolithography process using a mask to form an island-shaped semiconductor layer 71. And contact holes 61 and 62 for forming the ohmic contact layer 81 and simultaneously exposing the data line 21, the gate pad 52, and the data pad 25 in the gate insulating film 60 and the organic insulating film 41. 63) respectively.

In order to form this in a photolithography process using one mask, a photoresist pattern having a different thickness is used as an etching mask. This will be described in detail with reference to FIG. 27.

As shown in FIG. 27, after the photoresist film is applied on the impurity doped semiconductor layer 80 to a thickness of 1 μm to 2 μm, the photoresist film is irradiated with light through a photolithography process and then developed. Photosensitive film patterns 312 and 314 are formed.

In this case, the first portion 312 of the photoresist layer disposed on the gate electrode 54 among the photoresist patterns 312 and 314 is thinner than the remaining second portion 314, and the data line 21 and the data pad 25 ) And a portion of the gate pad 52, that is, a portion where the contact hole is to be formed, does not exist. At this time, it is preferable that the thickness of the second portion 314 be 1/2 or less of the thickness of the first portion 312, for example, 4,000 Pa or less.

As such, the photoresist patterns 312 and 314 having partially different thicknesses are formed using one mask having partially different transmittance. In order to control the light transmission, a slit or lattice pattern or a mask with a translucent film is used. In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the photoresist is irradiated with light through such a mask, the polymers are completely decomposed at the portion (C) which is directly exposed to the light, and the polymers are not completely decomposed at the portion (B) corresponding to the slit pattern or the translucent film because the amount of light is small. The polymer is hardly decomposed at the portion A covered by the light shielding film. Subsequently, when the photoresist film is developed, only a portion A of which the polymer molecules are not decomposed remains, and a portion of the light portion irradiated with less light may have a thinner photoresist film than the portion A that is not irradiated with light at all. At this time, if the exposure time is extended, all molecules are decomposed, so be careful not to do so.

Next, using the photoresist patterns 312 and 314 as an etching mask, the contact hole exposing the gate pad 52 by etching the semiconductor layer 80, the semiconductor layer 70, and the gate insulating layer 60 doped with impurities ( 62) is completed, and the organic insulating film 41 of the part corresponding to C area | region is exposed. Subsequently, by using the photoresist patterns 312 and 314 as an etching mask, the contact hole 61 exposing the data line 21 and the data pad 25 by removing the organic insulating film 41 exposed at the portion corresponding to the C region is removed. Complete 63).                     

Subsequently, the photoresist film is removed to a predetermined thickness, that is, to the extent that the second portion 314 of the photoresist film can be completely removed. In this process, only the first portion 312 of the photoresist film is left thin on the semiconductor layer 80 doped with impurities. In this case, an ashing process using oxygen may be added to completely remove the photoresist residue of the second portion 314.

Subsequently, when the first layer 312 of the remaining photoresist pattern is used as an etching mask, the semiconductor layer 80 doped with impurities and the lower semiconductor layer 70 are etched and removed to form an island on the gate insulating layer 60. The semiconductor layer 71 having a shape and the semiconductor layer 81 doped with impurities, that is, the semiconductor pattern 71 and the ohmic contact layer 81 may be formed.

Finally, when the first portion 312 of the remaining photoresist film is removed, a cross-sectional structure as shown in FIG. 26B can be obtained.

Next, as shown in FIGS. 28A and 28B, the source electrode 112, the drain electrode 111, and the drain electrode connected to the data line 21 through the contact hole 61 by depositing and photolithography the ITO layer. A pixel electrode 110 connected to the 111, an auxiliary gate pad 113 connected to the gate pad 52 through the contact hole 62, and an auxiliary device connected to the data pad 25 through the contact hole 63. The data pad 115 is formed. In this case, IZO may be used instead of ITO.

Subsequently, the ohmic contact layer 81 and the drain electrode 113 contacting the source electrode 112 by etching the island-like ohmic contact layer 81 by using the source electrode 112 and the drain electrode 111 as a mask. ) Into an ohmic contact layer 83 in contact therewith.                     

Next, as shown in FIGS. 20 and 21, an insulating material such as silicon nitride or silicon oxide and an insulating material such as a photosensitive organic material containing black pigment are sequentially stacked and exposed and developed by a photo process using a mask. A color organic film 130 is formed, and the protective material 120 is formed by etching the lower insulating material using the colored organic film 130 as an etching mask. In this case, the colored organic layer 130 may block light incident to the thin film transistor, and may be formed on the gate line or the data line to provide a function of blocking light leaking around the wire. In addition, the height of the organic layer 130 may be adjusted to be used as a spacer.

The upper substrate 201 forms a common electrode 210 by stacking a transparent conductive material of ITO or IZO on the upper insulating substrate 200.

As described above, in the thin film transistor substrate according to the third embodiment of the present invention in which the thin film transistor is formed on the color filter, by forming an organic insulating film with a negative photosensitive resin, the light transmittance of the substrate can be increased, and high luminance is ensured. can do.

29 is a layout view of a thin film transistor substrate according to a fourth exemplary embodiment of the present invention, and FIG. 30 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 29 along a cutting line VII- ′ ′.

Gate wirings 22, 24, 26, and 28 formed of a double layer structure of the lower metal layer 201 and the upper metal layer 202 are formed on the insulating substrate 100. The gate wires 22, 24, 26, and 28 are connected to gate lines 22 and gate lines 22 extending in the horizontal direction, and receive the scan signals from the outside and transfer them to the gate lines 22. A gate electrode 22, 24, 26 including the gate electrode 26 of the thin film transistor, which is a part of the pad 24 and the gate line 22, and a common electrode which is parallel to the gate line 22 and input to the common electrode of the upper plate. The sustain electrode 28 receives a voltage such as a voltage from the outside. The storage electrode 28 overlaps the conductor pattern 68 for the storage capacitor connected to the pixel electrode 119 which will be described later to form a storage capacitor that improves the charge storage capability of the pixel.

The gate wirings 22, 24, 26, and 28 may also be formed of a single layer or triple layers.

In the case of forming a double layer, it is preferable that one layer is formed of a material having a low resistance and the other layer is formed of a material having good contact properties with other materials, and a double layer of Cr / Al (or Al alloy) or Al / Mo Bilayers are an example.

The gate insulating film 30 made of silicon nitride covers the gate wirings 22, 24, 26, and 28 on the substrate 100.

A semiconductor pattern 42 made of a semiconductor material such as hydrogenated amorphous silicon is formed on the gate insulating layer 30, and a semiconductor doped with an impurity such as amorphous silicon in which a high concentration of n-type impurities is doped is formed on the semiconductor pattern 42. Ohmic contact layers 55 and 56 made of material are formed.

On the gate insulating layer 30 and the ohmic contact layers 55 and 56, data wires 62, 64, 65, 66, and 68 made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, and Ta are formed. have. The data line 62, 64, 65, 66, 68 includes a data line 62 formed of a data line 62, a data pad 64, a source electrode 65, and a drain electrode 66 formed in a vertical direction. Also included are conductor patterns 68 for sustain capacitors located on 64, 65, 66 and sustain electrodes 28.

The data lines 62, 64, 65, 66, 68 may also be formed in a single layer like the gate lines 22, 24, 26, 28, but may be formed in a double layer or a triple layer. Of course, when forming more than two layers, it is preferable that one layer is formed of a material having low resistance and the other layer is formed of a material having good contact properties with other materials.

The source electrode 65 and the drain electrode 66 are in contact with the ohmic contacts 55 and 56. The ohmic contacts 55 and 56 lower contact resistance between the semiconductor pattern 40, the source electrode 65, and the drain electrode 66.

 An interlayer insulating film 70 made of an insulating material such as silicon oxide or silicon nitride is formed on the exposed front surface of the substrate including the data lines 62, 64, 65, 66, and 68.

On top of the interlayer insulating film 70, red (R), green (G), and blue (B) color filters 81, 82, and 83 are formed. Here, edge portions of the color filters 81, 82, and 83 of red (R), green (G), and blue (B) may be formed to overlap the data line 62.

On top of the blue (R), green (G), and blue (B) color filters (81, 82, 83) and the interlayer insulating film 70, a protective film 90 having a thickness of 2.5 to 3.0 탆 made of a negative photosensitive resin is formed. Formed. Negative photosensitive resins are prepared by incorporating negative photosensitive agents in resins such as acrylic series, BenzoCycloButane (BCC) and polyimide. In this case, the acrylic resin or BCB is 10W% to 20W%, the negative photosensitive agent is 10W% to 20W%, and the solvent is preferably 60W% to 70W% with respect to the total content of the composition.

As described above, when the protective film 90 is formed of the negative photosensitive resin, the light transmittance can be higher than that of the positive photosensitive resin, and high luminance can be achieved. In addition, the entire surface exposure work for increasing the transmittance of the protective film can be omitted.

In the passivation layer 90, together with the color filter 81 and the interlayer insulating film 70, the contact holes 92 and 98, the interlayer insulating film 70, and the gate exposing the drain electrode 66 and the conductive pattern 68 for the storage capacitor are exposed. The contact hole 94 which exposes the gate pad 24 with the insulating film 30 and the contact hole 96 which expose the data pad 64 with the interlayer insulating film 70 are formed, respectively.

On the passivation layer 90, a pixel electrode 119 is formed which receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate. The pixel electrode 119 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and is electrically connected to the drain electrode 66 through a contact hole 92 to receive an image signal. . In addition, the pixel electrode 112 is also connected to the capacitor pattern 68 for the storage capacitor through the contact hole 98 to transmit an image signal to the conductor pattern 68.

In addition, an auxiliary gate pad 113 and an auxiliary data pad 115 connected to the gate pad 24 and the data pad 64 through the contact holes 94 and 96 are formed on the passivation layer 90, respectively. .

On the other hand, between the pixel electrode 119 and the data line 62, a thick protective film 90 made of an organic insulating material having a low dielectric constant, such as a negative photosensitive resin, is formed. Therefore, even if the pixel electrode 119 and the data line 62 overlap, the parasitic capacitance caused by this is small. Accordingly, the pixel electrode 119 may be formed to overlap the data line 62. In this case, the width of the black matrix covering the light leakage region between the pixel electrode 119 and the data line 62 may be determined. It can be reduced, there is an advantage that can increase the aperture ratio.

Next, a method of manufacturing a substrate for a liquid crystal display according to a fourth exemplary embodiment of the present invention will be described in detail with reference to FIGS. 29, 30, and 31A through 34B.

First, as shown in FIGS. 31A and 31B, the lower layer 201 and the upper layer 202 are sequentially stacked by sputtering a conductive layer such as a metal, and the substrate 100 is formed by a photolithography process using a mask. Gate wirings 22, 24, 26, and 28 including a gate line 22, a gate pad 24, a gate electrode 26, and a storage electrode 28 having a double layer structure are formed thereon.

Next, the gate insulating layer 30, the semiconductor layer, and the semiconductor layer doped with impurities are continuously deposited, and are etched by a photolithography process using a mask to sequentially etch the semiconductor layer and the semiconductor layer doped with impurities to form island-like semiconductor layers. 42 and the ohmic contact layer 52 are formed.

Next, as shown in FIGS. 32A and 32B, a metal conductive layer is deposited and then etched by a photolithography process using a mask to form a data line 62, a data pad 64, a source electrode 65, and a drain electrode. The data wirings 62, 64, 65, 66, and 68 are formed, including the 66 and the conductor pattern 68 for the storage capacitor.                     

Subsequently, the island-like ohmic contact layer 52 is etched using the source electrode 65 and the drain electrode 66 as a mask to the ohmic contact layer 55 and the drain electrode 66 contacting the source electrode 65. The resistive contact layer 56 is contacted.

Then, an interlayer insulating film 70 is formed by laminating silicon nitride or silicon oxide.

Next, as shown in FIGS. 33A and 33B, the color filter materials including the red, green, and blue pigments are applied to form the red, green, and blue color filters 81, 82, and 83 in order. At this time, the red, green, and blue color filters 81, 82, and 83 minimize printing costs by using a printing method or a laser transfer method.

Subsequently, a protective film 90 is formed by thickly applying a negative photosensitive resin on the color filters 81, 82, 83, and the interlayer insulating film 70. At this time, the protective film 70 may be applied by the SOG method. And the negative photosensitive resin preferably contains acrylic resin or BCB, 10B% to 20W%, negative photoresist, 10W% to 20W% solvent, 60W% to 70W% solvent relative to the total content of the composition. Do. Since the protective film 90 contains a negative photosensitive agent, the protective film 90 may have a lower absorbance than the positive photosensitive resin containing the positive photosensitive agent, thereby increasing the transmittance of light from the lower part of the substrate. In addition, the entire surface exposure work for increasing the transmittance of the substrate can be omitted.

The protective film 90 does not require a separate photoresist pattern because it contains a photoresist. Thus, in order to form the contact holes 92, 94, 96, and 98 in the protective film 90, direct exposure and development operations are performed. After the protective film 90 is selectively exposed and developed, the color filter 81 is exposed through the contact holes 92 and 98, and the interlayer insulating film 70 is exposed through the contact holes 94 and 96.                     

In the process of developing the protective film 90, a NaOH base developer or a KOH base developer may be used. Even when the protective film 70 is patterned using a developer containing such metal ions, the electrical properties of the thin film transistor are not changed. .

Subsequently, the color filter 81, the interlayer insulating film 70, and the gate insulating film 30 exposed through the contact holes 92, 94, 96, and 98 are etched until the metal layer is exposed to expose the drain electrode 66. Complete the contact hole 92, the contact hole 94 revealing the gate pad 24, the contact hole 96 revealing the data pad 64, and the contact hole 98 revealing the conductor pattern 68 for the retention capacitor. do.

Next, as shown in FIGS. 29 and 30, a transparent material layer made of ITO or IZO is deposited and etched by a photolithography process using a mask, and the drain electrodes are formed through the contact holes 92 and 98. An auxiliary gate pad connected to the gate pad 24 and the data pad 64 through the pixel electrode 119 and the contact holes 94 and 96 connected to the conductor pattern 68 for the storage capacitor. 113 and the auxiliary data pad 115.

As described above, in the thin film transistor substrate according to the fourth embodiment of the present invention, in which a color filter is formed on the thin film transistor, a protective film is formed using an organic insulating material such as a negative photosensitive resin, thereby increasing the light transmittance of the substrate. , High brightness can be secured.

As mentioned above, this invention can raise the light transmittance of a board | substrate by employ | adopting the organic insulating film formed from negative photosensitive resin, and can ensure high brightness. In addition, the entire surface exposure work for increasing the transmittance can be omitted, thereby simplifying the process.

Claims (22)

Board, A gate wiring including a gate line and a gate electrode formed on the substrate; A gate insulating film covering the gate wiring, A data line crossing the gate line insulated from the gate line; A thin film transistor including the gate electrode and electrically connected to the gate line and the data line; A pixel electrode electrically connected to the thin film transistor, A thin film transistor substrate comprising an organic insulating film positioned between the pixel electrode and the data line and formed of a resin containing a negative photosensitive agent.  In claim 1, The pixel electrode is formed to overlap the data line. In claim 1, The gate wiring is formed on the substrate, The thin film transistor includes a semiconductor pattern formed on the gate insulating layer, a source electrode protruding from the data line and electrically connected to the semiconductor pattern, and a drain electrode corresponding to the source electrode and electrically connected to the semiconductor pattern. , The organic insulating layer covers the data line and the thin film transistor, A contact hole for exposing the drain electrode is formed in the organic insulating film, And the pixel electrode is connected to the drain electrode through the contact hole. In claim 3, The semiconductor pattern may be formed along the data line, the source electrode and the drain electrode, and may further include a region positioned between the source electrode and the drain electrode. In claim 3, The semiconductor pattern is a thin film transistor substrate formed in an island shape. In claim 1, The data line is formed on the substrate, A color filter formed on the substrate to overlap the data line; The organic insulating layer covers the data line and the color filter, The gate line is formed on the organic insulating layer, The gate insulating film covers the gate line on the organic insulating film, A contact hole for exposing the data line is formed in the organic insulating film and the gate insulating film; The thin film transistor includes a semiconductor pattern formed on the gate insulating layer, a source electrode connected to the data line through the contact hole to contact the semiconductor pattern, and a drain electrode corresponding to the source electrode. , And the pixel electrode is integrally formed with the drain electrode. In claim 6, The thin film transistor substrate of which the source electrode and the drain electrode are formed of ITO or IZO. In claim 7, A protective film covering the thin film transistor, The thin film transistor substrate further comprising a colored organic layer formed on the passivation layer. In claim 8, The data line extends along the gate line to cover a gap between the gate line and the pixel electrode; The colored organic film is formed to cover the gap between the data line and the neighboring data line. In claim 6, The thin film transistor substrate further comprises a light blocking portion formed to overlap the semiconductor pattern on the substrate. In claim 10, The light blocking unit extends from the data line. In claim 1, The gate wiring is formed on the substrate, The thin film transistor includes a semiconductor pattern formed on the gate insulating layer, a source electrode protruding from the data line and electrically connected to the semiconductor pattern, and a drain electrode corresponding to the source electrode and electrically connected to the semiconductor pattern. An insulating film covering the thin film transistor and the gate insulating film, and a color filter formed on the insulating film, The organic insulating layer covers the color filter, A contact hole for exposing the drain electrode is formed in the organic insulating film, the color filter, and the insulating film; And the pixel electrode is connected to the drain electrode through the contact hole. Forming a gate wiring including a gate line and a gate electrode on the substrate, Forming a gate insulating film covering the gate wiring; Forming a semiconductor pattern on the gate insulating layer; Forming a data line including a data line crossing the gate line, a source electrode in contact with the semiconductor pattern, and a drain electrode corresponding to the source electrode and in contact with the semiconductor pattern; Forming an organic insulating film made of a negative photosensitive resin so as to cover the data line and the semiconductor pattern; Forming a contact hole in the organic insulating layer to expose the drain electrode; Forming a pixel electrode connected to the drain electrode through the contact hole on the organic insulating layer. In claim 13, The semiconductor pattern and the data line are formed in a photolithography process using a photoresist pattern having a partially different thickness. The method of claim 14, The photoresist pattern may include a first portion having a first thickness on the upper portion of the data line and a second portion having a second thickness thinner than the first thickness on the upper portion between the source electrode and the drain electrode. Manufacturing method. The method of claim 15, Formation of the semiconductor pattern and the data wiring, Depositing a semiconductor layer and a conductive layer on the gate insulating layer, and then forming the photoresist pattern; Etching the conductive layer using the photoresist pattern as a mask to expose a portion of the semiconductor layer; Removing the exposed portion of the semiconductor layer and the second portion of the photoresist pattern to complete the semiconductor pattern, exposing a portion of the conductive layer between the source electrode and the drain electrode; Removing the exposed portions of the conductive layer to complete the data wiring; Removing a first portion of the photoresist pattern Method of manufacturing a thin film transistor substrate comprising a. The method of claim 14, The photoresist pattern is formed using a photomask including a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region. Forming a data line including a data line on the insulating substrate; Forming a color filter of red, green, and blue on the substrate, Forming an organic insulating film made of a negative photosensitive resin so as to cover the data line and the color filter; Forming a gate line including a gate line and a gate electrode on the insulating layer; Forming a gate insulating film covering the gate wiring; Forming a semiconductor pattern on the gate insulating film and forming a contact hole in the gate insulating film and the insulating film to expose a portion of the data line; Forming a pixel wiring including a source electrode and a drain electrode respectively contacting the semiconductor pattern, and a pixel electrode connected to the drain electrode; Method of manufacturing a thin film transistor substrate comprising a. The method of claim 18, Forming the gate insulating film, the contact hole and the semiconductor pattern, Sequentially depositing a gate insulating film and a semiconductor layer covering the gate wiring; A photoresist pattern including a first portion positioned on a portion corresponding to the gate electrode on the semiconductor layer and a second portion formed thinner than the first portion on a portion other than a portion where the first portion and the contact hole are to be formed; Forming step, Etching the semiconductor layer, the gate insulating film, and the organic insulating film using first and second portions of the photosensitive film as a mask to form the contact hole; Removing the second portion of the photoresist pattern. Etching the semiconductor layer using the first portion of the photoresist pattern as a mask to form the semiconductor pattern; Removing a first portion of the photoresist pattern Method of manufacturing a thin film transistor substrate comprising a. The method of claim 18, And forming the data line to extend the data line and to form a light blocking portion positioned at a portion corresponding to the semiconductor layer pattern. The method of claim 18, The light blocking part is formed to extend to cover the light leakage region between the gate line and the pixel electrode. In claim 13, Before forming the organic insulating film, an insulating film covering the data line and the substrate is formed, and a color filter overlapping the data line is formed on the insulating film, A contact hole exposing the drain electrode is formed in the organic insulating film, the color filter and the insulating film.

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