KR100723875B1 - Microprocessors Suitable for Simultaneous Startup and Reset and Processor ID Control Methods in the Microprocessors - Google Patents

Abstract

A microprocessor suitable for simultaneous startup and a reset and processor ID control method in the microprocessor include: a decoder configured to receive a reset ID and a reset signal having a predetermined binary value and decode and output the reset ID; A processor ID generation unit configured to generate at least one microprocessor ID and a reset ID of a microprocessor connected in series by inputting a decoding result of the decoder; And a reset vector unit for selecting a reset vector based on the decoding result of the decoder, and having a configuration capable of controlling reset and processor IDs in each microprocessor constituting the multiprocessor system. When a reset signal is input to perform initialization, every individual microprocessor in the multiprocessor system generates a unique reset vector and processor ID. The result is that all microprocessors can perform the startup procedure at the same time when the reset signal is released, simplifying the reset procedure in a multiprocessor system and providing the time and ease of system design required for startup of the microprocessor.

Reset vector, reset id, processor id, multiprocessor

Description

Microprocessor suitable for constructing multi-processor system and method for managing reset and processor ID}

1 shows a simplified block diagram of a microprocessor according to the present invention.

2 is a block diagram showing a more detailed configuration of a microprocessor according to the present invention.

3 is a flowchart illustrating a process of resetting a microprocessor and generating a processor ID according to the present invention.

4 shows an example of a multiprocessor system constructed using a microprocessor in accordance with the present invention.

5 shows an extension of a multiprocessor system using a microprocessor in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

100: microprocessor with reset and processor ID generation unit

110,220: Decoder

120: reset vector section

130: ID generation unit

210: processor ID generation unit

230: reset ID (nRID) generation unit

240: reset vector table

250: selection

417,515: Multiprocessor System Bus Arbitrator

413,415,511,513 shared memory shared on multiprocessor system bus

409,411,507,509: Shared I / O devices shared on a multiprocessor system bus

The present invention relates to a microprocessor capable of constructing a multiple microprocessor system by connecting a plurality of microprocessors in series. More particularly, the present invention relates to a unique reset in a reset vector table by receiving reset information received from a front end microprocessor. Select a vector and generate a unique processor ID and a reset ID to be passed to the next microprocessor at the same time to control the microprocessor and the reset and processor ID of the microprocessor, which is suitable for simultaneous start-ups that can form multiple microprocessor systems. It is about.

In a conventional multiprocessor system, the reset and processor ID assignment schemes allow all microprocessors to have the same reset vector, so that each microprocessor uses a complex algorithm outside the processor for the construction of the multiprocessor system. An arbitrator must be used that allows the microprocessor to start up sequentially using the reset vector. In addition, when using a shared system bus, each microprocessor must have a unique processor ID in order to guarantee the use of the bus, which must also mediate access to the system bus using an additional arbiter.

US Patent US 6,314,515 B1 "Resetting Multiple Processors in a Computer System" by Compaq Computer Corporation is a system using two processors (P ₁ , P _Z ) in which a reset signal for initializing the system is provided. P _Z is put on hold using the interprocessor communication module while it is first applied to P ₁ to perform normal startup, and then P _Z is started after P ₁ completes the procedures necessary for system startup. . The patent provides a method of guaranteeing the startup of a processor by placing an interprocessor communication module outside the processor for the startup of two or more processors, while the other processor withholds the reset while one processor performs the startup procedure. This method has to arbitrate startup between processors using complex arbitration circuits and algorithms external to the processor, and only one processor can be started at a time.

Japanese Patent Application No. 11-21068 by 株式會社 東芝 特 開平 11-21068 "Reset software" receives a plurality of reset signals, generates a reset vector, and generates a reset vector. This patent relates to a method for converting a start address in accordance with a reset input at start up. The patent requires a plurality of reset signals and is designed as an alternative startup method to prevent false start of a program due to a hardware failure in a single processor system. The disadvantage is that you must use a group.

Patent 10-0201399 "Reset Interrupt Circuit" by LG Semiconductor Co., Ltd. is a patent for a device for receiving a reset signal and a separate port state input and combining them to select a new reset vector. The patent requires a plurality of port state inputs, and is designed as a method of starting and selecting a type of program that operates according to the state of external hardware in a single processor system, and is similar in form to the US patent for application to a multiprocessor system. The disadvantage is that an external arbitrator must be used.

The technical problem to be solved by the present invention is to solve the above problems, and a plurality of reset vectors are embedded therein, and every individual microprocessor automatically selects a unique reset vector through a connection between microprocessors. And a microprocessor suitable for simultaneous startup and a reset and processor ID of the microprocessor, which generate errors in bus access on a shared system bus and unique processor IDs to ensure unique bus access of individual microprocessors. The present invention provides a computer-readable recording medium that records a method and a program for executing the method on a computer.

In order to achieve the above technical problem, a microprocessor suitable for simultaneous startup according to the present invention comprises: a decoder for receiving a reset ID and a reset signal having a predetermined binary value and decoding the reset ID; A processor ID generation unit configured to generate at least one microprocessor ID and a reset ID of a microprocessor connected in series by inputting a decoding result of the decoder; And a reset vector unit for selecting a reset vector based on the decoding result of the decoder.

More preferably, the reset vector portion of the microprocessor includes: a reset vector table for storing at least one reset vector; And a reset vector selector configured to select a vector corresponding to the reset ID from the reset vector table so that the reset vector is set as a start address after the reset of the processor is completed.

More preferably, the ID generation unit of the microprocessor processor ID generation unit for generating its own microprocessor ID based on the reset ID; And a reset ID generating unit generating a reset ID of a next microprocessor to be connected with the self.

More preferably, the reset ID of the microprocessor is input from a microprocessor of a front end connected in series with the same configuration as the microprocessor.

According to an aspect of the present invention, there is provided a method for resetting a microprocessor and a processor ID control method, the method including: at least one reset vector; Determining an activation state of a received reset signal; When the reset signal is activated, at least one ID is generated by decoding the reset ID according to a predetermined reset ID received from a serially connected microprocessor and an activation state of the reset signal based on the reset signal. Selecting one of the; And maintaining a current ID and a reset vector when the reset signal is inactive.

More preferably, the selecting of the control method may include generating a processor ID indicating its ID; Generating a reset ID to be provided to the next microprocessor in series; Determining whether the reset signal is inactivated, and repeating the above steps if it is in an active state, and maintaining the generated processor ID, reset ID, and reset vector in an inactive state.

In order to achieve the above technical problem, a computer-readable recording medium having recorded thereon a program capable of executing a method of resetting a microprocessor and controlling a processor ID suitable for simultaneous startup according to the present invention includes at least one reset vector. step; Determining an activation state of a received reset signal; When the reset signal is activated, at least one ID is generated by decoding the reset ID according to a predetermined reset ID received from a serially connected microprocessor and an activation state of the reset signal based on the reset signal and generating the reset vector. Selecting one of the; And maintaining a current ID and a reset vector when the reset signal is inactive.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 1 is a block diagram showing a simple configuration of a microprocessor according to the present invention, Figure 2 is a block diagram showing a more detailed configuration of a microprocessor according to the present invention, Figure 3 is a reset and processor of the microprocessor according to the present invention This flowchart shows the process of ID creation related operation. 4 is a view showing an example of a multiprocessor system constructed using a microprocessor according to the present invention, and FIG. 5 is a view showing an extension example of a multiprocessor system using a microprocessor according to the present invention.

First, the configuration of the microprocessor 100 according to the present invention will be briefly described with reference to FIG. 1. The decoder 110 may be divided into three parts. First, the decoder 110 receives a reset ID and a reset signal having a predetermined binary value, decodes the reset ID, and delivers the reset ID to the next blocks. The ID generation unit 130 generates and outputs at least one microprocessor ID and a reset ID of a next stage microprocessor connected in series with the current microprocessor using the decoding result of the decoder as an input. The reset vector unit 120 receives the decoding result of the decoder and selects and outputs a reset vector.

Now, the function of each block shown in FIG. 1 will be described in detail with reference to FIG. 2. The functional blocks shown in FIG. 1 are generally divided into blocks 100 in FIG. 2. Looking at the block 100 in detail, the decoder 220, the reset vector selector 250, the reset vector table 240, the reset ID generator 230 that generates a reset ID of the next processor, and the processor ID generator 210. It is composed. The ID generator 130 of FIG. 1 includes the processor ID generator 210 and the reset ID generator 230 of FIG. 2. The reset vector unit 120 of FIG. 1 includes the selector 250 and the reset vector table 240 of FIG. 2. When m microprocessors 200 are used in a multiprocessor system, the previous reset ID (pRID) is used. And the bit width of the next reset ID (nRID) signal are determined by the rounding value of log ₂ (m). That is, since four microprocessors are used in FIG. 4, the width is 2 bits, which is log ₂ (4). The decoder 220 receives a pRID corresponding to the nRID of the previous microprocessor as an input, decodes it, and outputs it. The decoder 220 transmits the decryption result to the selector 250 and the processor ID generator 210. The selector 250 selects a reset vector corresponding to the selected reset ID from the reset vector table 240, which is a table composed of at least m reset vectors, and transmits the reset vector to the program counter 270 to cancel the program. Set as start address for start. The processor ID generator 210 receives a result of the decoder 220 and generates a unique processor ID (PID). The method for generating a unique processor ID is not limited to the specific method in the present invention. However, in order to generate a unique processor ID, it is preferable to set a reference value of a preset processor ID, and generate a unique processor ID by adding a reset ID value to this value. The generated processor ID is stored in the processor ID register 260 to distinguish it from bus access by other microprocessors in the system by adding a unique processor ID when the microprocessor accesses the system bus via the bus interface device 280. Do it.

The microprocessor suitable for simultaneous startup according to the present invention generates a unique reset vector and a processor ID, and at the same time, generates a reset ID to be used in the next microprocessor serially connected through the reset ID generator 230. The reset ID generation in the reset ID generator 230 is not limited to a specific method in the present invention. A unique reset ID generation method by the reset ID generation unit 230 preferably uses an adder. Each microprocessor 200 configures a reset ID generation unit 230 to have a value of a previous reset ID (pRID) + 1 as each microprocessor is serially connected, starting with an initial reset ID (Initial RID) value. can do. In the example of FIG. 4 to be described later, when the pRID value is increased by 1 using the adder, in the microprocessors 401 to 407, when the initial reset ID value is 0, the reset ID values of 0, 1, 2, and 3 are each microprocessor. Assigned to processors 401-407 in turn.

3 is a flowchart illustrating a process of resetting a microprocessor and generating a processor ID according to the present invention. First, a reset vector table for storing reset vectors as described in FIG. 2 is provided (310). Now, when the system is powered up, each microprocessor examines the reset input (320). If the reset has not yet been applied, the state is set to the initial value (330). If the reset signal is applied, the previous reset ID value inputted as the previous reset ID is decoded (340), and the reset vector, the processor ID, and the next reset ID (nRID) are determined according to the decoding result (350). Next, if the reset signal is not terminated by checking the reset signal (360), the above steps 340 to 350 are repeatedly performed. If the reset signal is terminated, the generated reset vector, the processor ID, and the next reset ID (nRID) are maintained continuously (330) to perform the startup procedure of the microprocessor (200).

As can be seen from Figures 1 to 3, the setting of the reset vector and the determination of the processor ID are all completed before the reset is terminated. Therefore, when the microprocessor according to the present invention forms a multi-microprocessor system as shown in FIGS. 4 to 5, each microprocessor can independently start the microprocessor at the time when the reset is terminated without crashing the system bus. It becomes possible.

4 is a diagram illustrating an example of a multiprocessor system using a microprocessor according to the present invention. Four microprocessors 401, 403, 405, 407 according to the present invention, a system bus 419 shared by these microprocessors, a bus arbiter 417 that arbitrates access to the bus, a shared memory 413 and 415 connected to the system bus, and shared inputs and outputs. It consists of devices 409 and 411. Each microprocessor shown in FIG. 4 is characterized by having a previous microprocessor reset ID (pRID) input, a next reset ID (nRID) output, and a reset signal (reset) input. Each microprocessor connects all microprocessors in series by connecting the next reset ID (nRID) output to the previous reset ID (pRID) input of the next stage of microprocessors. The 401 applies an initial RID for the reset ID to the previous reset ID pRID input. Of the multiple microprocessors in series, the next reset ID (nRID) output of the last microprocessor 407 is left open. All microprocessors are configured in series by concatenating pRIDs and nRIDs. Therefore, each microprocessor acquires reset information according to its position in a serially connected state, and processes the microprocessor and transmits the reset information to the next microprocessor so that a unique reset vector can be set.

5 is an example in which the configuration of FIG. 4 is further expanded. In the same manner as the embodiment of Fig. 4, all the microprocessors 501 to 505 are connected in series using the previous reset ID pRID and the next reset ID nRID signal lines. A system bus 517 shared by these microprocessors, a bus arbiter 515 to arbitrate access to the bus, shared memories 511 and 513 connected to the system bus, and shared input / output devices 507 and 509 are configured.

Each processor 501-505 selects a unique reset vector before the reset signal is terminated, so that after the reset is canceled, all microprocessors in the multiprocessor system start up at the same time.

The reset and processor ID control method in the microprocessor according to the present invention can also be embodied as computer readable code on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, hard disk, floppy disk, flash memory, optical data storage device, and also carrier wave (e.g. transmission over the Internet). It is also included to be implemented in the form of. The computer readable recording medium can also be distributed over computer systems connected over a computer network so that the computer readable code is stored and executed in a distributed fashion. Also, the font ROM data structure according to the present invention can be read by a computer on a recording medium such as a computer readable ROM, RAM, CD-ROM, magnetic tape, hard disk, floppy disk, flash memory, optical data storage device, and the like. It can be implemented as code.

As described above, the present invention has been described based on the preferred embodiments, but these embodiments are intended to illustrate the present invention, not to limit the present invention, and those skilled in the art to which the present invention pertains should be practiced without departing from the technical spirit of the present invention. It will be apparent that various changes, modifications, or adjustments to the examples are possible. Therefore, the protection scope of the present invention will be limited only by the appended claims, and should be construed as including all such changes, modifications or adjustments.

As described above, according to the microprocessor suitable for simultaneous start and the reset and processor ID control method of the microprocessor according to the present invention, the microprocessor constituting the multiprocessor system can control the reset and the processor ID. Thus, when a reset signal is input to perform initialization, every individual microprocessor in the multiprocessor system generates a unique reset vector and processor ID. The result is that all microprocessors can perform the startup procedure at the same time when the reset signal is released, simplifying the reset procedure in a multiprocessor system and providing the time and ease of system design required for startup of the microprocessor.

In addition, by automatically generating a unique processor ID, sharing of system resources using a single system bus can be easily achieved, and the system can be implemented without using an external arbitrator.

In addition, it can be easily applied to embedded systems, and the embedded system can be easily expanded to a multiprocessor system in terms of function and performance.

Claims (12)

A decoder configured to receive a reset ID and a reset signal having a predetermined binary value and decode and output the reset ID; A processor ID generation unit configured to generate at least one microprocessor ID and a reset ID of a microprocessor connected in series by inputting a decoding result of the decoder; And And a reset vector unit for selecting a reset vector based on the decoding result of the decoder. The method of claim 1, wherein the reset vector unit A reset vector table for storing at least one reset vector; And And a reset vector selector configured to select a vector corresponding to the reset ID from the reset vector table so that the reset vector is set as a start address after the reset of the processor is completed. Processor. According to claim 1, wherein the ID generating unit A processor ID generator configured to generate a microprocessor ID of the microprocessor ID based on the reset ID; And And a reset ID generator for generating a reset ID of a next microprocessor to be connected with the microprocessor. The method of claim 1, wherein the reset ID is A microprocessor suitable for simultaneous startup, characterized in that the input is received from a microprocessor of the front end connected in series with the same configuration as the microprocessor. The processor ID generator of claim 3, wherein the processor ID generator And performing a predetermined mathematical process including arithmetic operations on the value representing the reset ID to generate a reset ID of the next processor. The method of claim 3, wherein the reset ID generating unit And generating a reset ID of the next processor by performing a predetermined mathematical process including arithmetic operations on the value indicated by the reset ID. The method of claim 1, wherein the reset ID is When n is the number of microprocessors connected in series,

A microprocessor suitable for simultaneous start up, characterized in that it has a rounded value of. The method of claim 1, wherein the microprocessor And the reset signal is deactivated and started simultaneously with other microprocessors connected in series with the same configuration as the microprocessor. (a) having at least one reset vector; (b) determining an activation state of the received reset signal; (c) if the reset signal is activated, generates at least one ID by decoding the reset ID according to a predetermined reset ID received from a serially connected microprocessor and an activation state of the reset signal based on the reset signal; Selecting one of the reset vectors; And and (d) maintaining the current ID and reset vector if the reset signal is inactive. The method of claim 9, wherein step (c) (c1) generating a processor ID indicating its ID; (c2) generating a reset ID to be provided to the next microprocessor in series; (c3) determining whether the reset signal is inactivated, transitioning to step (c1) if it is in an active state, and maintaining the generated processor ID, reset ID, and reset vector in an inactive state; Microprocessor reset and processor ID control method for simultaneous startup. The method of claim 10, wherein step (c2) And performing a predetermined mathematical process including arithmetic operations on the value of the reset ID to generate a reset ID to be provided to the next microprocessor. (a) having at least one reset vector; (b) determining an activation state of the received reset signal; (c) if the reset signal is activated, generates at least one ID by decoding the reset ID according to a predetermined reset ID received from a serially connected microprocessor and an activation state of the reset signal based on the reset signal; Selecting one of the reset vectors; And (d) if the reset signal is inactive, maintaining a current ID and a reset vector; a program capable of executing a method of resetting the microprocessor and controlling the processor ID in a computer suitable for simultaneous starting; Recordable computer-readable recording media.

Images