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KR100739099B1 - Epitaxial Wafers and Manufacturing Method Thereof - Google Patents

Epitaxial Wafers and Manufacturing Method Thereof

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KR100739099B1
KR100739099B1 KR1020050127359A KR20050127359A KR100739099B1 KR 100739099 B1 KR100739099 B1 KR 100739099B1 KR 1020050127359 A KR1020050127359 A KR 1020050127359A KR 20050127359 A KR20050127359 A KR 20050127359A KR 100739099 B1 KR100739099 B1 KR 100739099B1
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layer
sio
wafer
refractive index
epitaxial
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KR20070066329A (en
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구영수
김재선
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주식회사 실트론
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

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  • General Physics & Mathematics (AREA)
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  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 에피택셜 웨이퍼의 자동도핑 방지용 SiO2 배면실층을 플라즈마 강화 CVD로 형성하는 방법에 관한 것이다. 본 발명에 따르면, 플라즈마 강화 CVD법을 사용하여 웨이퍼 배면에 굴절률이 다른 제 1 SiO2층과 제 2 SiO2층을 형성함으로써 불순물의 자동도핑에 의한 휨현상과 EPI 헤이즈라는 두가지 문제점을 해결할 수 있다. The present invention relates to a method of forming an SiO 2 backside seal layer for the anti-doping of epitaxial wafers by plasma enhanced CVD. According to the present invention, by using the plasma enhanced CVD method, the first SiO 2 layer and the second SiO 2 layer having different refractive indices are formed on the back surface of the wafer, thereby solving two problems such as warping phenomenon due to auto doping of impurities and EPI haze.

굴절율, 1.46, 플라즈마 강화 CVD, 자동도핑, 배면실층 Refractive Index, 1.46, Plasma Enhanced CVD, Auto Doping, Back Seal Layer

Description

에피택셜 웨이퍼 및 그 제조방법{EPITAXIAL WAFER AND MAUFACTURING METHOD THEREOF}Epitaxial wafer and its manufacturing method {EPITAXIAL WAFER AND MAUFACTURING METHOD THEREOF}

도 1은 굴절율에 따른 EPI 헤이즈 발생 구간을 나타내는 그래프,1 is a graph showing the EPI haze generation interval according to the refractive index,

도 2는 PECVD 방법에 따라 배면실층이 형성된 웨이퍼의 굴절율 1. 46 이상 및 이하인 경우 EPI 헤이즈의 상태를 도시한 도면,2 is a view showing the state of the EPI haze when the refractive index of 1.46 or more and less than the wafer of the back chamber layer formed by the PECVD method,

도 3a 및 도 3b는 각각 웨이퍼의 굴절율과 웨이퍼의 델타 워피지(Delta Warpage) 현상과 델타 보우(Delta Bow) 현상의 관계를 나타내는 그래프,3A and 3B are graphs showing the relationship between the refractive index of the wafer, the Delta Warpage phenomenon, and the Delta Bow phenomenon of the wafer,

도 4는 본 발명의 일 실시예에 따른 배면실층이 2층으로 형성된 에피택셜 웨이퍼의 단면도. 4 is a cross-sectional view of an epitaxial wafer having a backside seal layer formed of two layers according to an embodiment of the present invention.

본 발명은 플라즈마 강화 화학증착법(Plasma enhanced chemical vapour doposition; PECVD)를 이용하여 에피택셜 웨이퍼 배면에 2층의 배면실층(backside seal layer)을 갖는 에피택셜 웨이퍼 및 그 제조방법에 관한 것이다.The present invention relates to an epitaxial wafer having a backside seal layer of two layers on the back surface of the epitaxial wafer using plasma enhanced chemical vapor deposition (PECVD), and a method of manufacturing the same.

일반적으로 에피택셜 웨이퍼를 형성하기 위해서 웨이퍼 상에 실리콘층을 고온 성장하는 동안 실리콘 웨이퍼의 배면을 통해 안티몬, 붕소, 인과 같은 도펀트 원자들이 확산된다. 즉, 배면으로부터 확산되는 도펀트 분자들은 웨이퍼의 전면에 성장하는 에피택셜층에 합체되어 오염시킬 수 있으며 웨이퍼 에지 근처의 저항 균일성을 저하시킨다. 이러한 현상을 자동도핑(autodoping)이라 하는데, 이러한 현상은 웨이퍼의 에지에서 가장 두드러지게 나타난다. 이것은 에피택셜 도펀트 프로파일의 불균질성을 유발하며, 웨이퍼의 휨을 야기시킨다.In general, dopant atoms such as antimony, boron and phosphorus diffuse through the backside of the silicon wafer during the high temperature growth of the silicon layer on the wafer to form an epitaxial wafer. That is, dopant molecules diffused from the backside can coalesce and contaminate the epitaxial layer growing on the front side of the wafer and degrade resistance uniformity near the wafer edge. This phenomenon is called autodoping, which is most noticeable at the edge of the wafer. This causes heterogeneity of the epitaxial dopant profile and causes warpage of the wafer.

이러한 자동도핑 효과를 감소시키기 위해서 웨이퍼 배면을 밀봉시킬 수 있는 SiO2 배면실층이 개발되었다.In order to reduce this autodoping effect, a SiO 2 backside layer has been developed that can seal the wafer backside.

이러한 SiO2 배면실층은 대기압 어플리케이션과 저압 어플리케이션 화학증착 방법 등을 이용하여 형성하였다. The SiO 2 back chamber layer was formed using an atmospheric pressure application and a low pressure application chemical vapor deposition method.

최근에 300℃ 이하의 낮은 온도에서 증착가능하며 증착 속도가 크기 때문에Recently, it is possible to deposit at low temperature below 300 ℃ and because of the high deposition rate

PE CVD(Plasma Enhanced CVD) 방법을 이용하여 배면실층을 형성하는 방법이 연구되고 있다. 그러나 PE CVD(Plasma Enhanced CVD) 방법을 이용하여 배면실층을 형성하면, PE CVD의 플라즈마 데미지와 SiO2 필름 특성으로 웨이퍼가 휘어지는 휨현상(Warpage)이 악화되거나, 에피택셜 증착 공정 중에 배면실층으로부터 불순물의 표면전이가 일어나 웨이퍼 에지 부위에서 광산란, 즉 EPI 헤이즈(Haze)가 발생한다. A method of forming a back seal layer by using PE CVD (Plasma Enhanced CVD) has been studied. However, if the back chamber layer is formed by using PE CVD (Plasma Enhanced CVD) method, the warpage of the wafer is deteriorated due to the plasma damage and SiO 2 film characteristics of the PE CVD, or the impurities from the back chamber layer during the epitaxial deposition process are deteriorated. Surface transitions occur and light scattering, or EPI Haze, occurs at the wafer edge.

또한, 고품질의 반도체 웨이퍼에 있어서는 이 EPI 헤이즈는 낮거나 전혀 없어야 한다. In addition, for high quality semiconductor wafers, this EPI haze should be low or absent.

본 발명은 이러한 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 웨이퍼의 휨 현상과 EPI 헤이즈에 상관없이 플라즈마 강화 화학 증착법을 이용하여 웨이퍼 상에 배면실층을 형성할 수 있는 방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a method for forming a back seal layer on a wafer using plasma enhanced chemical vapor deposition regardless of warpage of the wafer and EPI haze. .

또한, 본 발명의 목적은 자동도핑에 의해 실질적으로 영향을 받지 않는 에피택셜 웨이퍼를 제공하는 것이다.It is also an object of the present invention to provide an epitaxial wafer that is substantially unaffected by autodoping.

또한, 본 발명의 목적은 휨 현상이 없고 헤이즈가 없는 에피택셜 웨이퍼를 제공하는 것이다.It is also an object of the present invention to provide an epitaxial wafer free from warpage and no haze.

본 발명의 일 측면에 따르면, 본 발명의 일 실시예에 따른 플라즈마 강화 CVD법을 사용하여 웨이퍼 배면에 자동방지용 2층 배면실층을 형성하는 방법은 상기 2층 배면실층으로 웨이퍼 배면에 굴절률이 다른 제 1 SiO2층과 제 2 SiO2층을 형성한다.According to an aspect of the present invention, a method of forming a two-layer backside seal layer for self-prevention on the back of a wafer by using a plasma enhanced CVD method according to an embodiment of the present invention is a second layer backside seal layer having a different refractive index on the back of the wafer One SiO 2 layer and a second SiO 2 layer are formed.

상기 제 1 SiO2층은 웨이퍼 실리콘과 접촉하여 형성하며, 상기 제 1 SiO2층 상에 연속하여 상기 제 2 SiO2층이 형성된다. 상기 제 1 SiO2층이 상기 제 2 SiO2층보다 굴절귤이 큰 것이 바람직하다. 보다 바람직하게는 상기 제 1 SiO2층의 굴절율은 1.46 이상이고, 상기 제 2 SiO2층의 굴절율은 1.46 이하일 수도 있다.1 wherein the SiO 2 layer is formed in contact with the silicon wafer, subsequent to the claim 1 wherein the SiO 2 layer wherein the second SiO 2 layer is formed. To claim 1 wherein the SiO 2 layer is greater than the refractive tangerine claim 2 SiO 2 layer. More preferably, the refractive index of the first SiO 2 layer is 1.46 or more, and the refractive index of the second SiO 2 layer may be 1.46 or less.

상기 제 2 SiO2층은 산소 운반가스로 N2O 및 실리콘 운반가스로 SiH4를 사용하며, 이들은 SiH4 : N2O = 100sccm : 2200sccm = 1: 22인 관계를 만족하며, 노내 압력을 챔버 압력으로 4.5Torr, RF 파워는 300W를 적용하며, 상기 제 1 SiO2층은 SiH4 : N2O = 100sccm : 1800sccm = 1: 18인 관계를 만족하며, 노내 압력을 챔버 압력으로 4.0Torr, RF 파워 300W를 적용할 수도 있다.The second SiO 2 layer uses N 2 O as the oxygen carrier gas and SiH 4 as the silicon carrier gas, which satisfies the relationship of SiH 4 : N 2 O = 100 sccm: 2200 sccm = 1: 22, and the chamber pressure is applied to the chamber. Apply 4.5 Torr pressure and 300W RF power, the first SiO 2 layer satisfies the relationship of SiH 4 : N 2 O = 100 sccm: 1800 sccm = 1: 18, the furnace pressure is 4.0 Torr, RF You can also apply 300W of power.

본 발명의 다른 측면에 따르면, 에피택셜 웨이퍼는 자동도핑을 방지하기 위해서 웨이퍼 배면에 굴절률이 다른 제 1 SiO2층과 제 2 SiO2층을 갖는다.According to another aspect of the present invention, the epitaxial wafer has a first SiO 2 layer and a second SiO 2 layer having different refractive indices on the back surface of the wafer to prevent autodoping.

상기 제 1 SiO2층은 웨이퍼 실리콘과 접촉하여 형성되며, 상기 제 1 SiO2층 상에 연속하여 상기 제 2 SiO2층이 형성되며, 상기 제 1 SiO2층이 상기 제 2 SiO2층보다 굴절귤이 크며, 상기 제 2 SiO2층의 굴절율은 1.46 이하일 수도 있다. The first SiO 2 layer is formed in contact with the silicon wafer, the first SiO 2 layer in succession on the first 2 SiO 2 layer is formed, the first refractive SiO 2 layer is greater than the first 2 SiO 2 layer The tangerine is large, and the refractive index of the second SiO 2 layer may be 1.46 or less.

이하 도면을 참조하여 본 발명의 일 실시예에 대하여 상세히 설명하겠다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

도 1은 굴절율에 따른 EPI 헤이즈 발생 구간을 나타내는 그래프이며, 도 2는 PECVD 방법에 따라 배면층이 형성된 웨이퍼의 굴절율 1. 46 이상 및 이하인 경우 에지 헤이즈의 상태를 도시한 도면이며, 도 3a 및 도 3b는 각각 웨이퍼의 굴절율과 웨이퍼의 델타 워피지 현상과 델타 보우 현상의 관계를 도시한 그래프이다.1 is a graph showing the EPI haze generation interval according to the refractive index, Figure 2 is a view showing the state of the edge haze when the refractive index of 1.46 or more of the wafer having the back layer formed by the PECVD method, Figure 3a and FIG. 3b is a graph showing the relationship between the refractive index of the wafer, the delta warpage phenomenon and the delta bow phenomenon of the wafer, respectively.

도 1 및 도 2를 참조하면, 플라즈마 강화 CVD를 이용하여 웨이퍼 배면에 SiO2 배면실층을 형성하여 굴절율 RI(Refractive Index)을 측정하면, 상기 굴절율 RI 값이 1.46 이상일 경우 웨이퍼의 휨 현상이 작게 나타나지만, 에피택셜 공정에서 헤이즈를 유발하는 현상이 나타난다는 것을 알 수 있다.1 and 2, when the refractive index RI (Refractive Index) is measured by forming a SiO 2 backside layer on the back surface of the wafer using plasma enhanced CVD, the warpage of the wafer is small when the refractive index RI is 1.46 or more. In addition, it can be seen that the phenomenon causing haze occurs in the epitaxial process.

이는 굴절율이 1.46 이상일 경우 SiO2 층은 상당히 성긴 층으로 성장하기 때 문에 에피택셜층을 입히기 전 상태에서 거치는 클리닝 공정으로부터 상당히 많은 양의 불순물들을 상기 SiO2 층에 함유하게 되기 때문이다.This is because when the refractive index is 1.46 or higher, the SiO 2 layer grows into a fairly coarse layer, and thus contains a considerable amount of impurities in the SiO 2 layer from the cleaning process which is carried out before the epitaxial layer is coated.

이 불순물(특히 H2O)들이 에피택셜 공정의 고온(1000℃ 이상)에서 배면으로부터 확산되어 웨이퍼의 전면에 에피택셜층(EPI) 헤이즈를 유발하는 원인이 된다.These impurities (especially H 2 O) diffuse from the back at the high temperature of the epitaxial process (more than 1000 DEG C), causing the epitaxial layer (EPI) haze on the entire surface of the wafer.

이 EPI 헤이즈를 제어하기 위해 RI 값이 1.46보다 낮은 SiO2 층을 만들게 되면, 도 3a 및 도 3b에 도시된 바와 같이 EPI 헤이즈는 발생하지 않으나 웨이퍼 휨 현상이 발생하여 워피지가 악화되는 현상이 발생하였다.When the SiO 2 layer having the RI value lower than 1.46 is formed to control the EPI haze, as shown in FIGS. 3A and 3B, the EPI haze does not occur, but the warpage occurs and the warpage deteriorates. It was.

따라서 SiO층이 한가지 굴절률만을 갖도록 하면, 워피지와 EPI 헤이즈라는 두가지 문제점을 모두 해결할 수 없다는 것을 알 수 있다.Therefore, it can be seen that if the SiO layer has only one refractive index, both problems of warpage and EPI haze cannot be solved.

PE CVD 방법은 통상 희석용으로 N2, 산소 운반가스로 N2O 및 실리콘 운반가스로 SiH4를 사용한다. 플라즈마 상에서 이들 화합물은 각각의 이온 성분으로 해리되며 보다 이동성인 전자가 반응 챔버와 결부된 고출력의 고주파 RF에 의해서 가속되어 플라즈마를 타격한다. 플라즈마 내의 양이온과, 접지된 히터 블록 상에 놓인 웨이퍼 사이에 작은 네카티브 전위가 존재한다. 이 전위차는 이온을 웨이퍼 표면 방향으로 가속시켜 웨이피 표면에서 이온은 실리콘 이산화물인 SiO2층을 형성한다.PE CVD methods typically use N 2 for dilution, N 2 O for oxygen carrier gas and SiH 4 for silicon carrier gas. On the plasma these compounds dissociate into their respective ionic components and more mobile electrons are accelerated by the high power high frequency RF associated with the reaction chamber to strike the plasma. There is a small negative potential between the cations in the plasma and the wafer lying on the grounded heater block. This potential difference accelerates ions toward the wafer surface, forming a SiO 2 layer where the ions are silicon dioxide on the wafer surface.

한편, 고주파 RF 파워는 전자를 가속화함으로써 플라즈마를 타격하는 데 이용되는 반면, 저주파 RF 파워는 형성하고자 하는 층의 고밀도화를 강화하는데 이용할 수도 있다. 이는 저주파 RF 파워가 더 많은 이온을 더 긴 시간 동안 이동하도 록 유지하기 때문이다.On the other hand, high frequency RF power is used to strike the plasma by accelerating electrons, while low frequency RF power may be used to enhance the density of the layer to be formed. This is because low frequency RF power keeps more ions moving for longer periods of time.

본 발명의 일 실시예에 따르면 PE CVD를 이용하여 내층은 높은 굴절을 가지고 외층은 낮은 굴절율을 갖는 SiO2 2층층을 갖는 웨이퍼가 형성된다. 상기 도 1 내지 도 3b에서 알 수 있는 바와 같이 내층의 굴절율은 일반적으로 1.46 이상이고 외층의 굴절율은 일반적으로 1.46 미만이다. 따라서 내층은 웨이퍼의 EPI 헤이즈 및 웨이퍼의 기하하적인 형태를 제어할 수 있으며, 외층은 EPI 헤이즈(Haze)를 제어할 수 있다.According to an embodiment of the present invention, a wafer having a SiO 2 two-layer layer having a high refractive index and an outer layer having a low refractive index is formed using PE CVD. As can be seen in Figures 1 to 3b the refractive index of the inner layer is generally 1.46 or more and the refractive index of the outer layer is generally less than 1.46. Thus, the inner layer can control the EPI haze of the wafer and the geometry of the wafer, and the outer layer can control the EPI haze.

이제 2층의 SiO2 배면실층을 갖는 웨이퍼를 제조하기 위한 일련의 공정을 살펴본다.We now look at a series of processes for fabricating a wafer with two SiO 2 backside layers.

먼저 여러 실험에 의하면, 굴절율(RI)이 PE CVD 공정에 사용된 구성 가스의 비에 의존하므로, 굴절율(RI)이 1.46인 웨이퍼는 PE CVD 장치의 압력, 시간, 온도, RF 파워, N2, N2O SiH4 등을 소정의 조건으로 설정함으로써 형성한다. First, according to several experiments, since the refractive index (RI) is dependent on the ratio of the constituent gases used in the PE CVD process, wafers with a refractive index (RI) of 1.46 may be used for the pressure, time, temperature, RF power, N 2 , forms, such as by setting the N 2 O SiH 4 at a predetermined condition.

굴절율(RI)이 1.46 이상 예를 들면 굴절율(RI)이 1.48인 경우에는 구성 가스비가 SiH4 : N2O = 100sccm : 1800sccm = 1: 18를 만족하고, 챔버 압력이 4.0Torr, RF 파워가 300W가 되도록 설정할 수도 있다.When the refractive index (RI) is 1.46 or more, for example, the refractive index (RI) is 1.48, the constituent gas ratio satisfies SiH 4 : N 2 O = 100 sccm: 1800 sccm = 1: 18, the chamber pressure is 4.0 Torr, and the RF power is 300 W. It can also be set to

굴절율(RI)이 1.46 이하 예를 들면 굴절율(RI)이 1.45인 경우 구성 가스비가 SiH4 : N2O = 100sccm : 2200sccm = 1: 22를 만족하고, 챔버 압력이 4.5Torr, RF 파워가 300W가 되도록 설정할 수도 있다.When the refractive index (RI) is 1.46 or less, for example, when the refractive index (RI) is 1.45, the constituent gas ratio satisfies SiH 4 : N 2 O = 100 sccm: 2200 sccm = 1: 22, the chamber pressure is 4.5 Torr, and the RF power is 300 W. It can also be set.

도 4는 본 발명에 따른 2층 배면실층을 갖는 에피택셜 웨이퍼의 단면도이다.4 is a cross-sectional view of an epitaxial wafer having a two-layer backside seal layer in accordance with the present invention.

도 4에 도시한 바와 같이, 웨이퍼의 기판(1)의 전면에는 소자가 형성될 에피택셜층(2)이 형성되며, 웨이퍼 기판의 배면에는 웨이퍼 실리콘과 접촉하며 굴절율(RI)이 1.46 이상인 제 1 SiO2 배면실층(3)이 형성된다. 상기 제 1 SiO2 배면실층(3)은 웨이퍼의 휨을 최소화하는 역할을 하게 된다. 결국에 EPI 헤이즈 발생을 막는 역할을 하게 된다. 한편, 상기 제 1 SiO2 배면실층(3)상에는 상기 제 1 SiO2 배면실층(3)보다 굴절율이 작은, 바람직하게는 1.46 이하의 굴절율을 갖는 제 2 SiO2 배면실층(4)이 형성된다. 상기 제 1 SiO2 배면실층(4)는 SiO2층의 불순물 함유를 최소화하게 하여 EPI 헤이즈 발생을 막는 역할을 하게 된다. As shown in FIG. 4, an epitaxial layer 2 on which a device is to be formed is formed on a front surface of a substrate 1 of a wafer, and a first surface having a refractive index RI of 1.46 or more on the back surface of the wafer substrate is in contact with wafer silicon. SiO 2 backing chamber layer 3 is formed. The first SiO 2 backside seal layer 3 serves to minimize warpage of the wafer. Eventually, it plays a role in preventing EPI haze. On the other hand, wherein 1 SiO 2 rear seal layer (3) formed on the first 1 SiO 2 rear seal layer (3) of claim 2 SiO 2 rear seal layer 4, the refractive index has a small, preferably a refractive index of less than 1.46 is formed more. The first SiO 2 back chamber layer 4 serves to prevent the occurrence of EPI haze by minimizing the impurity content of the SiO 2 layer.

본 발명은 웨이퍼의 휨현상과 EPI 헤이즈에 상관없이 플라즈마 강화 화학 증착법을 이용하여 웨이퍼상에 배면층을 형성할 수 있는 방법을 제공할 수 있다.The present invention can provide a method for forming a back layer on a wafer using plasma enhanced chemical vapor deposition regardless of warpage of the wafer and EPI haze.

또한, 본 발명은 자동도핑에 의해 실질적으로 영향을 받지 않는 에피택셜 웨이퍼를 제공할 수 있다.In addition, the present invention can provide an epitaxial wafer that is substantially unaffected by autodoping.

또한, 본 발명은 EPI 헤이즈가 낮거나 없는 단결정 실리콘 웨이퍼를 제공할 수 있다.In addition, the present invention can provide single crystal silicon wafers with low or no EPI haze.

Claims (10)

플라즈마 강화 CVD법을 사용하여 웨이퍼 배면에 자동방지용 2층 배면실층을 형성하는 방법에 있어서,In the method of forming a two-layer back seal layer for automatic prevention on the back of the wafer by using a plasma enhanced CVD method, 상기 2층 배면실층은 웨이퍼 배면에 굴절률이 다른 제 1 SiO2층과 제 2 SiO2층을 포함하는 에피택셜 웨이퍼의 제조방법. And the two-layer backside seal layer comprises a first SiO 2 layer and a second SiO 2 layer having different refractive indices on the back surface of the wafer. 제 1 항에 있어서,The method of claim 1, 상기 제 1 SiO2층은 웨이퍼 실리콘과 접촉하여 형성되며, 상기 제 1 SiO2층 상에 연속하여 상기 제 2 SiO2층이 형성되고 상기 제 1 SiO2층이 상기 제 2 SiO2층보다 굴절률이 큰 에피택셜 웨이퍼의 제조방법. Is formed by the first SiO 2 layer is in contact with the silicon wafer, the first in series on the SiO 2 layer is the first 2 SiO 2 layer is formed in the first SiO 2 layer having a refractive index than the first 2 SiO 2 layer Method for producing large epitaxial wafers. 제 2 항에 있어서,The method of claim 2, 상기 제 1 SiO2층의 굴절률은 1.46 이상인 에피택셜 웨이퍼의 제조방법.And a refractive index of the first SiO 2 layer is 1.46 or greater. 제 2 항에 있어서,The method of claim 2, 상기 제 2 SiO2층의 굴절률은 1.46 이하인 에피택셜 웨이퍼의 제조방법.And a refractive index of the second SiO 2 layer is 1.46 or less. 제 1 항에 있어서,The method of claim 1, 상기 제 2 SiO2층은 산소 운반가스로 N2O 및 실리콘 운반가스로 SiH4를 사용하며, 이들 구성가스비가 SiH4 : N2O = 100sccm : 2200sccm = 1: 22 인 관계를 만족하며, 챔버 압력이 4.5Torr이며, RF 파워가 300W로 설정되는 에피택셜 웨이퍼의 제조방법.The second SiO 2 layer uses N 2 O as the oxygen carrier gas and SiH 4 as the silicon carrier gas, and the composition gas ratio satisfies the relationship of SiH 4 : N 2 O = 100 sccm: 2200 sccm = 1: 22, and the chamber A method of manufacturing an epitaxial wafer in which the pressure is 4.5 Torr and the RF power is set to 300W. 제 1 항에 있어서,The method of claim 1, 상기 제 1 SiO2층은 산소 운반가스로 N2O 및 실리콘 운반가스로 SiH4를 사용하며, 이들 구성가스비가 SiH4 : N2O = 100sccm : 1800sccm = 1: 18인 관계를 만족하며, 챔버 압력이 4Torr이며, RF 파워가 300W로 설정되는 에피택셜 웨이퍼의 제조방법.The first SiO 2 layer uses N 2 O as the oxygen carrier gas and SiH 4 as the silicon carrier gas, and the composition gas ratio satisfies the relationship that SiH 4 : N 2 O = 100 sccm: 1800 sccm = 1:18, and the chamber A method of manufacturing an epitaxial wafer in which the pressure is 4 Torr and the RF power is set to 300W. 자동도핑을 방지하기 위해서 웨이퍼 배면에 굴절률이 다른 제 1 SiO2층과 제 2 SiO2층을 갖는 에피택셜 웨이퍼.An epitaxial wafer having a first SiO 2 layer and a second SiO 2 layer having different refractive indices on the back surface of the wafer to prevent autodoping. 제 7 항에 있어서,The method of claim 7, wherein 상기 제 1 SiO2층은 웨이퍼 실리콘과 접촉하여 형성되며, 상기 제 1 SiO2층 상에 연속하여 상기 제 2 SiO2층이 형성되며, 상기 제 1 SiO2층이 상기 제 2 SiO2층보다 굴절률이 큰 에피택셜 웨이퍼. Wherein 1 SiO 2 layer is formed in contact with the silicon wafer, wherein the 1 SiO 2 layer in succession on a formed is the first 2 SiO 2 layer, wherein the 1 SiO 2 layer having a refractive index than the first 2 SiO 2 layer This big epitaxial wafer. 제 7 항에 있어서,The method of claim 7, wherein 상기 제 2 SiO2층의 굴절률은 1.46 이하인 에피택셜 웨이퍼.The refractive index of the SiO 2 layer 2 is 1.46 or less epitaxial wafer. 제 7 항에 있어서,The method of claim 7, wherein 상기 제 1 SiO2층의 굴절률은 1.46 이상인 에피택셜 웨이퍼.And an index of refraction of said first SiO 2 layer is at least 1.46.
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