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KR100733217B1 - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR100733217B1
KR100733217B1 KR1020050051351A KR20050051351A KR100733217B1 KR 100733217 B1 KR100733217 B1 KR 100733217B1 KR 1020050051351 A KR1020050051351 A KR 1020050051351A KR 20050051351 A KR20050051351 A KR 20050051351A KR 100733217 B1 KR100733217 B1 KR 100733217B1
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contact
semiconductor device
forming
manufacturing
contact pad
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KR20060131136A (en
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김영석
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로, 콘택패드용 노광마스크를 이용한 사진 식각공정으로 콘택패드를 형성하여 보이드 현상을 방지하고, 금속 배선 사이 간격의 마진을 확보하여 브릿지 현상을 방지할 수 있는 기술이다.The present invention relates to a method for manufacturing a semiconductor device, to form a contact pad in a photolithography process using an exposure mask for contact pads to prevent voids, to secure the margin of the gap between the metal wiring to prevent the bridge phenomenon Technology.

콘택패드 Contact pad

Description

반도체 소자의 제조 방법{Method for manufacturing semiconductor devices}Method for manufacturing semiconductor devices

도 1는 종래 기술에 의한 반도체 소자의 금속 배선을 도시한 평면도.1 is a plan view showing a metal wiring of a semiconductor device according to the prior art.

도 2a 내지 도 2e는 종래 기술에 의한 반도체 소자의 제조방법을 도시한 공정 단면도.2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 3는 본 발명의 실시예에 따른 반도체 소자의 금속 배선을 도시한 평면도.3 is a plan view showing a metal wiring of a semiconductor device according to an embodiment of the present invention.

도 4a 내지 도 4c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 도시한 공정 단면도.4A to 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 콘택패드를 갖는 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a contact pad.

최근의 반도체 소자는 소자의 집적도가 증가함에 따라 메모리 셀 크기가 점점 감소되면서 콘택 마진이 점점 작아지므로 콘택을 더욱 작게 형성해야만 한다. In recent semiconductor devices, as the integration degree of the device increases, the contact margin decreases as the memory cell size decreases, and thus the contact has to be made smaller.

이때, 콘택의 크기가 0.25μm이상이고, 깊이가 1000μm 이하인 경우는 알루미늄 메탈 라인으로 콘택을 바로 매립할 수 있었으나, 콘택의 크기가 0.20μm 이하인 경우는 알루미늄으로 콘택 홀을 매립할 수가 없어 콘택을 뚫고 매립 특성이 좋 은 물질로 콘택 홀을 매립하여 금속 배선을 형성하는 방법을 이용하고 있다. At this time, when the contact size was 0.25 μm or more and the depth was 1000 μm or less, the contact could be directly buried with an aluminum metal line. However, when the contact size was 0.20 μm or less, the contact hole could not be buried with aluminum. A method of forming a metal wiring by filling a contact hole with a material having good buried characteristics is used.

도 1은 종래 기술에 의한 반도체 소자의 금속 배선을 도시한 평면도이다. 1 is a plan view showing a metal wiring of a semiconductor device according to the prior art.

도 1과 같이, 절연층(13) 상부에 금속 배선(19a)이 구비되어 있고, 상기 금속 배선(19a)에 도전 배선(도 2a의 11)을 연결하는 콘택 플러그(17a)가 구비되어 있다.  As shown in FIG. 1, a metal wiring 19a is provided on the insulating layer 13, and a contact plug 17a is provided to connect the conductive wiring (11 in FIG. 2A) to the metal wiring 19a.

이때, 콘택 부분을 감싸주기 위하여 상기 금속 배선(19a)을 콘택 플러그(17a) 주위에 두껍게 형성함으로써 금속 배선 사이의 간격이 좁아지고, 브릿지가 유발될 수 있다.At this time, by forming the metal wiring 19a thickly around the contact plug 17a to cover the contact portion, the gap between the metal wirings can be narrowed, and a bridge can be caused.

도 2a 내지 도 2e는 종래 기술에 의한 반도체 소자의 제조방법을 도시한 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

이때, 상기 도 2e는 콘택플러그가 콘택 홀을 완전히 매립하지 못한 경우를 도시한 것이다.
먼저, 도 2a와 같이, 도전 배선(11) 상부에 절연층(13)을 두껍게 도포하고 상기 절연층(13)의 일정 부분을 식각하여 상기 도전 배선(11)을 노출시키는 콘택 홀(15)을 형성한다.2E illustrates a case in which the contact plug does not completely fill the contact hole.
First, as shown in FIG. 2A, the contact hole 15 exposing the conductive wiring 11 by exposing the insulating layer 13 thickly on the conductive wiring 11 and etching a portion of the insulating layer 13 is exposed. Form.

삭제delete

다음으로, 도 2b와 같이, 상기 콘택 홀(15)을 매립하는 콘택 플러그용 도전체(17)를 전체 표면 상부에 형성한다.Next, as shown in FIG. 2B, a contact plug conductor 17 filling the contact hole 15 is formed over the entire surface.

상기 도전체(17)는 단차 회복성이 우수한 도전물질로 형성한 것이다.The conductor 17 is formed of a conductive material having excellent step recoverability.

다음으로, 도 2c와 같이, 상기 도전체(17)를 에치백(etch back)하여 상기 콘택홀(15)을 매립하는 콘택 플러그(17a)를 형성한다.Next, as illustrated in FIG. 2C, the conductor 17 is etched back to form a contact plug 17a filling the contact hole 15.

이어서, 도 2d와 같이, 상기 결과물 전면에 금속층(19)을 증착한다. Subsequently, as shown in FIG. 2D, the metal layer 19 is deposited on the entire surface of the resultant product.

다음으로, 도 2e와 같이, 상기 도전체(17)의 에치백 공정시, 상기 콘택 홀(15) 상측의 도전체(17)가 손실된다. 이때, 상기 금속층(19)의 형성 공정시 단차 피복성이 나쁜 경우, 상기 콘택 홀(15)의 상측을 완전히 매립하지 못하여 보이드(Void)(A)를 유발한다. Next, as illustrated in FIG. 2E, during the etch back process of the conductor 17, the conductor 17 above the contact hole 15 is lost. At this time, when the step coverage is poor in the formation process of the metal layer 19, the upper side of the contact hole 15 is not completely buried to cause a void (A).

상술한 바와 같이 종래기술에 따른 반도체 소자의 제조 방법은, 콘택 플러그를 형성하는 에치백 공정시 수반되는 과도 식각으로 콘택 홀 상부의 손실이 심각하여 금속층 형성 공정시 보이드가 유발될 수 있는 문제점이 있다. 또한, 콘택부분을 감싸주기 위하여 콘택이 지나가는 부분의 금속 배선을 두껍게 형성하므로 상기 금속 배선 사이의 간격이 좁아지게 되어 브릿지가 유발될 수 있는 문제점이 있다.As described above, the method of manufacturing a semiconductor device according to the related art has a problem that voids may be caused in a metal layer forming process due to severe loss of the upper portion of the contact hole due to excessive etching accompanying the etch back process of forming the contact plug. . In addition, since the metal wiring of the portion through which the contact passes is formed thick to surround the contact portion, there is a problem that the gap between the metal wirings is narrowed, thereby causing a bridge.

상기 문제점을 해결하기 위한 본 발명의 목적은 콘택플러그를 형성하는 에치백 공정없이 마스크를 이용한 식각공정으로 콘택패드를 형성함으로써 보이드 현상을 방지할 수 있으며, 금속 배선 사이 간격의 마진을 확보하여 브릿지 현상을 방지할 수 있는 반도체 소자의 제조 방법을 제공하기 위한 것이다.An object of the present invention for solving the above problems is to prevent the void phenomenon by forming a contact pad in the etching process using a mask without an etch back process for forming a contact plug, bridges by securing a margin of the gap between metal wiring It is to provide a method for manufacturing a semiconductor device that can prevent the.

상기 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은,
도전 배선 상부에 절연층을 형성하는 단계;
상기 절연층을 식각하여 상기 도전 배선을 노출시키는 콘택 홀을 형성하는 단계;
상기 콘택 홀을 매립하는 콘택플러그용 도전체를 전면에 형성하는 단계;
콘택패드용 노광마스크를 이용한 사진 식각공정으로 콘택패드를 형성하는 단계; 및
상기 콘택패드 보다 좁거나 같은 선폭으로 상기 콘택패드에 접속되는 금속 배선을 형성하는 단계
를 포함하는 것을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object,
Forming an insulating layer on the conductive wiring;
Etching the insulating layer to form a contact hole exposing the conductive wiring;
Forming a contact plug conductor on the front surface to fill the contact hole;
Forming a contact pad by a photolithography process using an exposure mask for the contact pad; And
Forming a metal wire connected to the contact pad with a line width narrower than or equal to the contact pad;
Characterized in that it comprises a.

이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명의 실시예에 따른 반도체 소자의 금속 배선을 도시한 평면도이다.3 is a plan view illustrating metal wiring of a semiconductor device in accordance with an embodiment of the present invention.

도 3과 같이, 절연층(23) 상부에 금속 배선(31a)이 구비되어 있고, 상기 금속 배선(31a)에 도전 배선(도 4a의 21)을 연결하는 콘택홀(25)이 구비되어 있다.As shown in FIG. 3, the metal wiring 31a is provided on the insulating layer 23, and the contact hole 25 connecting the conductive wiring (21 in FIG. 4A) to the metal wiring 31a is provided.

도 4a 내지 도 4c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 도시한 공정 단면도로서, 도 3의 ⓐ-ⓐ′절단면을 따라 도시한 것이다.4A through 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, and are taken along the line AA ′ of FIG. 3.

먼저, 도 4a와 같이, 도전 배선(21)상에 절연층(23)을 두껍게 도포하고 상기 절연층(23)의 일정 부분을 식각하여 상기 도전 배선(21)을 노출시키는 콘택 홀(25)을 형성한다. First, as shown in FIG. 4A, the contact hole 25 exposing the conductive wiring 21 by exposing the insulating layer 23 thickly on the conductive wiring 21 and etching a portion of the insulating layer 23 is exposed. Form.

다음으로, 도 4b와 같이, 상기 콘택 홀(25)을 매립하는 콘택 플러그용 도전체(27)를 전체 표면 상부에 형성하고, 그 상부에 감광막(미도시)을 도포한다.Next, as shown in FIG. 4B, a contact plug conductor 27 filling the contact hole 25 is formed over the entire surface, and a photosensitive film (not shown) is applied thereon.

이때, 상기 도전체(27)는 단차 회복성이 우수한 도전물질로 형성한 것이다.In this case, the conductor 27 is formed of a conductive material having excellent step recoverability.

이후, 콘택패드용 노광 마스크를 이용한 노광 및 현상 공정으로 콘택 홀(25)과 그 주변의 절연층(23)의 소정 영역을 덮도록 감광막 패턴(29)을 형성한다.Subsequently, the photosensitive film pattern 29 is formed to cover a predetermined region of the contact hole 25 and the insulating layer 23 around the contact hole 25 by an exposure and development process using an exposure mask for contact pads.

이어서, 도 4c와 같이, 상기 감광막 패턴(29)을 마스크로 상기 콘택 플러그용 도전체(27)를 식각하여 콘택 패드(30)가 구비되는 콘택플러그(27a)를 형성하고, 상기 감광막 패턴(29)을 제거한 다음, 그 상부에 금속층(31)을 증착한다.Subsequently, as shown in FIG. 4C, the contact plug conductor 27 is etched using the photoresist pattern 29 as a mask to form a contact plug 27a provided with the contact pad 30, and the photoresist pattern 29 ) Is removed, and then a metal layer 31 is deposited thereon.

후속 공정으로, 상기 금속층(31)을 패터닝하여 상기 콘택 패드(30)의 선폭과 같거나 좁게 금속 배선(도 3의 31a)을 형성한다. 따라서, 금속 배선(도 3의 31a) 사이 간격의 마진을 확보할 수 있으며, 상기 금속배선(도 3의 31a)을 일자로 형성할 수 있다. In a subsequent process, the metal layer 31 is patterned to form metal wirings 31a of FIG. 3 that are equal to or narrower than the line width of the contact pad 30. Therefore, the margin of the gap between the metal wirings 31a of FIG. 3 can be secured, and the metal wirings 31a of FIG. 3 can be formed in a straight line.

이상에서 살펴본 바와 같이, 본 발명은 콘택플러그를 형성하는 에치백 공정없이 마스크를 이용한 식각공정으로 콘택패드를 형성한다. 이를 통해 금속층을 완전히 매립하지 못하여 발생하는 보이드 현상을 방지할 수 있으며, 금속 배선을 일자로 형성할 수 있다. 또한, 마스크를 이용하여 콘택패드의 크기와 위치를 조절할 수 있으며, 금속배선 사이 간격의 마진을 확보하여 브릿지 현상을 방지할 수 있는 효과를 제공한다.As described above, the present invention forms a contact pad by an etching process using a mask without an etch back process of forming a contact plug. As a result, it is possible to prevent voids caused by not completely filling the metal layer, and to form metal wires in a straight line. In addition, the size and position of the contact pad can be adjusted using a mask, and the margin of the gap between the metal wires can be secured, thereby providing an effect of preventing the bridge phenomenon.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허 청구 범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (5)

도전 배선 상부에 절연층을 형성하는 단계;Forming an insulating layer on the conductive wiring; 상기 절연층을 식각하여 상기 도전 배선을 노출시키는 콘택 홀을 형성하는 단계;Etching the insulating layer to form a contact hole exposing the conductive wiring; 상기 콘택 홀을 매립하는 콘택플러그용 도전체를 전면에 형성하는 단계;Forming a contact plug conductor on the front surface to fill the contact hole; 콘택패드용 노광마스크를 이용한 사진 식각공정으로 콘택패드를 형성하는 단계; 및 Forming a contact pad by a photolithography process using an exposure mask for the contact pad; And 상기 콘택패드 보다 좁거나 같은 선폭으로 상기 콘택패드에 접속되는 금속 배선을 형성하는 단계Forming a metal wire connected to the contact pad with a line width narrower than or equal to the contact pad; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, 상기 콘택플러그용 도전체는 단차 회복성이 우수한 도전물질로 형성한 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the contact plug conductor is formed of a conductive material having excellent step recoverability. 삭제delete 제 1 항에 있어서, 상기 사진 식각 공정은 상기 콘택플러그용 도전체와 상기 절연층의 식각 선택비 차이를 이용하여 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the photolithography process is performed using a difference in etching selectivity between the contact plug conductor and the insulating layer. 삭제delete
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020001328A (en) * 2000-06-28 2002-01-09 윤종용 Method for manufacturing conductive contact body of semiconductor device
KR20020003013A (en) * 2000-06-30 2002-01-10 윤종용 Method for manufacturing conductive contact of semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020001328A (en) * 2000-06-28 2002-01-09 윤종용 Method for manufacturing conductive contact body of semiconductor device
KR20020003013A (en) * 2000-06-30 2002-01-10 윤종용 Method for manufacturing conductive contact of semiconductor device

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