KR100745070B1 - Landing plug formation method of semiconductor device - Google Patents

Abstract

A method of forming a landing plug of a semiconductor device according to the present invention includes forming a nitride film for a spacer on an entire surface of a semiconductor substrate on which a gate stack is formed; Forming an interlayer insulating film over the gate stack and the semiconductor substrate; Exposing a predetermined region of the spacer nitride film; Forming a first oxide film on the entire surface of the semiconductor substrate; Selectively removing the first oxide film on the gate stack sidewall and the semiconductor substrate; Forming a second oxide film on the entire surface of the semiconductor substrate including the first oxide film; Etching the spacer nitride film to form the spacer film while selectively removing the second oxide film on both sides of the gate stack and the bottom surface of the semiconductor substrate; And forming a landing plug on the semiconductor substrate.

Landing Plug, First Oxide, Second Oxide, USG

Description

Method for fabricating landing plug in the semiconductor device

1A to 1F are views illustrating a method of forming a landing plug of a semiconductor device according to the related art.

2A to 2J are views illustrating a method of forming a landing plug of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

200 semiconductor substrate 212 gate stack

220: first oxide film 224: second oxide film

228: conductive film for landing plug

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a landing plug of a semiconductor device.

Recently, a DRAM device having a high capacity has been used as a semiconductor memory device. The DRAM device includes a memory cell region for storing information data in the form of charge and a peripheral circuit region for inputting and outputting data, and a unit cell of the memory cell region includes one transistor and one capacitor. In order to form such a DRAM device, first, a transistor including a word line and a source / drain is formed on a semiconductor substrate, and contact holes are formed on the source and the drain selectively through an interlayer insulating film. After forming the storage nodes of the bit line and the capacitor respectively connected to the source and the drain through the contact hole, the dielectric layer and the plate electrode are formed on the storage node to form the capacitor.

However, as the degree of integration of semiconductor devices increases, process margins decrease. Accordingly, self-aligned contact (SAC) processes are mainly used to form contact plugs connecting the source, the bit line, the drain, and the storage node. When the self-aligned contact process is used, even if a misalignment occurs, the nitride film acts as a buffer film to prevent the bridge phenomenon between the gate conductive film and the contact plug.

1A to 1F are views illustrating a method of forming a landing plug of a semiconductor device according to the related art.

First, referring to FIG. 1A, an isolation layer 102 for defining an active region is formed on a semiconductor substrate 100. A gate stack 112 is then formed on the semiconductor substrate 100. The gate stack 112 has a structure in which the gate insulating film pattern 104, the conductive film pattern 106, the metal silicide film pattern 108, and the hard mask film pattern 110 are sequentially stacked. The gate insulating film pattern 104 may be formed of an oxide film, the conductive film pattern 106 may be formed of a poly film, and the metal silicide film pattern 108 may be formed of a tungsten silicide (WSix) film. The hard mask layer pattern 110 may be formed of a nitride layer. The nitride film 114 for spacers is formed on the entire surface of the gate stack 112.

Next, referring to FIG. 1B, an interlayer insulating film 116 is formed on the semiconductor substrate 100 and the gate stack 112, and a photoresist film selectively exposing the spacer nitride film 114 on the interlayer insulating film 116. A pattern (not shown) is formed. Subsequently, an etching process using a photosensitive film pattern as a mask is performed to selectively expose the spacer nitride film 114.

Next, referring to FIG. 1C, an undoped silicate glass (USG) oxide film 118 is formed on the exposed spacer nitride film 114 and the semiconductor substrate 100 by a chemical vapor deposition (CVD) method. do. In this case, the USG oxide layer 118 is thinly deposited on both sides of the gate stack 112 and the bottom of the semiconductor substrate, and is thickly deposited on the top of the hard mask layer pattern 110. The USG oxide film 118 serves as a buffer film when removing the spacer nitride film 114 remaining in the lower portion of the gate stack 112 during a process of forming a subsequent landing plug contact hole (LPC). Do it.

Next, referring to FIG. 1D, the landing plug contact hole is formed by removing the USG oxide layer 118, and a spacer layer 120 is formed on the side of the gate stack 112. The USG oxide layer 118 may be removed using an etch-back process or a chemical mechanical polishing (CMP) method using a slurry of high selectivity. The chemical mechanical polishing is stopped when the hard mask film pattern 110 located on the upper portion of the gate stack 112 begins to be exposed due to the difference in the selectivity between the oxide film and the nitride film. However, the etchback process is performed in a state in which sufficient USG oxide layer 118 does not exist on the hard mask layer pattern 110, so that the USG oxide layer 118 does not act as a buffer and is lost to the hard mask layer pattern 110. A) occurs.

Next, referring to FIG. 1E, the landing plug poly film 122 is formed to fill the landing plug contact hole and the semiconductor substrate 100, and an etch back of the landing plug poly film 122 is formed to separate the gate stacks. etch-back). However, the gate stack 112 exposed by the misalignment during subsequent storage node contact (not shown) etching due to the loss of the hard mask layer pattern 110 caused by the etch back process of the USG oxide layer 118. This attack causes a self-aligned contact (SAC) process failure to cause a bridge between the gate stack 112 and the storage node contact plug, thereby deteriorating the reliability of the device.

The technical problem to be achieved by the present invention is to improve the USG oxide film formation process to ensure the thickness of the nitride film for hard mask and the separation critical dimension (CD) sufficient in the process of separating between the subsequent gate electrode to achieve a self-aligned contact (SAC) margin The present invention provides a method of forming a landing plug of a semiconductor device which prevents a bridge from being generated between a gate electrode and a storage node contact plug.

In order to achieve the above technical problem, a method of forming a landing plug of a semiconductor device according to the present invention comprises: forming a nitride film for a spacer on the entire surface of a semiconductor substrate on which a gate stack is formed; Forming an interlayer insulating film over the gate stack and the semiconductor substrate; Exposing a predetermined region of the spacer nitride film; Forming a first oxide film over the entire semiconductor substrate; Selectively removing the first oxide film on the gate stack sidewall and the semiconductor substrate; Forming a second oxide film on an entire surface of the semiconductor substrate including the first oxide film; Etching the spacer nitride film to form a spacer film while selectively removing the second oxide film on both side surfaces of the gate stack and the bottom surface of the semiconductor substrate; And forming a landing plug on the semiconductor substrate.

The forming of the landing plug on the semiconductor substrate may include forming a landing plug contact hole by patterning a region in which the resulting landing plug is to be formed; Forming a landing plug embedded material in the contact hole; And planarizing the landing plug buried material until the second oxide film is exposed.

It is preferable that USG is used for the said 1st and 2nd oxide film.

The first oxide film may be formed to a thickness of 500 kPa.

In the step of selectively removing the first oxide layer, one of wet etching and dry etching may be used.

The second oxide film may be formed to a thickness of 600-1200 kPa.

The landing plug buried material is preferably any one of poly, tungsten, aluminum.

The planarizing of the landing plug embedded material may use any one of an etch back or chemical mechanical polishing (CMP) method.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

2A to 2J are diagrams for describing a method for forming a landing plug of a semiconductor device according to an exemplary embodiment of the present invention.

First, referring to FIG. 2A, an isolation layer 202 is formed on the semiconductor substrate 200 to define an active region. A gate stack 212 is then formed on the semiconductor substrate 200. The gate stack 212 has a structure in which the gate insulating layer pattern 204, the conductive layer pattern 206, the metal silicide layer pattern 208, and the hard mask layer pattern 210 are sequentially stacked. The conductive film pattern 206 may be formed by applying a conductive material such as polysilicon, and the metal silicide film pattern 208 may be formed of a tungsten silicide (WSix) film. In addition, the hard mask layer pattern 210 may be formed of a nitride layer. The nitride film 214 for the spacer is formed over the gate stack 212 and the semiconductor substrate 200.

Next, referring to FIG. 2B, an interlayer insulating film 216 is formed on the semiconductor substrate 200 and the gate stack 212, and a photoresist film selectively exposing the spacer nitride film 214 on the interlayer insulating film 216. A pattern (not shown) is formed.

Next, referring to FIG. 2C, an etching process using a photosensitive film pattern as a mask is performed to selectively expose the spacer nitride film 214.

Next, referring to FIG. 2D, a first undoped silicate glass (USG) oxide film 220 is formed on the entire surface of the gate stack 212 and the semiconductor substrate 200. The first USG oxide film 220 is formed to have a thickness of 500 kW or less by using a chemical vapor deposition (CVD) method using a siethylene (SiH₄) gas as a source gas. In this case, since the first USG oxide layer 220 has poor step coverage characteristics, the first USG oxide layer 220 is thinly deposited on both sides of the gate stack 212 and the bottom surface of the semiconductor substrate 200, and the upper portion of the hard mask layer pattern 210. It is formed in the form of thick deposition on the top. When the first USG oxide layer 220 removes the spacer nitride layer 214 remaining under the gate stack 212 during a process of forming a subsequent landing plug contact hole (LPC), the buffer It just acts.

Next, referring to FIG. 2E, an etching process is performed on the first USG oxide layer 220 to selectively remove the first USG oxide layer 220 on the side surface of the gate stack 212 and the bottom surface of the semiconductor substrate 200. . That is, when the etching process is performed, the first USG oxide layer 220 on the side of the gate stack 212 and the bottom surface of the semiconductor substrate 200, which are thinly deposited by the etching rate, is completely removed while being relatively thick. The first USG oxide layer 220 on the gate stack 212 deposited is partially left. Here, the etching process may use either wet etching or dry etching. At this time, when the removal is performed using wet etching, selective etching may be performed to leave the first USG oxide layer 220 on the bottom surface of the gate stack 212 at a thickness of about 200-300 Å. In addition, in the case of removing by dry etching, etching is performed until the spacer nitride layer 214 is exposed.

Next, referring to FIG. 2F, a second USG oxide film 224 is formed on the entire surface of the semiconductor substrate 200 including the first USG oxide film 220 remaining on the gate stack 212. The second USG oxide film 224 may be formed to be thicker than the deposition thickness of the first USG oxide film 220 by using a chemical vapor deposition method using a SiH (SiH₄) gas as a source gas, in an embodiment of the present invention. It is preferable to form the thickness of 600-1200 GPa. The second USG oxide layer 224 may be formed on the gate stack 212 in which the first USG oxide layer 220 remains to secure a sufficient thickness, thereby performing a planarization process for forming a subsequent landing plug. The hard mask layer pattern 210 of the stack 212 may be prevented from being damaged.

Next, referring to FIG. 2G, the spacer nitride film 214 is etched while selectively removing the second USG oxide film 224 on both side surfaces of the gate stack 212 and the bottom surface of the semiconductor substrate 200. The spacer film 226 is formed. In this case, the second USG oxide layer 224 is formed sufficiently thick on the gate stack 212 even if the etch back process is excessively performed to prevent the contact hole from opening when forming the subsequent landing plug contact hole. The mask layer pattern 210 may be prevented from being attacked.

Next, referring to FIG. 2H, the landing plug conductive film 228 is deposited so that the exposed surface of the semiconductor substrate 200 including the second USG oxide film 224 is embedded. The landing plug conductive film 228 may be deposited using polysilicon.

Next, referring to FIG. 2I, the resultant is subjected to a polishing process, for example, an etch back process or a chemical mechanical polishing (CMP) method, until the upper portion of the hard mask layer pattern 210 is exposed. . Here, after depositing the conductive plug 228 for the landing plug, as illustrated in FIG. 2J, a polishing process, for example, an etch back process or a chemical mechanical polishing (CMP) method, may be performed to form the second USG oxide film 224. You can also proceed until the surface is exposed. When the polishing process is performed until the surface of the second USG oxide layer 224 is exposed, a margin of self alignment contact (SAC) defect may be improved during a subsequent storage node contact forming process.

As described so far, according to the method for forming a landing plug of a semiconductor device according to the present invention, by forming a sufficient USG oxide film on the hard mask film pattern of the gate stack by using the step coverage characteristics and the etching process characteristics of the USG oxide film. The hard mask film pattern can be prevented from being damaged. In addition, by preventing the hard mask layer pattern from being damaged, the yield of the device may be improved by improving the margin of defects of the self-aligned contact of the subsequent storage node contact and the gate stack.

Claims (8)

Forming a nitride film for a spacer on an entire surface of the semiconductor substrate on which the gate stack is formed; Forming an interlayer insulating film over the gate stack and the semiconductor substrate; Exposing a predetermined region of the spacer nitride film; Forming a first oxide film over the entire semiconductor substrate; Etching the upper portion of the gate stack such that the first oxide layer on the side of the gate stack is removed while remaining a portion of the gate stack; Forming a second oxide film on an entire surface of the semiconductor substrate including the first oxide film; Etching the spacer nitride film to form a spacer film while selectively removing the second oxide film on both side surfaces of the gate stack and the bottom surface of the semiconductor substrate; And And forming a landing plug on the semiconductor substrate. The method of claim 1, wherein the forming of the landing plug on the semiconductor substrate comprises: Patterning a region where the resulting landing plug is to be formed to form a landing plug contact hole; Forming a landing plug embedded material in the contact hole; And And planarizing the landing plug buried material until the second oxide film is exposed. The method of claim 1, The first and second oxide films are USG, characterized in that the landing plug forming method of the semiconductor device. The method of claim 1, And the first oxide film is formed to a thickness of 500 kPa. The method of claim 1, In the step of selectively removing the first oxide film, the landing plug forming method of a semiconductor device, characterized in that using either wet etching or dry etching. The method of claim 1, And the second oxide film is formed to a thickness of 600-1200 kPa. The method of claim 1, The landing plug buried material is a landing plug forming method of a semiconductor device, characterized in that using any one of poly, tungsten, aluminum. The method of claim 1, The planarization of the landing plug embedded material may include any one of an etch back or chemical mechanical polishing (CMP) method.

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