KR100757920B1 - Reference voltage generation circuit of semiconductor memory device and control method thereof - Google Patents

Abstract

A reference voltage generation circuit of a semiconductor memory device of the present invention includes: a voltage generator configured to generate an internal voltage generator control voltage from a first voltage in response to an input of a first control signal; A control signal generator for distributing the first voltage to generate a second control signal; And a controller configured to control the level of the internal voltage generator control voltage in response to the potential level of the second control signal.

Semiconductor memory device, reference voltage, internal voltage generator control voltage

Description

Circuit for Generating Reference Voltage in Semiconductor Memory Apparatus and Control Method for the Same}

1 is a block diagram showing an arrangement of a reference voltage generation circuit of a semiconductor memory device according to the prior art;

FIG. 2 is a circuit diagram of an OP amplifier provided in the reference voltage divider and each internal voltage generator shown in FIG.

3 is a graph illustrating an operation of a reference voltage generation circuit of a semiconductor memory device according to the related art;

4 is a block diagram showing an internal configuration of a reference voltage generation circuit of a semiconductor memory device according to the present invention;

5 is a detailed configuration diagram of the reference voltage generation circuit shown in FIG. 4;

6 is a graph for describing an operation of a reference voltage generation circuit of a semiconductor memory device according to the present invention.

<Description of the symbols for the main parts of the drawings>

10/80: reference voltage generation circuit 20: power divider

30: core voltage generator 40: ambient voltage generator

50: high potential voltage generator 60: bulk voltage generator

70: OP amplifier 810: first control unit

820: temperature compensation unit 830: first voltage generation unit

840: second voltage generator 850: second control signal generator

860: second control unit

The present invention relates to a reference voltage generator circuit of a semiconductor memory device and a method of controlling the same, and more particularly, an internal voltage generator control voltage supplied to an OP amplifier provided in a reference voltage divider and a plurality of internal voltage generators. A reference voltage generation circuit of a semiconductor memory device controlled according to the level of VDD) and a control method thereof.

In general, a semiconductor memory device receives a voltage such as an external power supply (VDD) and a ground voltage (VSS) from the outside of the chip, and includes a reference voltage (Vref), a core voltage (Vcore), a peripheral voltage (Vperi), and a high potential voltage ( Internal voltages such as VPP) and bulk voltage (VBB) are generated and used by themselves. At this time, the reference voltage Vref becomes an important power source used to generate the core voltage Vcore, the peripheral voltage Vperi, the high potential voltage VPP, the bulk voltage VBB, and the like. In this case, each of the above-described internal voltage generators includes an OP amplifier, and the reference voltage generation circuit for generating the reference voltage Vref also generates and supplies an internal voltage generator control voltage for operating the OP amplifier.

Hereinafter, a reference voltage generation circuit according to the related art will be described with reference to FIGS. 1 to 3.

1 is a block diagram illustrating an arrangement of a reference voltage generation circuit of a semiconductor memory device according to the related art.

The reference voltage generator 10 generates and outputs a reference voltage Vref and an internal voltage generator control voltage Vigncnt, and the reference voltage Vref under the control of the internal voltage generator control voltage Vigncnt. A power divider 20 to supply an internal voltage generator of the core voltage generator 30 to generate a core voltage Vcore from the reference voltage Vref according to the control of the internal voltage generator control voltage Vigncnt. Peripheral voltage generator 40 generating a peripheral voltage Vperi from the reference voltage Vref under the control of a voltage generator control voltage Vigncnt, and the reference voltage under the control of the internal voltage generator control voltage Vigncnt. The bulk voltage VBB is derived from the reference voltage Vref under the control of the high voltage generator 50 and the internal voltage generator control voltage Vigncnt, which generate the high potential voltage VPP from Vref. The resulting bulk voltage generator 60 is shown.

Since the power divider 20 and each of the internal voltage generators 30 to 60 are each provided with an OP amplifier, the internal voltage generator control voltage Vigncnt generated by the reference voltage generator 10 is the power divider. 20 and a voltage to start the operation of each of the internal voltage generators 30 to 60. Thereafter, each of the internal voltage generators 30 to 60 converts the reference voltage Vref to a predetermined voltage level to generate respective internal voltages.

FIG. 2 is a circuit diagram of an OP amplifier provided in the reference voltage divider and each internal voltage generator shown in FIG. 1.

As illustrated, the OP amplifier 70 includes a comparator 710 for comparing the reference voltage Vref and the divided voltage Vdiv, and an external power supply VDD according to a comparison result of the comparator 710. Is supplied to the first output node Nout1, the switching unit 720, the voltage divider 730 for generating the divided voltage Vdiv by distributing the voltage applied to the first node Nout1, and the internal voltage. The comparison control unit 740 controls the operation of the comparison unit 710 according to the control of the generator control voltage Vigncnt.

The comparator 710 may include a first transistor having a gate terminal connected to the first node N1, an external supply power VDD applied to a source terminal, and a drain terminal connected to the second node N2. TR1), a second transistor TR2 having a gate terminal and a drain terminal connected to the first node N1 and the external supply power supply VDD applied to a source terminal, and the reference voltage Vref applied to a gate terminal. The distribution voltage Vdiv is applied to the third transistor TR3 and the gate terminal where the drain terminal is connected to the second node N2, the source terminal is connected to the third node N3, and the drain terminal is connected to the first node. The fourth terminal TR4 is connected to the node N1 and the source terminal is connected to the third node N3.

In addition, the switching unit 720 has a gate terminal connected to the second node N2, the external supply power supply VDD is applied to a source terminal, and a drain terminal connected to the first output node Nout1. It consists of five transistors TR5.

The voltage divider 730 includes a sixth transistor TR6 having a gate terminal and a drain terminal connected to the first output node Nout1, and a source terminal connected to a fourth node N4, and a gate terminal and a drain terminal. The seventh transistor TR7 is connected to the fourth node N4 and the source terminal is connected to the common ground node Ngnd.

Finally, the comparison controller 740 is configured to apply the internal voltage generator control voltage Vigncnt to a gate terminal, a drain terminal thereof to the third node N3, and a source terminal thereof to the common ground node Ngnd. It consists of the 8th transistor TR8.

Here, the sixth and seventh transistors TR6 and TR7 of the voltage divider 730 distribute the output voltage Vout applied to the first output node Nout1 to the fourth node N4. Is provided for feeding. The level of the voltage applied to the fourth node N4 is determined according to the ratio of the resistance values held by the sixth and seventh transistors TR6 and TR7, respectively. That is, the voltage applied to the fourth node N4 becomes the division voltage Vdiv.

The OP amplifier 70 configured as described above starts to operate when the internal voltage generator control voltage Vigncnt is enabled. This is because the ground voltage VSS of the common ground node Ngnd is transmitted to the third node N3 until the eighth transistor TR8 of the comparison controller 740 is turned on. When the internal voltage generator control voltage Vigncnt has a preset level, the level of the reference voltage Vref input to the third transistor TR3 of the comparator 710 is the fourth transistor TR4. When the voltage level is higher than the level of the divided voltage Vdiv input to the voltage level, the potential level of the second node N2 is lower than the potential level of the first node N1. Accordingly, the amount of current flowing through the fifth transistor TR5 of the switching unit 720 increases, and then the level of the output voltage Vout and the distribution voltage Vdiv also increases.

On the other hand, when the level of the reference voltage Vref is lower than the level of the division voltage Vdiv, the potential level of the second node N2 becomes higher than the potential level of the first node N1. Accordingly, the amount of current flowing through the fifth transistor TR5 is reduced, and the level of the output voltage Vout and the distribution voltage Vdiv is also lowered.

That is, the output voltage Vout of the OP amplifier 70 has a potential level amplified by a predetermined multiple of the reference voltage Vref by the resistance ratio formed in the voltage divider 730. In general, since the internal voltage generator control voltage Vigncnt as well as the reference voltage Vref maintains a constant potential level, the output voltage Vout of the OP amplifier 70 may also maintain a constant potential level.

3 is a graph illustrating an operation of a reference voltage generation circuit of a semiconductor memory device according to the related art.

In the figure, 1.6 V to 2.2 V, which is a general operating area, is represented in the level change of the external power supply VDD. It can be seen that the level of the reference voltage (Vref) and the internal voltage generator control voltage (Vigncnt) generated according to the prior art is kept constant at 823mV and 751mV in the operating region of the external power supply (VDD), respectively. .

As such, when the internal voltage generator control voltage Vigncnt maintains a constant level, when the external power supply VDD maintains a level close to 2.2 V, that is, the internal voltage generator control voltage in a high VDD region. The supply of (Vigncnt) has a problem that excessive current flows through the transistors in the OP amplifier. That is, power consumption has been generated in each OP amplifier according to the level change of the external power supply VDD, but this problem has not been improved conventionally.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and is a reference of a semiconductor memory device that reduces power consumption by differentially generating a level of an internal voltage generator control voltage according to a level of an external supply power source (VDD) in an operating region. There is a technical problem in providing a voltage generation circuit and a control method thereof.

According to an aspect of the present invention, there is provided a reference voltage generation circuit of a semiconductor memory device, the voltage generation unit generating an internal voltage generator control voltage from a first voltage in response to an input of a first control signal; A control signal generator for distributing the first voltage to generate a second control signal; And a controller configured to control the level of the internal voltage generator control voltage in response to the potential level of the second control signal.

In addition, the reference voltage generation circuit of the semiconductor memory device of the present invention, the voltage generator for generating an internal voltage generator control voltage from an external power supply (VDD) in response to the input of the first control signal; A control unit for lowering the level of the internal voltage generator control voltage when the potential of the second control signal is greater than or equal to a predetermined level; And a control signal generator for distributing the external supply power VDD to generate a second control signal.

The control method of the reference voltage generation circuit of the semiconductor memory device of the present invention includes the steps of: a) generating an internal voltage generator control voltage from the first voltage in response to an input of the first control signal; b) dividing the first voltage to generate a second control signal; And c) controlling the level of the internal voltage generator control voltage according to the potential of the second control signal.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

4 is a block diagram illustrating an internal configuration of a reference voltage generation circuit of a semiconductor memory device according to the present invention.

As illustrated, the reference voltage generation circuit 80 of the first control unit 810 and the first control unit 810 may generate a first control signal ctrl1 in response to an input of an external power supply VDD. A temperature compensator 820 for generating a reference voltage Vref from the external power supply VDD in response to an input of the first control signal ctrl1 so that the operation is not affected by a temperature change; A second voltage generator 840 for generating and outputting an internal voltage generator control voltage Vigncnt from an external supply power source VDD in response to an input of the first voltage generator 830 and the first control signal ctrl1; The internal voltage generator control voltage corresponding to a potential level of the second control signal generator 850 and the second control signal ctrl2 that distributes the external supply power VDD to generate a second control signal ctrl2. And a second control unit 860 for controlling the level of Vigncnt. .

The first control signal ctrl1 is a signal generated when the external supply power VDD is input to the first controller 810. The first control signal ctrl1 may perform the operation of generating the reference voltage Vref of the first voltage generator 830 and the operation of generating the internal voltage generator control voltage Vigncnt of the second voltage generator 840. Used to control. At this time, the temperature compensator 820 serves to prevent the first control signal ctrl1 from being affected by the temperature change.

The second control signal generator 850 distributes the external supply power VDD to generate the second control signal ctrl2. Thereafter, the second control signal ctrl2 is supplied to the second control unit 860, and the second control unit 860 is configured to enable the second voltage generation unit () according to whether the second control signal ctrl2 is enabled. The level of the internal voltage generator control voltage Vigncnt generated at 840 is controlled.

Detailed configuration and operation of the reference voltage generation circuit 80 configured as described above will be described with reference to FIG. 5.

FIG. 5 is a detailed configuration diagram of the reference voltage generation circuit shown in FIG. 4.

As illustrated, the first controller 810 has a gate terminal connected to the fifth node N5, the external supply power VDD applied to a source terminal, and a drain terminal connected to the sixth node N6. A ninth transistor TR9 and a gate terminal and a drain terminal are connected to the fifth node N5 and the tenth transistor TR10 to which the external supply power supply VDD is applied to a source terminal.

The temperature compensator 820 includes an eleventh transistor TR11 having a gate terminal and a drain terminal connected to the sixth node N6, and a source terminal connected to a common ground terminal, and a gate terminal of the temperature compensator 820. Is connected to the fifth node N5 and the drain terminal is configured to include a twelfth transistor TR12 and a first resistor R1 provided between the source terminal of the twelfth transistor TR12 and the common ground terminal. .

In addition, the first voltage generator 830 has a gate terminal connected to the fifth node N5, an external supply power VDD applied to a source terminal, and a drain terminal connected to a second output node Nout2. A thirteenth transistor TR13 and a gate terminal and a drain terminal are connected to the second output node Nout2 and are configured of a fourteenth transistor TR14 to which a ground voltage VSS is applied to a source terminal.

The second voltage generator 840 has a gate terminal connected to the fifth node N5, a source terminal applied with the external supply power supply VDD, and a drain terminal connected to a third output node Nout3. A fifteenth transistor TR15 and a gate terminal and a drain terminal are connected to the third output node Nout3 and the sixteenth transistor TR16 to which the ground voltage VSS is applied to a source terminal.

In addition, the second control signal generator 850 is provided between the resistor array RA provided between an external supply power supply VDD input terminal and the seventh node N7 and the seventh node N7 and the ground terminal. It consists of a transistor array TA.

Lastly, the second controller 860 may include a gate terminal connected to the seventh node N7, a drain terminal connected to the third output node Nout3, and a ground voltage VSS applied to a source terminal. 17 transistors TR17.

Through such a configuration, a potential applied to the fifth node N5 of the first controller 810 controls the operations of the first voltage generator 830 and the second voltage generator 840. It can be seen. That is, the potential applied to the fifth node N5 is the first control signal ctrl1.

The voltage applied to the second output node Nout2 may be the reference voltage Vref and the voltage applied to the third output node Nout3 may be the internal voltage generator control voltage Vigncnt.

In addition, the resistor array RA of the second control signal generator 850 may be implemented as a transistor array as well as a combination of resistors as passive elements.

When the external power supply VDD has a potential of a predetermined level or more, a predetermined amount of current flows through the ninth and tenth transistors TR9 and TR10 of the first controller 810. Accordingly, the first control signal ctrl1 is generated at the fifth node N5. At this time, since the first control signal ctrl1 also controls the amount of current flowing through the ninth and tenth transistors TR9 and TR10, the first control signal ctrl1 maintains a constant level.

The current flowing through the ninth transistor TR9 is transmitted to the sixth node N6 and again controls the eleventh and twelfth transistors TR11 and TR12 of the temperature compensator 820. In general, the threshold voltage of the transistor is lower in high temperature conditions than in low temperature conditions. When the temperature of the reference voltage generator 80 is greater than or equal to a predetermined temperature, the threshold voltages of the eleventh and twelfth transistors TR11 and TR12 are lowered. At this time, since the first resistor R1 is provided, the potential level of the first control signal ctrl1 is not lowered. On the contrary, when the temperature of the reference voltage generation circuit 80 is below a predetermined temperature, the threshold voltages of the eleventh and twelfth transistors TR11 and TR12 are increased. At this time, the current flowing through the eleventh transistor TR11 is greater than the current flowing through the twelfth transistor TR12, which controls the amount of current flowing through the ninth transistor TR9. Due to this operation, the potential level of the first control signal ctrl1 is not increased.

Meanwhile, the first control signal ctrl1 is transmitted to the thirteenth transistor TR13 of the first voltage generator 830. At this time, a predetermined amount of current flows through the thirteenth transistor TR13 according to the potential level of the first control signal ctrl1 and is transmitted to the second output node Nout2. Thereafter, the current delivered to the second output node Nout2 again controls the fourteenth transistor TR14 to allow a predetermined amount of current to flow in the fourteenth transistor TR14. The reference voltage Vref is generated by a difference in the amount of current flowing through the thirteenth transistor TR13 and the fourteenth transistor TR14. Therefore, the potential level of the reference voltage Vref is kept constant.

The first control signal ctrl1 is also transmitted to the fifteenth transistor TR15 of the second voltage generator 840. As in the first voltage generator 830, a predetermined amount of current flows through the fifteenth transistor TR15 according to the potential level of the first control signal ctrl1 and is transmitted to the third output node Nout3. . Thereafter, the current delivered to the third output node Nout3 again controls the sixteenth transistor TR16 to allow a predetermined amount of current to flow through the sixteenth transistor TR16. The internal voltage generator control voltage Vigncnt is generated by a difference in the amount of current flowing through the fifteenth transistor TR15 and the sixteenth transistor TR16.

The second control signal ctrl2 is equal to the resistance ratio of the resistor array RA and the transistor array TA of the second control signal generator 850 when the external supply power supply VDD exceeds a predetermined level. To be distributed accordingly.

Thereafter, the second control signal ctrl2 is transmitted to the seventeenth transistor TR17 of the second controller 860. When the second control signal ctrl2 does not turn on the seventeenth transistor TR17, the internal voltage generator control voltage Vigncnt applied to the third output node Nout3 is the second control signal ctrl2. Is not affected. However, when the current flows through the seventeenth transistor TR17 by the second control signal ctrl2, the level of the internal voltage generator control voltage Vigncnt is lowered.

6 is a graph for describing an operation of a reference voltage generation circuit of a semiconductor memory device according to the present invention.

The illustrated graph shows a result of simulating the reference voltage generator circuit 80. In the drawing, when the external power supply VDD is close to 1.6 V, the internal voltage generator control voltage Vigncnt maintains a level of 751 mV, but when the external power supply VDD is close to 2.2 V, 751 mV. When the external power supply (VDD) is 2.2V away from the level it can be seen that the 699mV. In the related art, the current consumption of 17.8 uA decreased to 11.3 uA after the present invention was implemented.

As described above, by applying the reference voltage generation circuit of the semiconductor memory device of the present invention, the problem that excessive current flows through the transistors in the OP amplifier in response to the supply of the internal voltage generator control voltage in the high VDD region can be improved. It became. That is, power consumption is reduced in each OP amplifier according to the level change of the external power supply VDD, thereby increasing power efficiency in using the power divider and each internal voltage generator of the semiconductor memory device.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The reference voltage generation circuit and the control method of the semiconductor memory device of the present invention described above to generate the level of the internal voltage generator control voltage according to the level of the external power supply (VDD) in the operating region to reduce power consumption. It works.

Claims (26)

A voltage generator configured to generate an internal voltage generator control voltage from the first voltage in response to an input of the first control signal; A control signal generator for distributing the first voltage to generate a second control signal; And A controller configured to control a level of the internal voltage generator control voltage in response to a potential level of the second control signal; A reference voltage generation circuit of a semiconductor memory device comprising a. The method of claim 1, The voltage generator, A first transistor having a first control signal input to a gate terminal, a first voltage applied to a source terminal, and a drain terminal connected to an output node; And A second transistor having a gate terminal and a drain terminal connected to the output node and having a ground voltage VSS applied to a source terminal; And wherein the internal voltage generator control voltage is formed at the output node. The method of claim 1, The control signal generator, A resistor array provided between the first voltage input terminal and the first node; And A transistor array provided between the first node and a ground terminal; And wherein the second control signal is formed at the first node. The method of claim 1, The control signal generator, A first transistor array provided between the first voltage input terminal and the first node; And A second transistor array provided between the first node and a ground terminal; And wherein the second control signal is formed at the first node. The method of claim 1, The control unit includes a transistor configured to receive the second control signal at a gate terminal, the internal voltage generator control voltage at a drain terminal, and a ground voltage VSS at a source terminal. Voltage generating circuit. The method of claim 1, And a first controller configured to generate the first control signal in response to the input of the first voltage. The method of claim 6, And a temperature compensator for preventing the operation of the first controller from being affected by the temperature change. The method of claim 7, wherein The first controller and the temperature compensator are connected through a first node and a second node, The first control unit, A first transistor having a gate terminal connected to the first node, a first voltage applied to a source terminal, and a drain terminal connected to the second node; And A second transistor having a gate terminal and a drain terminal connected to the first node and the first voltage applied to a source terminal; Includes, the first control signal is formed in the first node, The temperature compensator, A third transistor having a gate terminal and a drain terminal connected to the second node and a source terminal connected to a common ground terminal; A fourth transistor having a gate terminal connected to the second node and a drain terminal connected to the first node; And A resistor provided between the source terminal of the fourth transistor and the common ground terminal; A reference voltage generation circuit of a semiconductor memory device comprising a. delete The method of claim 1, And a reference voltage generator configured to generate and output a reference voltage (Vref) from the first voltage in response to an input of the first control signal. The method of claim 10, The reference voltage generator, A first transistor having a first control signal input to a gate terminal, a first voltage applied to a source terminal, and a drain terminal connected to an output node; And A second transistor having a gate terminal and a drain terminal connected to the output node and having a ground voltage VSS applied to a source terminal; And a reference voltage (Vref) is formed at the output node. The method of claim 1, And the first voltage is an external supply power supply (VDD). A voltage generator configured to generate an internal voltage generator control voltage from an external supply power source VDD in response to an input of the first control signal; A control unit for lowering the level of the internal voltage generator control voltage when the potential of the second control signal is greater than or equal to a predetermined level; And A control signal generator configured to distribute the external power supply VDD to generate a second control signal; A reference voltage generation circuit of a semiconductor memory device comprising a. The method of claim 13, The voltage generator, A first transistor in which the first control signal is input to a gate terminal, the external supply power source (VDD) is applied to a source terminal, and a drain terminal is connected to an output node; And A second transistor having a gate terminal and a drain terminal connected to the output node and having a ground voltage VSS applied to a source terminal; And wherein the internal voltage generator control voltage is formed at the output node. The method of claim 13, The control unit includes a transistor configured to receive the second control signal at a gate terminal, the internal voltage generator control voltage at a drain terminal, and a ground voltage VSS at a source terminal. Voltage generating circuit. The method of claim 13, The control signal generator, A resistor array provided between the external power supply input terminal and the first node; And A transistor array provided between the first node and a ground terminal; And wherein the second control signal is formed at the first node. The method of claim 13, The control signal generator, A first transistor array provided between the external power supply input terminal and the first node; And A second transistor array provided between the first node and a ground terminal; And wherein the second control signal is formed at the first node. The method of claim 13, And a first controller configured to generate the first control signal in response to an input of the external supply power supply (VDD). The method of claim 18, And a temperature compensator for preventing the operation of the first controller from being affected by the temperature change. The method of claim 19, The first controller and the temperature compensator are connected through a first node and a second node, The first control unit, A first transistor having a gate terminal connected to the first node, a first voltage applied to a source terminal, and a drain terminal connected to the second node; And A second transistor having a gate terminal and a drain terminal connected to the first node and the first voltage applied to a source terminal; Includes, the first control signal is formed in the first node, The temperature compensator, A third transistor having a gate terminal and a drain terminal connected to the second node and a source terminal connected to a common ground terminal; A fourth transistor having a gate terminal connected to the second node and a drain terminal connected to the first node; And A resistor provided between the source terminal of the fourth transistor and the common ground terminal; A reference voltage generation circuit of a semiconductor memory device comprising a. delete The method of claim 13, And a reference voltage generator configured to generate and output a reference voltage (Vref) from the first voltage in response to an input of the first control signal. The method of claim 22, The reference voltage generator, A first transistor having a first control signal input to a gate terminal, a first voltage applied to a source terminal, and a drain terminal connected to an output node; And A second transistor having a gate terminal and a drain terminal connected to the output node and having a ground voltage VSS applied to a source terminal; And a reference voltage (Vref) is formed at the output node. a) generating an internal voltage generator control voltage from the first voltage in response to the input of the first control signal; b) dividing the first voltage to generate a second control signal; And c) lowering the level of the internal voltage generator control voltage if the potential of the second control signal is above a predetermined level; The control method of the reference voltage generation circuit of a semiconductor memory device comprising a. delete The method of claim 24, And the first voltage is an external supply power supply (VDD).

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