KR100769955B1 - Detector of receiver in wireless communication system - Google Patents

Abstract

The present invention relates to a detection apparatus of a receiving end of a wireless communication system.

The detection apparatus of the present invention obtains a first detection signal using a channel transfer function included in a transmission signal and a received first nulling matrix, and a nulling matrix using a first detection signal and a channel transfer function. A determinant calculation unit for generating a determinant for obtaining a; A first channel state calculator for updating a first nulling matrix using a determinant and calculating a first channel state information value using a noise component, a channel transfer function, and a determinant included in a transmission signal; And a second nulling matrix using a determinant and a transmission signal, a first detection signal using a second nulling matrix and a channel transfer function, and a second channel state information value using a noise component, a channel transfer function, and a determinant. And a second channel state calculator for calculating.

According to the present invention, it is possible to reduce the implementation complexity for detecting the signal transmitted by the transmitting end, and at the same time can be expected to effect the efficient detection.

Wireless communication system, receiver, MIMO, detector, multiplier, nulling matrix, channel state

Description

Detector of wireless communication system receiver {DETECTOR OF RECEIVER IN WIRELESS COMMUNICATION SYSTEM}

1 is a block diagram illustrating a detection apparatus of a receiving end of a wireless communication system according to an exemplary embodiment of the present invention.

2 is a diagram illustrating a process of obtaining a determinant and a first signal in a determinant calculation unit according to an exemplary embodiment of the present invention.

3 is a diagram illustrating a process of obtaining a channel state information value in a first channel state calculator according to an exemplary embodiment of the present invention.

4 is a diagram illustrating a process of obtaining a channel state information value in a second channel state calculator according to an exemplary embodiment of the present invention.

5 is a block diagram illustrating a multiplier used in a determinant calculator, a first channel state calculator, and a second channel state calculator according to an embodiment of the present invention.

The present invention relates to a detection apparatus of a wireless communication system receiving end, and more particularly, to a detection apparatus of a wireless communication system receiving end using a multi input multi output (hereinafter referred to as "MIMO") scheme.

 MIMO is a technology that transmits data of the same frequency band in parallel by using a plurality of antennas in parallel to increase the data rate, and receives the transmitted parallel data by a receiver including a plurality of antennas. I use it.

In the MIMO wireless communication system, the signal transmitted by the transmitter using multiple antennas is detected at the receiver. If the received signal is to be received at the same rate as the transmitter, the mixed signal from the radio channel is detected. Must be separated in parallel. Therefore, the multi-antenna detector of the receiving end can efficiently recover the correct signal only by separating the data.

The performance of the detector is greatly influenced by the detection algorithm. In general, a detector capable of detecting even a relatively small signal-to-noise ratio has a high complexity, and when using a low complexity algorithm, an input signal having a relatively high signal-to-noise ratio is required.

In addition, when a signal input and processed by a detector is represented by a binary number, the complexity of hardware increases because the number of binary numbers representing the signal must be increased to increase the accuracy of the signal and the detection / decoding performance. Thus, performance and complexity are generally inversely related.

Conventional multiple transmit / receive antenna detectors (MIMO detectors) have mainly used a method called Vertical Bell-Laboratories Layered Space-Time (V-BLAST).

The implementation complexity of this approach is quite high and the performance is quasi-best. The increase in complexity is mainly due to repeated interfering signal rejection operations.

The algorithm detects the first signal, removes the detected signal component from the first received signal when there are M transmit antennas and transmits M signals in parallel, and then removes the detected signal component from the first received signal. To detect them in turn. This way, if the first detected signal is correctly detected, the accuracy of the next signal is increased, but if it is not, it will greatly affect the result of the next transmission signal detection, and the overall detection performance will be degraded. There are disadvantages.

Accordingly, an object of the present invention is to provide a detection apparatus of a wireless communication system receiver using a MIMO scheme.

According to a first aspect of the present invention for solving the above technical problem, a detection apparatus of a receiving end for receiving and detecting a transmission signal transmitted from a transmitting end of a wireless communication system of a multiple input-output system,

A determinant calculation unit for obtaining a first detection signal using a channel transfer function and a first nulling matrix, and generating a determinant for obtaining a nulling matrix using the first detection signal and a channel transfer function; A first channel state calculator for updating a first nulling matrix using a determinant and calculating a first channel state information value using a noise component, a channel transfer function, and a determinant included in a transmission signal; And a second nulling matrix using a determinant and a transmission signal, a second detection signal using a second nulling matrix and a channel transfer function, and a second channel state information value using a noise component, a channel transfer function, and a determinant. And a second channel state calculator for calculating.

Here, the determinant calculator, the first channel state calculator, and the second channel state calculator include a multiplier that performs limited multiplication of a specific bit.

According to a second aspect of the present invention, a multiplication apparatus used in a receiving end for receiving and detecting a transmission signal transmitted from a transmitting end of a wireless communication system of a multiple input / output system,

Providing a first sign bit of the first signal received, and performing a first division operation on the bits included in the first signal until it is smaller than a specific number, and outputting the first number of divisions and the final first residual value generated; A first valid bit converter; Providing a second sign bit of the received second signal, and performing a second division operation on the bits included in the second signal until the number is smaller than a specific number, and outputting the number of second divisions generated and the final second remainder; A second valid bit converter; A multiplier that multiplies the first residual value by the second residual value; A multiplier that adds a first division number and a second division number; An XOR gate for performing an XOR (eXclusive-OR) on the first sign bit and the second sign bit; A valid bit shifter for generating a first bit using the output value of the adder and the output value of the multiplier; And a bit unit inverter for outputting a multiplication operation value of the first signal and the second signal using the output value of the effective bit shifter and the output value of the XOR gate.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, except to exclude other components unless otherwise stated.

In addition, the term module described herein refers to one unit for processing a specific function or operation, which may implement hardware or software or a combination of hardware and software.

A detection apparatus of a receiving end of a wireless communication system according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a detection apparatus of a receiving end of a wireless communication system according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a detection apparatus according to an embodiment of the present invention includes a determinant calculator 100, a first channel state information calculator 200, a second channel state calculator 300, and a soft decision decoder 400. ).

In the embodiment of the present invention, it is assumed that there are two transmit antennas used in the transmitter and three receive antennas used in the receiver.

In addition, the detector according to the embodiment of the present invention is implemented using a ZF nulling technique among several algorithms.

The determinant calculation unit 100 obtains the determinant and the first detected signal X ₀ necessary to obtain the inverse matrix. The signal r input to the determinant calculator 100 is a signal generated by adding a signal vector x transmitted through a transmission antenna to a noise vector n after passing through a wireless channel transfer function H. It can be expressed as Equation 1.

Here, the row of the channel transfer function matrix H indicates the order of receive antennas, and the column indicates the order of transmit antennas. As shown in Equation 1, the signal input to each receiving antenna is composed of the sum of the noise of the receiving end and the signal generated by multiplying each transmission signal by the channel transfer function H on the radio channel. Therefore, in order to effectively detect / separate the desired transmission signal from the receiver, a nulling matrix W must be obtained.

In this case, the nulling matrix converts the components of the wireless channel transfer function H through the Zero Forcing (ZF) method, which converts the components other than the signal (first or second) to be detected to zero (0). Can be obtained as a basis.

Here, the W matrix may be represented by Equation 2 below.

와

는

와

을 치환한 것이며, C는

을 치환한 것이다.

는 H 행렬의 전치 이다. 또한

는 역행렬을 구할 때 필요한 행렬식(determinant)을 나타낸다. here,

Wow

Is

Wow

Where C is substituted

Is substituted.

Is the transpose of the H matrix. Also

Denotes the determinant needed to find the inverse matrix.

Accordingly, the first column of the W matrix corresponds to a vector w ₀ for detecting the first transmission signal and the second column corresponds to a vector w ₁ for detecting the second transmission signal. Here, w ₀ is calculated by the first channel state calculator and w ₁ is calculated by the second channel state calculator.

)(determinant)을 구하고, 하기 수학식3을 이용하여 첫번째 검파 신호 X₀을 계산한다. 이때, 행렬식(

)(determinant)과 검파된 첫번째 신호 X₀를 구하는 과정은 다음의 도 2에 나타내었다.The determinant calculation unit 100 calculates a determinant required to obtain an inverse matrix using Equation 3 below.

(determinant) is calculated, and the first detected signal X ₀ is calculated using Equation 3 below. Where determinant (

(determinant) and the first signal X ₀ detected is shown in Figure 2 below.

The first channel state calculator 200 calculates a nulling vector w ₀ necessary for detecting the first signal and a channel state of the first signal, and outputs a first channel state information value CS ₀ . At this time, the calculated vector w ₀ is again provided as an input signal of the determinant calculation unit 100. Here, a process of obtaining the vector w ₀ calculated by the first channel state calculator 200 and the channel state information value CS ₀ of the first signal is shown in FIG. 3.

The second channel state calculator 300 obtains a nulling vector w ₁ and a second detected signal required for detecting the second signal, and outputs the second channel state information value CS ₁ . In this case, the process of obtaining the vector w ₁ and the second detected signal X ₁ calculated by the second channel state calculator 300 is shown in FIG. 4.

Meanwhile, the determinant calculator 100, the first channel state calculator 200, and the second channel state calculator 300 include a multiplier illustrated in FIG. 5, and use the multiplier to determine the determinant and the first channel. The state information value CSi ₀ and the second channel state information value CSi ₁ are calculated. In this case, the multiplier is a limited multiplier having a maximum size of 9 bits * 9 bits.

In addition, the determinant calculator 100, the first channel state calculator 200, and the second channel state calculator 300 apply a rounding technique of pseudo code to the adder and the subtractor to compensate for the accuracy of the signal. do.

 At this time, the rounding technique of the pseudo code is a 20-bit signal by adding a signal from the last 7 bits of the signal represented by 26 bits and a signal from the last 10 bits of the signal represented by 29 bits. Unlike the rounding technique that generates, only the last 6 bits of the signal represented by 26 bits are removed, 1 is added, and then the last 9 bits of the 29-bit signal are removed in the same way. After adding 1 and adding a second signal from which the last bit is removed again, a 20-bit signal is generated. This method compensates the accuracy of the signal when representing a decimal point.

The soft decision decoder 400 softly decodes the detection signals X ₀ and X ₁ received from the determinant calculator and the second channel state calculator and transmits the detected signals X ₀ and X ₁ to the next stage. In this case, the soft decision decoder 400 receives the first channel state information value CSi ₀ and the second channel state information value CSi ₁ from the first channel state calculator and the second channel state calculator, and calculates the matrix. Receive the determinant from negative.

Such a detector of the receiving end has the advantage of reducing the complexity caused in detecting / decoding the received signal and at the same time increasing the performance.

2 is a diagram illustrating a process of obtaining a determinant and a first signal in a determinant calculation unit according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the determinant calculation unit 100 according to an embodiment of the present invention detects / decodes a received signal by using Equation 3 below.

Here, the equation (3) Denotes the detected signal as a vector, and vector N, which corresponds to the receiver noise, has little effect on the algorithm.

)만큼 크기가 곱해진 형태가 된다. 이때, 첫번째 검파된 신호(X₀)는 상기 수학식 3에 의해 5단계의 딜레이를 거쳐 계산되고, 최종 행렬식은 8단의 딜레이를 거쳐 계산된다. 즉, 행렬식 계산부(100)는 수신된 신호에 포함된 채널 전달함수와 제1 채널 상태 계산부(200)로부터 수신되는 널링(Nulling)행렬을 이용하여 첫번째 검파 신호(CSi₀)를 구하고, 첫번째 검파 신호(CSi₀)와 채널 전달함수를 이용하여 널링(Nulling)행렬을 구하기 위한 행렬식을 계산한다.The first detected signal shown in Fig. 2 is deterministic than the signal transmitted from the transmitter.

Is multiplied by). At this time, the first detected signal (X ₀ ) is calculated through the delay of five steps by the equation (3), the final determinant is calculated through the delay of eight stages. That is, the determinant calculator 100 obtains the first detection signal CSi ₀ using the channel transfer function included in the received signal and the nulling matrix received from the first channel state calculator 200. A determinant for calculating a nulling matrix is calculated using the detection signal CSi ₀ and a channel transfer function.

3 is a diagram illustrating a process of obtaining a channel state information value in a first channel state calculator according to an exemplary embodiment of the present invention.

As shown in FIG. 3, the first channel state calculation unit 200 according to an embodiment of the present invention is based on the determinant output from the determinant calculation unit 100 shown in FIG. The channel state information value csi ₀ is output using Equation 4.

The first channel state calculating unit 200 receives the determinant output from the determinant calculating unit 100 shown in FIG. 1 and generates a nulling vector W ₀ in the delay step 8 based on Equation 2 above. That is, the first channel state calculator 200 obtains a nulling matrix by using the received signal and the determinant received from the determinant calculator 100, obtains a noise component included in the received signal, and the channel transfer function. And a first channel state information value csi ₀ using the determinant.

In addition, the first channel state calculator 200 outputs channel state information using Equation 4.

4 is a diagram illustrating a process of obtaining channel state information value CSi ₁ in the second channel state calculator according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the second channel state calculator 300 according to an embodiment of the present invention is based on the determinant output from the determinant calculator 100 shown in FIG. The channel state information value csi ₁ is output using Equation 5.

The second channel state calculation unit 300 receives the determinant output from the determinant calculation unit 100 shown in FIG. ₁ and generates a nulling vector W ₁ in the delay step 8 based on Equation 2 above.

In addition, the second channel state calculator 300 calculates the second detected signal X ₁ using Equation 3 and outputs the second channel state information value CSi ₁ using Equation 5. do.

That is, the second channel state calculation unit 300 obtains a nulling matrix W ₁ using the determinant received from the determinant calculation unit 100 and includes the nulling matrix W _{1 in} the nulling matrix W ₁ and the received signal r. The detection signal is obtained using the channel transfer function, and the second channel state information value CSi ₁ is calculated using the noise component, the channel transfer function, and the determinant included in the received signal.

In this case, the second detected signal and the channel state information generated by the second channel state calculation unit 300 are generated through steps 9 and 13 of the delay, respectively.

5 is a block diagram illustrating a multiplier used in a determinant calculator, a first channel state calculator, and a second channel state calculator according to an embodiment of the present invention.

As shown in FIG. 5, the multiplier 500 according to an exemplary embodiment of the present invention includes a first valid bit converter 510, a second valid bit converter 520, a multiplier 560, an adder 570, and a valid bit shifter. 540, a bitwise inverter 550, and an eXclusive-OR (XOR) gate 530, with a limited size of up to 9 bits * 9 bits.

The first valid bit converter 510 stores the sign bit corresponding to the first bit after reading the size of the input signal, and divides the input signal by performing two division operations to store the number of divisions. If the signal divided by 2 is larger than 512 bits, the division 2 operation is repeatedly performed. If not, the absolute value, the sign, and the number of divisions of the signal are output.

In this case, the first valid bit converter 510 converts the input signal to a positive number if the input signal is negative before performing the division operation.

After reading the magnitude of the input signal, the second valid bit converter 520 stores the sign bit corresponding to the first bit, and divides the input signal by two operations to store the number of divisions. If the signal divided by 2 is larger than 512 bits, the division 2 operation is repeated. If not, the absolute value, the sign, and the number of divisions of the signal are output.

In this case, the second valid bit converter 520 converts the input signal to a positive number if the input signal is negative before performing the division operation.

The multiplier 560 performs multiplication by receiving each signal absolute value (divided two operation is performed and smaller than 512) output from the first valid bit converter 510 and the second valid bit converter 520. The multiplication value is transmitted to the valid bit shifter 540.

The adder 570 receives and adds the number of divisions (Exponent) output from the first valid bit converter 510 and the second valid bit converter 520, and then transmits them to the valid bit shifter 540.

The XOR gate 530 receives the respective codes output from the first valid bit converter 510 and the second valid bit converter 520, performs an XOR, and then transmits the codes to the bit inverter 550.

The effective bit shifter 540 multiplies the output value K of the adder 570 by 2 ^K and the output value of the multiplier 560 to transmit the multiplier 560 to the bit unit inverter 550.

The bit unit inverter 550 adds the effective value which is the output value of the effective bit shifter 540 and the code value which is the output value of the XOR gate 530, respectively, to obtain the final output value (the first valid bit converter 510 and the second valid bit converter). And a multiplication value of the signal inputted at 520.

Such a multiplier can improve the overall processing speed of the detector by enabling faster processing of the multiplication operation that the detector processes, and has an advantage of reducing complexity.

The embodiments of the present invention described above are not implemented only by the apparatus, but may be implemented through a program for realizing a function corresponding to the configuration of the embodiments of the present invention or a recording medium on which the program is recorded. From the description of the above-described embodiment can be easily implemented by those skilled in the art.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

According to the above configuration, the detection apparatus of the receiving end of the wireless communication system can reduce the implementation complexity for detecting the signal transmitted by the transmitting end, and at the same time, it can be expected to perform the effective detection.

Claims (11)

In the detector of the receiving end for receiving and detecting the transmission signal transmitted from the transmitting end of the wireless communication system of the multiple input and output method, A determinant calculation unit for obtaining a first detection signal using a channel transfer function and a first nulling matrix, and generating a determinant for obtaining a nulling matrix using the first detection signal and the channel transfer function; A first channel state calculator configured to update the first nulling matrix using the determinant and calculate a first channel state information value using the noise component included in the transmission signal, the channel transfer function, and the determinant ; And A second nulling matrix is obtained using the determinant and the transmitted signal, a second detection signal is obtained using the second nulling matrix and the channel transfer function, and the noise component, the channel transfer function, and the determinant are used. A second channel state calculator for calculating second channel state information; Detection apparatus of the receiving end comprising a. The method of claim 1, The determinant calculator, the first channel state calculator and the second channel state calculator includes a multiplier for performing a limited multiplication of a specific bit. The method of claim 2, The multiplication unit, Providing a first sign bit of the first signal received, and performing a first division operation on the bits included in the first signal until it is smaller than a specific number, thereby generating a first number of divisions and a final first residual value. A first valid bit converter to output; Providing a second sign bit of the received second signal, and performing a second division operation on the bits included in the second signal until it is smaller than a specific number, thereby generating the second division number and the final second residual value. A second valid bit converter to output; A multiplier that multiplies the first residual value by the second residual value; A multiplier for adding the first division number and the second division number; An XOR gate for performing an XOR (eXclusive-OR) on the first sign bit and the second sign bit; A valid bit shifter for generating a first bit using the output value of the adder and the output value of the multiplier; And A bit unit inverter for outputting a multiplication operation value of the first signal and the second signal by using the output value of the valid bit shifter and the output value of the XOR gate Detection apparatus of the receiving end comprising a. The method of claim 3, And the first valid bit converter converts the positive signal to a positive number when the first signal is negative before performing the first division operation. The method according to claim 3 or 4, And the second valid bit converter converts the positive signal to a positive number if the second signal is negative before performing the second division operation. The method according to any one of claims 1 to 4, And a soft decision decoder configured to receive the first detection signal and the second detection signal and perform soft decision decoding. The method of claim 2, The determinant calculator, the first channel state calculator and the second channel state calculator includes an adder and a subtractor using a rounding technique of pseudo code. The method of claim 7, wherein And a soft decision decoder configured to receive the first detection signal and the second detection signal and perform soft decision decoding. A multiplication apparatus used in a receiving end for receiving and detecting a transmission signal transmitted from a transmitting end of a multiple input / output wireless communication system, Providing a first sign bit of the first signal received, and performing a first division operation on the bits included in the first signal until it is smaller than a specific number, thereby generating a first number of divisions and a final first residual value. A first valid bit converter to output; Providing a second sign bit of the received second signal, and performing a second division operation on the bits included in the second signal until it is smaller than a specific number, thereby generating the second division number and the final second residual value. A second valid bit converter to output; A multiplier that multiplies the first residual value by the second residual value; A multiplier for adding the first division number and the second division number; An XOR gate for performing an XOR (eXclusive-OR) on the first sign bit and the second sign bit; A valid bit shifter for generating a first bit using the output value of the adder and the output value of the multiplier; And A bit unit inverter for outputting a multiplication operation value of the first signal and the second signal by using the output value of the valid bit shifter and the output value of the XOR gate Multiplication apparatus of the receiving end comprising a. The method of claim 9, And the first valid bit converter converts the positive signal to a positive number before performing the first division operation. The method according to claim 10 or 11, wherein And the second valid bit converter converts the positive signal to a positive number before performing the second division operation.

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