KR100763078B1 - How to erase NAND flash memory - Google Patents

Abstract

The present invention relates to a method of erasing a NAND flash memory, and includes a plurality of word lines, a common word line for providing a precharge voltage corresponding to the plurality of word lines, and a precharge voltage for operation. A method of erasing a NAND flash memory including a plurality of block selection switches connected to each other, the method comprising: applying a first voltage greater than an offset voltage than a bulk voltage for erasing as a control signal for operating the plurality of block selection switches ; 0V is applied to the first common word line connected to the first word line for erasing, and offset from the selection voltage higher than the bulk voltage to the second common word line connected to the second word line adjacent to the first word line. Applying a second voltage as large as the voltage; After a predetermined time, the first voltage applied to the control signal for operating the block select switch is changed to a bulk voltage, and the third common word line connected to the third word line not adjacent to the first word line is applied to the bulk voltage. Applying a selection voltage; And applying an erase voltage for cell erase to the substrate of the memory cell array.

Description

Method of erasing NAND flash memory {Method of erasing for nand flash memory}

1 is a conceptual diagram illustrating an erase operation of a conventional NAND flash memory.

2 is a conceptual diagram illustrating an erase operation of a NAND flash memory according to an embodiment of the present invention.

3 is a waveform diagram illustrating a voltage applied in the erase operation of FIG. 2.

* Explanation of symbols on the main parts of the drawings

10 to 50 and 110 to 150 word lines

The present invention relates to a method of erasing a NAND flash memory, and in particular, a cell of an unselected word line adjacent to a word line selected for erasing in a partial erase is erased or The present invention relates to a method of erasing a NAND flash memory capable of preventing interference.

When performing partial erasure on NAND flash memory, 0V is applied to the selected word line to cause Fowler-Nordheim (FN) tunneling due to the potential difference with the P well, and the unselected word line is floating. By self boosting by high voltage of P well, there is no voltage difference for FN tunneling to occur and it is not erased.

1 is a conceptual diagram illustrating an erase operation of a conventional NAND flash memory.

1 is a simplified view of a NAND flash memory. Referring to FIG. 1, a memory cell array formed on a P-well may be connected to a common drain terminal of each cell string in which a plurality of cells are connected in series. A plurality of bit lines BL1 to BLn are formed, and first to fifth word lines 10 to 50 are respectively formed to cross the bit lines BL1 to BLn and select memory cells, respectively.

을 인가한다. 이때

은 블록 선택 제어신호에 인가되는

보다 높은 전압이다. In the NAND flash memory, for example, to partially erase a cell connected to the third word line 30, 0V is applied to the third word line 30, and the word lines 10, 20, and 40 are otherwise. And 50) are

Is applied. At this time

Is applied to the block selection control signal.

Higher voltage.

이

보다 높은 전압이기 때문에, 블록 선택 스위치의 트랜지스터는 워드라인을

-

만큼 차지시키고 턴 오프되어 플로팅 시킨다.

this

Because of the higher voltage, the transistor of the block select switch

-

Charge and turn off to float.

Then, a high voltage is applied to the P-well of the substrate. Due to the high voltage of the P well, the memory cell connected to the third word line 30 is erased due to the FN tunneling caused by the voltage difference.

The other unselected word lines 10, 20, 40, and 50 are self-boosting, and the voltage rises by itself, thereby eliminating voltage difference enough to cause P well and FN tunneling. Does not become.

When the above erase method is used, a coupling effect exists between the third word line 30 to which 0V is applied and the second and fourth word lines 20 and 40 adjacent to the third word line. Cells connected to the second and fourth word lines 20 and 40 do not self-boost sufficiently to rise to a voltage sufficient to prevent FN tunneling.

In this case, when the boosting is insufficient and the voltage rise is insufficient, a voltage difference enough to cause the P well and the FN tunneling may occur, which may cause erasure. When a higher level potential is applied to the first, second, fourth and fifth word lines 10, 20, 40, and 50 that are not selected to solve the above problem, the third word line for erasing ( Other first and fifth word lines 10 and 50 that are not adjacent to 30 may be over-boosted to cause interference.

Accordingly, an aspect of the present invention is to provide a method of erasing a NAND flash memory such that cells which are not selected during partial erasing of the NAND flash memory are not erased or interfered by a coupling effect.

According to an aspect of the present invention for achieving the above technical problem, a method of erasing a NAND flash memory,

NAND flash including a plurality of word lines, a common word line corresponding to the plurality of word lines to provide a precharge voltage for operation, and a plurality of block selection switches connecting the word lines and the common word lines, respectively. CLAIMS 1. A method of erasing a memory, the method comprising: applying a first voltage greater than an offset voltage than a bulk voltage for erasing as a control signal for operating the plurality of block selection switches; 0V is applied to the first common word line connected to the first word line for erasing, and offset from the selection voltage higher than the bulk voltage to the second common word line connected to the second word line adjacent to the first word line. Applying a second voltage as large as the voltage; After a predetermined time, the first voltage applied to the control signal for operating the block select switch is changed to a bulk voltage, and the third common word line connected to the third word line not adjacent to the first word line is applied to the bulk voltage. Applying a selection voltage; And applying an erase voltage for cell erase to the substrate of the memory cell array.

The offset voltage is a difference between a voltage of the memory cell performing a normal boosting operation and a voltage of the memory cell performing a boosting operation due to a coupling effect between an adjacent second word line and a first word line. .

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

2 is a conceptual diagram illustrating an erase operation of a NAND flash memory according to an embodiment of the present invention.

2 is a simplified view of a NAND flash memory. Referring to FIG. 2, a memory cell array formed on a P-well includes a plurality of cells each connected to a common drain terminal of a cell string in which a plurality of cells are connected in series. The bit lines BL1 to BLn are formed, and the first to fifth word lines 110 to 150 are selected to cross the bit lines BL1 to BLn and select memory cells, respectively.

Node 1 to node 5 of each word line 110 to 150 and a block select switch operated by a global word line (GWL) and a block select control signal BLKWL are connected to each other.

+

가 인가된다. 이때

은 블록 선택 제어신호에 인가되는

보다 큰 전압이며,

은 커플링 효과에 의해 부스팅 되지 못하는 전압이다.In the memory cell array, for example, when the cells connected to the third word line 130 are to be erased, 0V is first applied to the global word line selected GWL connected to the third word line 130. A global word line (adjacent unselect GWL) connected to the second and fourth word lines adjacent to the third word line 130 is included in the global word line.

+

Is applied. At this time

Is applied to the block selection control signal.

Is a greater voltage,

Is the voltage that cannot be boosted by the coupling effect.

+

가 인가되면, 블록 선택 스위치가 턴 온 되고, 각각의 GWL은 노드 2 내지 노드 4와 연결된다. 그리고 노드 2 및 노드 4는 GWL의 전압레벨에 따라 프리차지 된다. 이때 상기

은

보다 큰 전압 레벨을 갖는다. 상기

은 메모리 셀이 정상적으로 부스팅 되었을 경우의 전압과, 커플링 효과에 의한 영향을 받아 부스팅 되었을 경우의 전압간의 차를 나타낸다.And block selection control signal BLKWL.

+

Is applied, the block select switch is turned on, and each GWL is connected to nodes 2-4. Nodes 2 and 4 are then precharged according to the voltage level of GWL. At this time

silver

Has a higher voltage level. remind

Denotes the difference between the voltage when the memory cell is normally boosted and the voltage when the memory cell is boosted under the influence of the coupling effect.

+

-

까지 프리차지가 되고, 이후에 블록 선택 스위치가 턴 오프되어 플로팅 된다. 이와 같이 동작하는 이유는 블록 선택 스위치인 트랜지스터의 특성에 의한 것으로, 앞서 말한 바와 같이

이

보다 큰 전압을 갖게 되므로, 노드 2 및 노드 4가

+

-

까지 프리차지 되는 동안은 블록 선택 스위치가 턴 온 상태로 유지되었다가, 노드 2 및 노드 4가

+

-

로 프리차지 되면 블록 선택 스위치가 턴오프 되는 것이다. 그리고 노드 2 및 노드 4가

+

-

로 프리차지 되기까지의 시간을

라 한다.Nodes 2 and 4 of the second and fourth word lines 120 and 140 may be

+

-

Precharge until the block select switch is turned off and floated. The reason for this operation is due to the characteristics of the transistor which is a block select switch.

this

Have a higher voltage, so node 2 and node 4

+

-

The block select switch remains on while precharged until Node 2 and Node 4

+

-

When precharged to, the block select switch is turned off. And node 2 and node 4

+

-

Time to precharge with

It is called.

로 낮추고, 또한 제 3 워드 라인(130)과는 인접하지 않은 제 1 및 제 5 워드 라인(110, 150)에 연결되는 GWL(non-adjacent unselected GWL)는

이 인가된다.When the nodes 2 and 4 of the second and fourth word lines 120 and 140 are floated, the voltage level applied to the block selection control signal BLKWL is adjusted.

Lower, and also connected to the first and fifth word lines 110 and 150 that are not adjacent to the third word line 130, the non-adjacent unselected GWL (GWL)

Is applied.

-

로 프리차지되고 이후에 블록 선택 스위치가 턴 오프되어 플로팅 된다. 이와 같이 되는 이유는 앞서 노드 2 및 노드 4가

+

-

로 프리차지된 후 플로팅 되는 이유를 설명한 것과 동일한 이유로 블록 선택 스위치를 이루고 있는 트랜지스터의 특성에 의한 것이다.Nodes 1 and 5 of the first and fifth word lines 110 and 150 are

-

Is precharged and then the block select switch is turned off and floated. The reason for this is that Node 2 and Node 4

+

-

This is due to the characteristics of the transistors forming the block select switch for the same reason as described above for being precharged and then floated.

+

-

가 프리차지된 후 플로팅 되며, 인접하지 않은 제 1 및 제 5 워드라인(110, 150)에는

-

가 프리차지된 후 플로팅 되는 상태가 된다.0V is applied to the third word line 130 and the second and fourth word lines 120 and 140 are adjacent to each other.

+

-

Is precharged and then floated, and the non-adjacent first and fifth word lines 110 and 150

-

Is pre-charged and then floated.

When a high voltage is applied to the P well in the above state, the cells of the third word line 130 are erased by the voltage difference with the P well.

가 미리 차지되어 있으므로, P웰과 소거가 일어나지 않는 전위차가 된다.In addition, even if the adjacent second and fourth word lines 130 are not sufficiently boosted by the coupling, the potential difference caused by the coupling may occur.

Since is occupied in advance, there is a potential difference between the P well and no erasure.

In addition, non-adjacent first and fifth word lines 130 are protected from being erased by boosting as in the conventional erasing process.

Therefore, only the word line desired to be erased can be selectively erased, and partial erasing can be performed without affecting other word lines.

The voltage applied in the erase method of the NAND flash memory according to the embodiment of the present invention as described above is as follows.

3 is a waveform diagram illustrating a voltage applied in the erase operation of FIG. 2.

+

만큼의 전압이

시간동안 인가되고, 인접한 선택되지 않은 워드 라인의 GWL에

+

을 인가됨으로써, 인접한 선택되지 않은 워드라인에

+

-

의 전압이 프리차지되도록 한다.As shown in FIG. 3, in the exemplary embodiment of the present invention, the block selection control signal BLKWL is first applied for partial erasure.

+

As much voltage

Applied for a period of time, to the GWL of an adjacent unselected word line.

+

Is applied to adjacent unselected word lines.

+

-

Allow the voltage to be precharged.

로 낮추어 인가되고, 인접하지 않고 선택되지 않은 워드라인의 GWL에

가 인가되어, 인접하지 않고 선택되지 않은 워드라인이

-

로 프리차지되도록 한다.Then again, the voltage level of the block selection control signal BLKWL

To the GWL of a wordline that is applied and is not contiguous and not selected.

Is applied so that nonadjacent and unselected word lines

-

To be precharged.

Subsequently, when a high voltage for erasing is applied to the P well, the selected word line is erased, and the remaining word lines are not erased.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the method of erasing a NAND flash memory according to the present invention solves a problem in which an unselected word line adjacent to a selected word line is incorrectly erased due to a coupling effect when performing a partial erase operation in units of words. Therefore, non-adjacent non-selected word lines are not over-boosted to enable effective partial erase.

Claims (2)

NAND flash including a plurality of word lines, a common word line corresponding to the plurality of word lines to provide a precharge voltage for operation, and a plurality of block selection switches connecting the word lines and the common word lines, respectively. In the memory erasing method, Applying a first voltage greater than an offset voltage than a bulk voltage for erasing as a control signal for operating the plurality of block selection switches; 0V is applied to the first common word line connected to the first word line for erasing, and offset from the selection voltage higher than the bulk voltage to the second common word line connected to the second word line adjacent to the first word line. Applying a second voltage as large as the voltage; After a predetermined time, the first voltage applied to the control signal for operating the block select switch is changed to a bulk voltage, and the third common word line connected to the third word line not adjacent to the first word line is applied to the bulk voltage. Applying a selection voltage; And Applying an erase voltage for cell erase to a substrate of the memory cell array; Erasing method of the NAND flash memory comprising a. The method of claim 1, The offset voltage is a NAND difference between a voltage of the memory cell performing a normal boosting operation and a voltage of the memory cell performing a boosting operation due to a coupling effect between an adjacent second word line and a first word line. How to erase flash memory.

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