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KR100772680B1 - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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KR100772680B1
KR100772680B1 KR1020060111539A KR20060111539A KR100772680B1 KR 100772680 B1 KR100772680 B1 KR 100772680B1 KR 1020060111539 A KR1020060111539 A KR 1020060111539A KR 20060111539 A KR20060111539 A KR 20060111539A KR 100772680 B1 KR100772680 B1 KR 100772680B1
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film
forming
semiconductor device
protective film
device manufacturing
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남기원
한기현
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 원하지 않는 기생 캐패시턴스 값을 증가시키는 도전패턴의 측벽보호막의 유전율을 낮추기 위한 반도체 소자 제조방법을 제공하기 위한 것으로, 본 발명은 기판 상에 복수개의 도전패턴을 형성하는 단계, 상기 도전패턴의 측벽에 이중층 측벽보호막을 형성하는 단계, 상기 도전패턴 상에 절연막을 형성하는 단계, 상기 절연막을 식각하여 상기 도전패턴 사이에 오픈부를 형성하는 단계, 상기 측벽보호막을 산화막으로 변화시키는 단계, 상기 오픈부를 매립하는 콘택 플러그를 형성하는 단계를 포함하고, 상기한 본 발명은 측벽보호 역할을 상실한 측벽보호막을 열공정을 실시하여 유전율이 낮은 산화막으로 변화시킴으로써 기생 캐패시턴스 값을 감소시켜 소자 신뢰성을 향상시키는 효과가 있다.The present invention is to provide a method for manufacturing a semiconductor device for lowering the dielectric constant of the sidewall protective film of the conductive pattern to increase the parasitic capacitance value, the present invention is to form a plurality of conductive patterns on the substrate, Forming a double layer sidewall protective film on sidewalls, forming an insulating film on the conductive pattern, etching the insulating film to form an open portion between the conductive patterns, changing the sidewall protective film to an oxide film, and Forming a buried contact plug, the present invention is effective to improve the device reliability by reducing the parasitic capacitance value by changing the sidewall protective film which lost the sidewall protection role to an oxide film having a low dielectric constant by performing a thermal process have.

Description

반도체 소자 제조방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

도 1a 내지 도 1f는 본 발명의 바람직한 실시예에 따른 반도체 소자 제조방법을 설명하기 위한 공정 단면도.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

11 : 반도체 기판 12 : 제1절연층11 semiconductor substrate 12 first insulating layer

13 : 폴리실리콘전극 14 : 금속전극13 polysilicon electrode 14 metal electrode

15 : 비트라인하드마스크 16A : 제1측벽보호막15: bit line hard mask 16A: first side wall protective film

17A : 제2측벽보호막 18 : 제2절연층17A: second side wall protective film 18: second insulating layer

19 : 하드마스크패턴 20 : 스토리지 노드 콘택홀19: hard mask pattern 20: storage node contact hole

21 : 스토리지 노드 콘택 플러그21: Storage Node Contact Plug

본 발명은 반도체 제조 기술에 관한 것으로, 특히 기생캐패시터 감소를 위한 반도체 소자의 절연막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for forming an insulating film of a semiconductor device for reducing parasitic capacitors.

반도체 소자의 고집적화에 따라 라인(Line) 간 공간(Spacing)의 감소 및 워드라인(Word Ling)과 비트라인(Bit Line) 또는 캐패시터(Cpatpcitor)의 사이를 분리시키는 각각의 절연막 두께가 지속적으로 감소하고 있다. As semiconductor devices become more integrated, the thickness of each insulating layer that reduces the spacing between lines and separates between word lines and bit lines or capacitors is continuously reduced. have.

위와 같이, 절연막의 두께 감소는 원하지 않는 기생 캐패시턴스(Capacitance) 값을 증가시키고 이로 인해 소자 특성이 열화되는 문제점이 있다. As described above, there is a problem in that the thickness reduction of the insulating layer increases the parasitic capacitance value, which causes deterioration of device characteristics.

기생 캐패시턴스 값이 증가되는 문제점을 해결하기 위해 절연막의 두께를 증가시키거나 낮은 유전율을 가지는 막을 사용하고 있다. 그러나, 단순히 절연막의 두께만을 증가시킬 경우 각 라인 간의 공간 감소와 이에 따른 갭필(Gap Fill) 마진 감소를 유발할 수 있고, 낮은 유전율을 가지는 막은 소자 측면에서 완전하게 검증되지 않은 문제점과 낮은 증착 스텝 커버리지(Step Coverage)에 의한 갭필 마진 감소를 유발하는 문제점이 있다.In order to solve the problem that the parasitic capacitance value is increased, an increase in the thickness of the insulating film or a film having a low dielectric constant is used. However, simply increasing the thickness of the insulating film can cause a decrease in the space between lines and thus a gap fill margin, and a film having a low dielectric constant has not been fully verified in terms of device and low deposition step coverage. There is a problem that causes a gap fill margin decrease by step coverage.

또한, 패턴(Pattern) 간의 거리가 점점 가까워지고 그 사이에 위치한 막은 스토리지 노드 콘택홀 식각시 절연 마진(margin)을 확보하기 위한 다양한 질화막(Nitride)으로 구성되는데, 이러한 막 사용으로 불필요한 유전율 상승을 초래하여 기생 캐패시턴스를 증가시키는 문제점이 있다. 질화막은 유전 상수 k ~ 6 정도의 높은 유전율 값을 가진다. In addition, the distance between the patterns becomes closer and closer, and the intervening films are composed of various nitrides to secure an insulation margin during etching of the storage node contact holes. There is a problem that increases the parasitic capacitance. The nitride film has a high dielectric constant value of about k-6.

특히, 스토리지 노드 콘택홀 식각시 비트라인패턴의 측면 어택(Attack)을 방지하기 비트라인패턴의 측벽에 형성되는 측벽보호막으로 질화막을 사용하는데 이때, 스토리지 노드 콘택홀 식각이 완료되는 시점에서는 필요하지 않은 질화막에 의 해 스토리지 노드 콘택과 비트라인 사이에 원하지 않는 기생 캐패시턴스 값을 증가시키는 문제점이 있다.In particular, a nitride layer is used as a sidewall protection layer formed on the sidewall of the bitline pattern to prevent side attack of the bitline pattern when the storage node contact hole is etched, which is not necessary when the storage node contact hole etching is completed. The nitride film has a problem of increasing an unwanted parasitic capacitance value between the storage node contact and the bit line.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 원하지 않는 기생 캐패시턴스 값을 증가시키는 도전패턴의 측벽보호막의 유전율을 낮추기 위한 반도체 소자 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device for reducing the dielectric constant of the sidewall protective film of the conductive pattern to increase the unwanted parasitic capacitance value.

본 발명에 의한 반도체 소자 제조방법은 기판 상에 복수개의 도전패턴을 형성하는 단계, 상기 도전패턴의 측벽에 이중층 측벽보호막을 형성하는 단계, 상기 도전패턴 상에 절연막을 형성하는 단계, 상기 절연막을 식각하여 상기 도전패턴 사이에 오픈부를 형성하는 단계, 열공정을 진행하는 단계, 상기 오픈부를 매립하는 콘택 플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.The method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a plurality of conductive patterns on a substrate, forming a double layer sidewall protective film on the sidewalls of the conductive pattern, forming an insulating film on the conductive pattern, and etching the insulating film. And forming an open portion between the conductive patterns, performing a thermal process, and forming a contact plug filling the open portion.

특히, 측벽보호막을 형성하는 단계는, 상기 도전패턴의 측벽에 질화막을 형성하는 단계, 상기 질화막 상에 불순물막을 형성하는 단계를 포함하는 것을 특징으로 한다.In particular, the forming of the sidewall protective film may include forming a nitride film on the sidewall of the conductive pattern and forming an impurity film on the nitride film.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명 의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 1a 내지 도 1f는 본 발명의 바람직한 실시예에 따른 반도체 소자 제조방법에 관한 것이다.1A to 1F are directed to a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

도 1a에 도시된 바와 같이, 반도체 기판(11) 상에 제1절연층(12)을 형성한다. 여기서, 제1절연층(12)은 예컨대 산화막(Oxide)으로 형성하고 단층 또는 다층으로 형성될수 있다. 또한, 제1절연층(12) 형성 전에 게이트패턴 및 랜딩 플러그 콘택(Landing Plug Contact;LPC)이 형성될 수 있다.As shown in FIG. 1A, a first insulating layer 12 is formed on the semiconductor substrate 11. Here, the first insulating layer 12 may be formed of, for example, an oxide and may be formed in a single layer or multiple layers. In addition, a gate pattern and a landing plug contact (LPC) may be formed before the first insulating layer 12 is formed.

이어서, 제1절연층(12) 상에 복수개의 비트라인패턴(Bit Line Pattern)을 형성한다. 여기서, 비트라인패턴은 폴리실리콘전극(13), 금속전극(14)과 비트라인하드마스크(15)의 적층구조로 형성된다. 특히, 금속전극(14)은 예컨대 텅스텐(Ｗ) 또는 텅스텐실리사이드(ＷSix)로 형성하고, 비트라인하드마스크(15)는 예컨대 질화막(Nitride)으로 형성할 수 있다.Subsequently, a plurality of bit line patterns are formed on the first insulating layer 12. Here, the bit line pattern is formed in a stacked structure of the polysilicon electrode 13, the metal electrode 14, and the bit line hard mask 15. In particular, the metal electrode 14 may be formed of, for example, tungsten or tungsten silicide, and the bit line hard mask 15 may be formed of, for example, a nitride film.

이어서, 비트라인패턴의 측벽에 제1측벽보호막(16)을 형성한다. 여기서, 제1측벽보호막(16)은 후속 스토리지 노드 콘택홀 식각시 비트라인패턴의 측면 어택(Attack)을 방지하기 위한 것이다. Subsequently, the first sidewall protection layer 16 is formed on the sidewall of the bit line pattern. The first sidewall protection layer 16 may prevent side attack of the bit line pattern during subsequent storage node contact hole etching.

또한, 제1측벽보호막(16)은 질화막으로 형성하는데, 제1측벽보호막(16)은 형성하는 공정은 400℃∼900℃의 온도에서 100Ｔ∼600Ｔ의 압력으로 SiH4 및 NH3가스를 사용하여 실시한다. 그리고, SiH4는 5sccm∼30sccm, NH3는 1000sccm∼9000sccm의 유량으로 플로우(Flow)시켜서 형성한다.In addition, the first side wall protective film 16 is formed of a nitride film. The process of forming the first side wall protective film 16 is performed by using SiH 4 and NH 3 gas at a pressure of 100 T to 600 T at a temperature of 400 ° C. to 900 ° C. Conduct. SiH 4 is formed by flowing at a flow rate of 5 sccm to 30 sccm and NH 3 at a flow rate of 1000 sccm to 9000 sccm.

도 1b에 도시된 바와 같이, 제1측벽보호막(16) 상에 제2측벽보호막(17)을 형성한다. 여기서, 제2측벽보호막(17)은 제1측벽보호막(16)과 동일하게 후속 스토리지 노드 콘택홀 식각시 비트라인패턴의 측면 어택(Attack)을 방지하기 위한 것이다. As shown in FIG. 1B, a second side wall protection film 17 is formed on the first side wall protection film 16. Here, the second sidewall protection layer 17 is to prevent side attack of the bit line pattern during subsequent storage node contact hole etching in the same manner as the first sidewall protection layer 16.

제2측벽보호막(17)은 불순물막으로 형성하되, 불순물은 인(P, Phosporus) 또는 보론(B, Boron)을 사용한다. 제2측벽보호막(17)을 형성하는 공정은 제1측벽보호막(16)과 동일한 조건 즉, 400℃∼900℃의 온도에서 100Ｔ∼600Ｔ의 압력으로 실시한다. 또한, SiH4와 불순물의 혼합가스 즉, SiH4와 인(P) 또는 보론(B)의 혼합가스를 사용하여 실시하고, 여기서 불순물은 전체 유량의 1％∼5％가 되도록 혼합하여 형성한다.The second sidewall protection film 17 is formed of an impurity film, and the impurity uses phosphorus (P, Phosporus) or boron (B, Boron). The process of forming the second side wall protective film 17 is carried out under the same conditions as the first side wall protective film 16, i.e., at a temperature of 100 to 600 T at a temperature of 400 to 900 ° C. In addition, it is performed using a mixed gas of SiH 4 and impurities, that is, a mixed gas of SiH 4 and phosphorus (P) or boron (B), wherein the impurities are formed by mixing so as to be 1% to 5% of the total flow rate.

제1 및 제2측벽보호막(16, 17)의 총 두께는 50Å∼200Å가 되도록 형성하고, 특히 제2측벽보호막(17)은 20Å∼100Å의 두께로 형성한다.The total thickness of the first and second side wall protective films 16 and 17 is 50 kPa to 200 kPa, and the second side wall protective film 17 is formed to a thickness of 20 kPa to 100 kPa.

도 1c에 도시된 바와 같이, 제1 및 제2측벽보호막(16, 17)을 식각하여 비트라인패턴의 측벽에만 잔류하도록 식각한다. 예컨대, 전면식각을 실시하여 식각한다.As shown in FIG. 1C, the first and second sidewall protection layers 16 and 17 are etched to remain only on the sidewalls of the bit line pattern. For example, etching is performed by performing full surface etching.

이하, 비트라인패턴의 측벽에 잔류하는 제1 및 제2측벽보호막(16, 17)을 '제1 및 제2측벽보호막(16A, 17A)'라고 한다.Hereinafter, the first and second sidewall protection films 16 and 17 remaining on the sidewalls of the bit line pattern are referred to as 'first and second sidewall protection films 16A and 17A'.

이어서, 비트라인패턴 사이를 채우면서 비트라인패턴 상에 제2절연층(18)을 형성한다. 여기서, 제2절연층(18)은 제1절연층(12)과 동일한 물질로 형성할 수 있 고 예컨대 산화막으로 형성한다.Subsequently, the second insulating layer 18 is formed on the bit line pattern while filling the space between the bit line patterns. Here, the second insulating layer 18 may be formed of the same material as the first insulating layer 12, for example, an oxide film.

이어서, 제2절연층(18) 상에 하드마스크패턴(19)을 형성한다. 여기서, 하드마스크패턴(19)은 스토리지 노드 콘택을 위한 오픈부 예정지역이 오픈되어 제2절연층(18) 식각시 식각마스크역할을 하기 위한 것이다. 하드마스크패턴(19)은 제2절연층(18) 상에 하드마스크층을 형성하고, 하드마스크층 상에 감광막을 코팅한 후 노광 및 현상으로 감광막패턴을 형성하고, 감광막패턴을 식각마스크로 하드마스크층을 식각하여 형성한다. Subsequently, a hard mask pattern 19 is formed on the second insulating layer 18. In this case, the hard mask pattern 19 is intended to serve as an etch mask when the planned open area for the storage node contact is opened to etch the second insulating layer 18. The hard mask pattern 19 forms a hard mask layer on the second insulating layer 18, coats the photoresist film on the hard mask layer, forms a photoresist pattern by exposure and development, and hardens the photoresist pattern as an etch mask. The mask layer is formed by etching.

도 1d에 도시된 바와 같이, 하드마스크패턴(19)을 식각마스크로 제2 및 제1절연층(18, 12)을 식각하여 스토리지 노드 콘택(Storage Node Contact;SNC)을 위한 오픈부(20)를 형성한다.As illustrated in FIG. 1D, the second and first insulating layers 18 and 12 are etched using the hard mask pattern 19 as an etch mask to open the opening 20 for a storage node contact (SNC). To form.

도 1e에 도시된 바와 같이, 제1 및 제2측벽보호막(16A, 17A)을 산화막으로 변화시킨다. 이때, 산화막은 제1측벽보호막(16A)의 일부 및 제2측벽보호막(17A)을 변화시키는 것이 바람직하다. As shown in Fig. 1E, the first and second sidewall protective films 16A and 17A are changed to oxide films. At this time, the oxide film preferably changes part of the first side wall protection film 16A and the second side wall protection film 17A.

이를 위해 열공정을 실시한다. 여기서, 열공정은 적어도 O2를 포함하는 분위기에서 실시한다. 예컨대, O2 단독 또는 N2/O2 분위기에서 450℃∼900℃의 온도로 실시한다. 이로 인해, 제2측벽보호막(17A)에 혼합된 불순물 즉, 인 또는 보론이 활성화되어 제1측벽보호막(16A)에 영향을 주어서 성질을 변형시키게 되는데, 불순물막인 제2측벽보호막(17A)을 형성한 후 열공정을 실시함으로써 제1측벽보호막(16A)의 성질변형이 극대화된다. 즉, 불순물 없이 열공정을 실시하면 성질변형되는 정도 가 수Å에 불과하지만, 불순물막 형성 후 열공정을 실시함으로써 아래 표와 같이 수십Å의 질화막 성질변형이 일어나는 것을 알 수 있다. 또한, 불순물막 형성 후 열공정을 실시하는 공정은 질화막만 노출되어 산화시키는 것보다 더 큰 효과를 얻을 수 있다.To do this, a thermal process is carried out. Here, the tear Chung carried out in an atmosphere containing at least O 2. For example, it is performed at a temperature of 450 ° C to 900 ° C in O 2 alone or in an N 2 / O 2 atmosphere. As a result, impurities mixed in the second sidewall protection film 17A, that is, phosphorus or boron, are activated to affect the first sidewall protection film 16A, thereby modifying the properties. The second sidewall protection film 17A, which is an impurity film, is modified. After the formation, the thermal process is performed to maximize the deformation of the first side wall protective film 16A. In other words, when the thermal process is performed without impurities, the degree of property deformation is only a few orders of magnitude. However, the thermal process after the formation of the impurity film shows that several tens of nitride film property deformation occurs as shown in the following table. In addition, the process of performing the thermal process after the formation of the impurity film can obtain a greater effect than exposing and oxidizing only the nitride film.

열공정을 실시함으로써 제1 및 제2측벽보호막(16A, 17A)이 산화막으로 변화된다. 제1측벽보호막(16A)의 변화정도는 아래 표에서 자세히 알 수 있다.By performing the thermal process, the first and second side wall protective films 16A and 17A are changed into oxide films. The degree of change of the first sidewall protective film 16A can be seen in detail in the table below.

#01# 01 #02# 02 #03# 03 #04# 04 #05# 05 #06# 06 질화막두께Nitride film thickness 130Å130Å 140Å140Å 열공정(시간)Thermal process (hours) 30분30 minutes 40분40 minutes 50분50 minutes 30분30 minutes 40분40 minutes 50분50 minutes 잔류질화막두께Residual Nitride Film Thickness 57Å57Å 48Å48Å 33Å33Å 64Å64Å 52Å52Å 43Å43Å 손실두께[Å]Loss thickness 73Å73Å 82Å82Å 97Å97 yen 76Å76Å 88Å88Å 97Å97 yen

상기 표1을 보면, 질화막이 130Å이고 열공정이 30분 진행될 경우 질화막은 73Å이 산화막으로 변화되어 57Å이 잔류하고, 50분 진행될 경우 질화막은 97Å이 산화막으로 변화되어 33Å이 잔류하는 것을 알 수 있다.Referring to Table 1, it can be seen that when the nitride film is 130 ms and the thermal process is performed for 30 minutes, the nitride film is 73 ms and is changed to an oxide film and 57 ms remains.

위와 같이, 열공정에 의해 제1 및 제2측벽보호막(16A, 17A)이 유전율이 낮은 산화막으로 변화되고 특히, 열공정 시간이 길어 질수록 산화막으로 변화되는 두께거 더 많아 진다. 따라서, 측벽보호막의 유전율이 낮아짐으로써 불필요한 기생 캐패시턴스를 감소시킬 수 있다. As described above, the first and second sidewall protective films 16A and 17A are changed to oxide films having a low dielectric constant by the thermal process, and in particular, the longer the thermal process time is, the more the thickness is changed to the oxide film. Therefore, unnecessary parasitic capacitance can be reduced by decreasing the dielectric constant of the sidewall protective film.

위의 열공정에 의해 변화된 제1측벽보호막의 일부 및 제2측벽보호막을 도면부호 17B, 잔류하는 제1측벽보호막을 도면부호 16B로 나타내었다.A part of the first side wall protective film and the second side wall protective film changed by the above thermal process are indicated by reference numeral 17B and the remaining first side wall protective film by reference numeral 16B.

도 1f에 도시된 바와 같이, 오픈부(20)를 매립하는 스토리지 노드 콘택 플러그(SNC Plug:Storage Node Contact Plug)(21)를 형성한다. 여기서, 스토리지 노드 콘택 플러그(21)는 오픈부(20)를 채우도록 도전물질을 형성하고 물리적식각을 실시하여 오픈부(20) 내부에만 잔류시킴으로써 형성한다. As illustrated in FIG. 1F, a storage node contact plug (SNC Plug) 21 filling the open part 20 is formed. Here, the storage node contact plug 21 is formed by forming a conductive material to fill the open portion 20 and performing physical etching to remain only in the open portion 20.

물리적식각은 평탄화 공정으로 예컨대 전면식각 또는 화학적기계적연마(Chemical Mechanical Polishing;CMP) 공정으로 실시하되, 식각타겟을 제2절연층(18) 상부가 드러나도록 실시하여 스토리지 노드 콘택 플러그(21)를 형성함과 동시에 하드마스크패턴(19)을 제거할 수 있다.Physical etching may be performed by planarization, for example, by surface etching or chemical mechanical polishing (CMP), and the etching target may be exposed to expose the upper portion of the second insulating layer 18 to form the storage node contact plug 21. At the same time, the hard mask pattern 19 can be removed.

또한, 도전물질은 예컨대 폴리실리콘(Poly Silicon)으로 형성할 수 있다.In addition, the conductive material may be formed of, for example, polysilicon.

상기한 본 발명은 비트라인패턴의 측벽보호막을 질화막과 불순물막의 이중층 제1 및 제2측벽보호막(16A, 17A)으로 형성하고, 스토리지 노드 콘택홀 형성 후 열공정을 실시하여 제1 및 제2측벽보호막(16A, 17A)을 산화막으로 변화시킴으로써 유전율을 낮추어 기생 캐패시턴스의 값을 낮출 수 있는 장점이 있다. 이때, 산화막은 제1측벽보호막(16A)의 일부 및 제2측벽보호막(17A)을 변화시키는 것이 바람직하다. According to the present invention, the sidewall passivation layer of the bit line pattern is formed of the double layer first and second sidewall passivation layers 16A and 17A of the nitride layer and the impurity layer, and the thermal process is performed after forming the storage node contact hole. By changing the protective films 16A and 17A into oxide films, the dielectric constant can be lowered to lower the parasitic capacitance. At this time, the oxide film preferably changes part of the first side wall protection film 16A and the second side wall protection film 17A.

한편, 본 실시예는 비트라인패턴의 측벽보호막에서의 응용을 설명한 것으로, 본 발명의 기술적 사상은 비트라인패턴의 측벽보호막 외에 게이트패턴과 같은 다른 도전패턴에도 응용될 수 있다.On the other hand, the present embodiment has described the application in the sidewall protective film of the bit line pattern, the technical idea of the present invention can be applied to other conductive patterns such as gate pattern in addition to the sidewall protective film of the bit line pattern.

이렇듯, 본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.As such, although the technical idea of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상기한 본 발명은 측벽보호 역할을 상실한 측벽보호막을 열공정을 실시하여 유전율이 낮은 산화막으로 변화시킴으로써 기생 캐패시턴스 값을 감소시켜 소자 신뢰성을 향상시키는 효과가 있다.The present invention has the effect of reducing the parasitic capacitance value by improving the device reliability by changing the sidewall protective film which lost the sidewall protection role to an oxide film having a low dielectric constant by performing a thermal process.

Claims (11)

기판 상에 복수개의 도전패턴을 형성하는 단계;Forming a plurality of conductive patterns on the substrate; 상기 도전패턴의 측벽에 이중층 측벽보호막을 형성하는 단계;Forming a double layer sidewall protective film on sidewalls of the conductive pattern; 상기 도전패턴 상에 절연막을 형성하는 단계;Forming an insulating film on the conductive pattern; 상기 절연막을 식각하여 상기 도전패턴 사이에 오픈부를 형성하는 단계;Etching the insulating layer to form an open portion between the conductive patterns; 열공정을 진행하는 단계; 및Performing a thermal process; And 상기 오픈부를 매립하는 콘택 플러그를 형성하는 단계Forming a contact plug to bury the open portion 를 포함하는 반도체 소자 제조방법.Semiconductor device manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 측벽보호막을 형성하는 단계는,Forming the sidewall protective film, 상기 도전패턴의 측벽에 질화막을 형성하는 단계; 및Forming a nitride film on sidewalls of the conductive pattern; And 상기 질화막 상에 불순물막을 형성하는 단계Forming an impurity film on the nitride film 를 포함하는 것을 특징으로 하는 반도체 소자 제조방법.Semiconductor device manufacturing method comprising a. 제2항에 있어서,The method of claim 2, 상기 질화막을 형성하는 단계는,Forming the nitride film, 400℃∼900℃의 온도에서 100Ｔ∼600Ｔ의 압력으로 SiH4 및 NH3가스를 사용하여 실시하는 것을 특징으로 하는 반도체 소자 제조방법.A method of manufacturing a semiconductor device, characterized by carrying out using SiH 4 and NH 3 gas at a pressure of 100T to 600T at a temperature of 400 ° C to 900 ° C. 제3항에 있어서,The method of claim 3, 상기 SiH4는 5sccm∼30sccm, NH3는 1000sccm∼9000sccm의 유량을 사용하는 것을 특징으로 하는 반도체 소자 제조방법.Said SiH 4 is 5sccm ~ 30sccm, NH 3 is 1000sccm ~ 9000sccm flow rate using a semiconductor device manufacturing method characterized in that. 제2항에 있어서,The method of claim 2, 상기 불순물막을 형성하는 단계는,Forming the impurity film, 400℃∼900℃의 온도에서 100Ｔ∼600Ｔ의 압력으로 SiH4와 불순물의 혼합가스를 사용하여 실시하는 것을 특징으로 하는 반도체 소자 제조방법.A method of manufacturing a semiconductor device, comprising using a mixed gas of SiH 4 and impurities at a pressure of 100T to 600T at a temperature of 400 ° C to 900 ° C. 제5항에 있어서,The method of claim 5, 상기 불순물은 인 또는 보론을 사용하되, 상기 혼합가스 전체 유량의 1％∼5％가 되도록 혼합하는 것을 특징으로 하는 반도체 소자 제조방법.The impurity is phosphorus or boron, but the semiconductor device manufacturing method characterized in that the mixture so as to be 1% to 5% of the total flow rate of the mixed gas. 제2항에 있어서,The method of claim 2, 상기 측벽보호막은 질화막과 불순물막의 총 두께를 50Å∼200Å으로 형성하고, 상기 불순물막은 20Å∼100Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자 제조방법. Wherein said sidewall protective film is formed to have a total thickness of a nitride film and an impurity film of 50 mW to 200 mW, and said impurity film is formed to a thickness of 20 mW to 100 mW. 제1항 내지 제7항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 7, 상기 열공정을 진행하는 단계에서,In the step of performing the thermal process, 상기 질화막의 일부 및 상기 불순물막을 산화시키는 것을 특징으로 하는 반도체 소자 제조방법.A part of the nitride film and the impurity film are oxidized. 제8항에 있어서,The method of claim 8, 상기 열공정은 적어도 O2를 포함하는 분위기에서 450℃∼900℃의 온도로 실시하는 것을 특징으로 하는 반도체 소자 제조방법.The thermal process is carried out at a temperature of 450 ℃ to 900 ℃ in an atmosphere containing at least O 2 characterized in that the semiconductor device manufacturing method. 제9항에 있어서,The method of claim 9, 상기 열공정은 O2 분위기 또는 N2/O2 분위기에서 실시하는 것을 특징으로 하는 반도체 소자 제조방법.The thermal process is a semiconductor device manufacturing method characterized in that carried out in O 2 atmosphere or N 2 / O 2 atmosphere. 제1항에 있어서,The method of claim 1, 상기 도전패턴은 비트라인패턴 또는 게이트패턴인 것을 특징으로 하는 반도체 소자 제조방법.The conductive pattern is a semiconductor device manufacturing method, characterized in that the bit line pattern or gate pattern.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020001144A (en) * 2000-06-26 2002-01-09 박종섭 Method of manufacturing a semiconductor device
KR20040079171A (en) * 2003-03-06 2004-09-14 주식회사 하이닉스반도체 Method for manufacturing semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020001144A (en) * 2000-06-26 2002-01-09 박종섭 Method of manufacturing a semiconductor device
KR20040079171A (en) * 2003-03-06 2004-09-14 주식회사 하이닉스반도체 Method for manufacturing semiconductor device

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