KR100808079B1 - Device for generating and distributing clock signals - Google Patents

Abstract

The present invention provides a clock generation and distribution device capable of generating and distributing a high precision clock signal even in a high frequency band of several kilohertz or more, and each voltage controlled oscillator oscillates in the same phase even in a high frequency band of 20 GHz. An object of the present invention is to provide a distributed VCO-type clock generation and distribution device that can generate a clock signal of a desired frequency and distribute the high frequency clock signal to each part of the chip more stably.

An LC resonant voltage controlled oscillator is employed as each voltage controlled oscillator, and the inductor component of the interconnection wiring between the oscillation nodes is made relatively small, or the LC resonant oscillator is oscillated synchronously by injection synchronization, so that each LC resonant voltage is controlled. Allow the controlled oscillator to reliably oscillate in phase.

Description

CLOCK SIGNAL GENERATING AND DISTRIBUTING APPARATUS}

1 is a diagram showing a distributed VCO type clock generation distribution method according to the present invention and a first embodiment of the present invention.

2A is a diagram illustrating a configuration example of an LC resonance oscillator.

2B is a diagram showing the relationship between the resistance of the wiring and the stability of oscillation of the LC resonator oscillator.

3A is a diagram showing a second embodiment of the present invention.

3B is a diagram showing a modification 1 of the second embodiment.

3C is a diagram showing a modification 2 of the second embodiment.

4 is a diagram showing a third embodiment of the present invention.

5A is a diagram showing a fourth embodiment of the present invention.

5B is a first modification of the fourth embodiment.

6 is a second modification of the fourth embodiment.

7 is a third modification of the fourth embodiment.

8A is a diagram showing an example of the configuration of an LC resonator oscillator having an input terminal for coupling.

8B is a diagram showing a configuration example 1 of the buffer circuit used in the present invention.

8C is a diagram showing a configuration example 2 of the buffer circuit used in the present invention.

9 is a diagram showing a conventional configuration example for realizing clock signal distribution.

10 is a diagram illustrating a conventional distributed VCO type clock generation distribution method in which wiring is one-dimensional.

Fig. 11 is a diagram showing a conventional distributed VCO clock generation distribution method in which the wiring is matrix type.

<Explanation of symbols for the main parts of the drawings>

20: LC resonant voltage controlled oscillator

30: wiring

31: resistance element

32: signal line

33: ground wire

39: ground plane

40: buffer

51: voltage controlled oscillator using ring oscillator

60: divider

70: phase comparator (PFD), charge pump (CP) and low pass filter (LF)

80: clock tree

81: buffer

90: circuit block

100: PLL

120: LC resonant voltage controlled oscillator with coupling input terminal

The present invention relates to a high speed interface circuit, a processor, and an apparatus for generating and distributing a high speed and high precision clock signal for an analog circuit or a digital circuit requiring a high frequency clock signal.

In recent years, with the rapid progress of semiconductor integrated circuits, the frequency of the clock signal has been continuously improved. As a result, the timing constraints required for clock signals are becoming strict. In addition, as the LSI increases in size, it is difficult to distribute a high precision clock signal to each part of the chip.

9 shows an example of a conventional configuration for realizing clock signal distribution. In the configuration example shown in FIG. 9, a PLL 100 including a voltage controlled oscillator (VCO) 50, a divider 60, a phase comparator (PFD), a charge pump (CP), and a low pass filter (LF) 70 is provided. The clock signal generated by the C1 is transmitted to the circuit block 90 through the clock tree 80 composed of the buffer 81. By the way, in this example, the timing precision and voltage amplitude of a clock signal deteriorate in the process of passing through the clock tree 80 which provided the buffer 81 in multiple stages. In particular, this problem becomes prominent in the high frequency band.

The method proposed by the following patent document 1 as a means of solving this problem is shown to FIG. 10 and FIG. In this example, a number of voltage controlled oscillators (VCOs) 51 composed of ring oscillators are disposed in each part of the chip. The oscillation nodes of these voltage controlled oscillators (VCOs) 51 are coupled by wiring conductors in one dimension in FIG. 10 and in a matrix in FIG. In addition, in order to control the oscillation frequency of each voltage controlled oscillator (VCO) 51, the voltage controlled oscillator (VCO) 51, the divider 60, the phase comparator (PFD), the charge pump (CP), and the low pass. The control signal generated by the PLL composed of the filter (LF) 70 is distributed to each voltage controlled oscillator (VCO) 51. Hereinafter, the device by this method is called "a distributed VCO type clock generation distribution device."

In the distributed VCO type clock generation distribution method of FIGS. 10 and 11, a clock signal is generated by a ring oscillator. However, in general, ring oscillators are weak in power supply noise and have low precision in generated clock signals, and thus are not suitable for use in high frequency bands of several kilohertz or more.

<Patent Document 1>

Japanese Patent Laid-Open No. 11-74762

Therefore, one of the problems to be solved by the present invention is to provide a distributed clock signal generation and distribution device capable of generating and distributing a high precision clock signal even in a high frequency band of several kilohertz or more.

In addition, although the wiring which couples between the oscillation nodes of voltage-controlled oscillator VCO is thought to be several hundred micrometers or more in length, in the high frequency band which reaches 20 GHz, the inductor component also cannot be ignored. For this reason, there arises a problem that each voltage controlled oscillator VCO does not oscillate in the same phase and cannot generate a clock signal of a desired frequency.

Therefore, another problem to be solved by the present invention is that each voltage-controlled oscillator (VCO) oscillates in the same phase, thereby generating a clock signal of a desired frequency, and the high frequency clock signal is more stably The present invention provides a distribution device for generating a distributed VCO clock signal to be distributed to a portion.

According to the present invention, in the distributed VCO type clock generation distribution apparatus, an LC resonant voltage controlled oscillator (hereinafter simply referred to as an LC resonant oscillator) is employed as each voltage controlled oscillator VCO, not a ring oscillator.

Then, an element such as a resistor, a buffer, or a circuit is inserted between the oscillation nodes of the LC resonator oscillator, thereby making the inductor component of the connection wiring relatively small. Alternatively, each LC resonator oscillator is oscillated in the same phase by using a wiring having a structure with a small inductor component in the wiring connecting the oscillation nodes of the LC resonator oscillator. Or the structure which arrange | positions one or more LC resonator oscillators which are not connected other than this wiring on the wiring which mutually connects LC resonator oscillator is employ | adopted.

Further, according to the present invention, the LC resonator oscillator is synchronously oscillated by the injection synchronization.

Fig. 1 shows each LC resonator oscillator by inserting a resistance element between the distributed VCO type clock generation distribution device according to the present invention employing an LC resonator oscillator as the voltage controlled oscillator (VCO) and the oscillation node of each LC resonator oscillator 20. The first embodiment of the present invention in which the influence of the inductance of the wiring between the oscillation nodes of (20) is reduced is shown. In the figure, although the oscillation nodes of each LC resonator oscillator 20 are connected by one-dimensional wiring, it is also possible to connect by mesh-type wiring.

In the present embodiment, the LC resonator oscillator # 1 (20) and the LC resonator oscillator # 2 (20) having the same physical configuration, which supply the clocks to the circuit block 91 and the circuit block 92 through the buffer 81, respectively, LC resonator oscillator # 0 (20) having the same physical configuration as those of these LC resonator oscillators 20, and a divider 60 which feeds back the output thereof and divides it, the divided output of the divider 60 and the phase of the reference clock. A phase comparator (PFD) for supplying a bias signal for oscillation control to each of the LC resonator oscillators 20 and a charge pump (CP) and a low pass filter (LF) 70 by comparison, and each LC resonator oscillator ( It consists of a resistance element 31 inserted between the oscillation nodes of 20).

On the other hand, it is apparent to those skilled in the art that the on-resistance of a transistor or the like can be used instead of the resistance element 31. In addition, although the LC resonator oscillator # 0 (20) constituting the PLL does not distribute the clock to any circuit block in the illustration, it is possible to arrange the PLL close to the circuit block for distributing the clock. It is possible to distribute the clock from the resonator oscillator # 0 (20) to its circuit block.

2A shows an example of the configuration of the LC resonator oscillator 20.

As shown, the source of the PMOS transistor 21 and the source of the PMOS transistor 22 are commonly connected to a power supply. The drain of the PMOS transistor 21 and the drain of the PMOS transistor 22 are connected to the drain of the NMOS transistor 23 and the drain of the NMOS transistor 24, respectively, and the gate of the PMOS transistor 21 and the PMOS transistor 22, respectively. The gate of is connected to the gate of the NMOS transistor 23 and the gate of the NMOS transistor 24, respectively. The source of the NMOS transistor 23 and the source of the NMOS transistor 24 are commonly connected to the drain of the NMOS transistor 28, the source of the NMOS transistor 28 is connected to the earth, and to the gate of the NMOS transistor 28. Bias signal # 1, which determines the common mode potential of the oscillation output node, is input. The drain of the PMOS transistor 21, the gate of the PMOS transistor 22, the gate of the PMOS transistor 21, and the drain of the PMOS transistor 22 are connected to each other.

An inductance element 27 is connected between the drain of the PMOS transistor 21 and the drain of the PMOS transistor 22, and one electrode of the variable capacitor 25 is connected to the drain of the PMOS transistor 21. One electrode of the variable capacitor 26 is connected to the drain of the 22, and the oscillation frequency of the LC resonance oscillator 20 is connected to the other electrode of the variable capacitor 25 and the variable capacitor 26. The bias signal # 2 for controlling the signal is input. This bias signal # 2 corresponds to the bias signal shown in FIG.

Next, the resistance value of the resistance element 31 shown in FIG. 1 will be described with reference to FIG. 2B.

FIG. 2B is a graph of simulation results of oscillation frequencies in the model in which two LC resonator oscillators 20 are connected by a wiring having a resistor and an inductor, and the resistance value R of the wiring between the LC resonator oscillators 20 and FIG. The relationship between the stability of the oscillation of the LC resonator oscillator 20 is shown.

In other words, the oscillation was stably at a frequency slightly exceeding 20 GHz, but the oscillation frequency was rapidly changed at an inductor value of 0.32 nH at a resistance value of R = 15 ohm and 0.67 nH at a resistance value of R = 75 ohm.

According to this graph, when the resistance value is high for the inductor component of the wiring, oscillation tends to be stable. From another viewpoint, the oscillation becomes unstable over a certain inductor value as the inductor component of the wiring increases with respect to a certain resistance value. Therefore, one factor that determines the stability of oscillation is the ratio of resistance and inductance. In addition, it can be seen that the oscillation can be stabilized if the inductor component of the wiring can be substantially reduced with respect to a certain resistance value.

When the length of the wiring becomes longer, the inductance and resistance of the wiring usually increase in proportion to the length, so that the value of the resistance to be inserted between the LC resonator oscillators 20 in the first embodiment is determined according to the length of the wiring. .

3A illustrates the physical structure of reducing the inductance of the wiring 30 connecting between the oscillation nodes of the LC resonator oscillator # 1 (20) and the LC resonator oscillator # 2 (20), which is the second embodiment of the present invention. The structure of the wiring 30 connecting between the oscillation nodes of the LC resonator oscillator # 1 (20) and the LC resonator oscillator # 2 (20) has a small inductance in the wiring portion, as can be seen from the description of FIG. 2B. It is preferable. Thus, as shown in the figure, the distance between the signal line and the ground plane connected to the fixed potential is shortened, and the ground lines connected to the fixed potential are similarly arranged on both sides of the signal line.

3B and 3C are modified examples 1 and 2 of the wiring structure shown in FIG. 3A. In Modification 1 of FIG. 3B, the signal line is very close to the ground plane. Instead of modification 1 of FIG. 3B, the signal line itself may be a micro strip line.

In Modification 2 of FIG. 3C, ground planes are disposed on both sides of the signal line. Instead of the modification 2 of FIG. 3C, the signal line itself may be a strip line.

4 shows a third embodiment of the present invention. In the present embodiment, the auxiliary LC resonator oscillator # A1 (20) and the LC resonator oscillator # A2 (20) having the same configuration as the LC resonator oscillator # 1 (20) and the like, the LC resonator oscillator # 1 (20), LC resonator oscillator # It arrange | positions between 2 (20) and LC resonator oscillator # 3 (20), and connects each oscillation node. The electrical length between each oscillating node can then be halved compared to the absence of the auxiliary LC resonator oscillator # A1 (20) and LC resonator oscillator # A2 (20), thereby reducing the inductance between the oscillation nodes. have.

Fig. 5A shows a fourth embodiment of the present invention in which the LC resonator oscillator is synchronously oscillated by injection synchronization. In this embodiment, the LC resonator oscillator # 2 (20) is connected between the oscillation nodes of the LC resonator oscillator # 1 (20) and the oscillation node of the LC resonator oscillator # 2 (20) via the buffer 40 to oscillate by injection synchronization. The LC resonator oscillator # 1 (20) and the LC resonator oscillator # 2 (20) are oscillated at the same frequency in phase.

In this embodiment, since the wiring between the oscillation nodes is divided by the buffer, as in the case of the fourth embodiment shown in FIG. 4, the LC resonator oscillator # 1 (20) and the LC resonator oscillator # 2 (20). The wiring length affecting the oscillation of is reduced, so that the inductance between the oscillation nodes can be reduced.

5B is a first modification of the configuration shown in FIG. 5A and oscillates the LC resonator oscillator # 1 (20) using at least one LC resonator oscillator # 2 120 having an input terminal for coupling. The node is connected to the coupling input terminal of LC resonator oscillator # 2 (120) having the input terminal for coupling via buffer 40 and the oscillation signal of LC resonator oscillator # 1 (20) is transmitted to LC resonator oscillator # 2 (120). It is injected into the LC resonator oscillator # 2 (120) to oscillate at the same frequency in phase with the LC resonator oscillator # 1 (20).

6 is a 2nd modification which provided two or more buffers 40 in FIG. 5B. Of course, also in the structure of FIG. 5A, multiple buffer 40 can be provided. The second modification has the effect of reducing the attenuation of the signal by shortening the substantial wiring length, for example, when the wiring length between the LC resonator oscillator # 1 (20) and the LC resonator oscillator # 2 (120) to be connected is long. Can be obtained.

7 is a 3rd modification and couples with these oscillation nodes using at least 1 set of LC resonator oscillator # 1 (120) and LC resonator oscillator # 2 (120) which respectively have an input terminal for coupling. The ring input terminals are alternately connected symmetrically through the buffer 40. With this symmetrical configuration, a higher precision clock can be distributed to each circuit block. Thus, for example, this modification is applied to the synchronization between LC resonator oscillator # 1 120 and LC resonator oscillator # 2 120 that supplies clocks for circuit blocks that require clocks with high precision for operation between circuit blocks. Is effective.

8A is an example of the configuration of an LC resonator oscillator 120 having an input terminal for coupling, and a series circuit of the PMOS transistor 21 and the NMOS transistor 23 of the LC resonator oscillator 20 shown in FIG. 2A. And a series circuit of the PMOS transistor 210, the NMOS transistor 230, and a series circuit of the PMOS transistor 220 and the MOS transistor 240 in parallel with respect to the series circuit of the PMOS transistor 22 and the NMOS transistor 24, respectively. Coupling input terminal # 1 for injecting an oscillation signal as a differential signal into each of the connection point of the PMOS transistor 210 and the NMOS transistor 230 and the connection point of the PMOS transistor 220 and the NMOS transistor 240. 291) and coupling input terminal # 2 (292).

Fig. 8B shows a structural example 1 of a buffer circuit suitable for use in the present invention. As shown, the drain of the NMOS transistor 411 and the drain of the NMOS transistor 412 are connected to the power supply through the resistor element 413 and the resistor element 414, respectively, and the source is common of the NMOS transistor 415. It is connected to the drain. The source of the NMOS transistor 415 is connected to earth, and a bias signal for determining the common mode potential of the buffer output is input to the gate.

An input terminal is provided at the gate of the NMOS transistor 411 and a gate of the NMOS transistor 412, and an output terminal is provided at the drain of the NMOS transistor 411 and the drain of the NMOS transistor 412.

8C shows a structural example 2 of a buffer circuit suitable for use in the present invention. As shown, a series circuit of the PMOS transistor 421 and the NMOS transistor 423 to which the gates are connected, and a series circuit of the PMOS transistor 422 and the NMOS transistor 424 to which the gates are connected similarly, is a power supply and an NMOS. The drains of the transistors 425 are connected in parallel. The source of the NMOS transistor 425 is connected to earth, and a bias signal for determining the common mode potential of the buffer output is input to the gate.

An input terminal is provided at the gate connection point of the PMOS transistor 421 and the NMOS transistor 423, and the gate connection point of the PMOS transistor 422 and the NMOS transistor 424, and the drain of the PMOS transistor 421 and the NMOS transistor 423 are respectively provided. An output terminal is provided at the connection point of the drain and the connection point of the drain of the PMOS transistor 422 and the drain of the NMOS transistor 424.

2A, 8A, 8B, and 8C are merely circuit examples, and it is apparent to those skilled in the art that various modifications can be employed in addition to the examples.

(Appendix 1) An LC resonant voltage controlled oscillator is used as the voltage controlled oscillator of the PLL, and an LC resonant voltage controlled oscillator having the same configuration as the LC resonant voltage controlled oscillator is arranged in each part of the chip, and the LC The oscillation node of the resonant voltage controlled oscillator is connected by one-dimensional wiring or mesh type wiring, and the oscillation frequency control signal generated in the PLL is distributed to the respective LC resonant voltage controlled oscillators, thereby providing the LC resonant voltage. And a LC resonant voltage controlled oscillator arranged in each part of the chip to distribute a clock signal from the oscillation node to a corresponding circuit, respectively.

(Supplementary Note 2) The clock according to Supplementary Note 1, wherein the inductance of the wiring connecting the oscillation nodes of the LC resonant voltage controlled oscillators is a value at which the LC resonant voltage controlled oscillators oscillate in the same phase. Device for generating and distributing signals.

(Supplementary Note 3) A clock signal generation and distribution apparatus according to Supplementary Note 2, wherein a resistance element is inserted between oscillation nodes of the LC resonant voltage controlled oscillator connected to each other.

(Supplementary Note 4) The clock signal generation and distribution apparatus according to Supplementary Note 3, wherein the resistance of the resistance element is caused by the on resistance of the transistor.

(Appendix 5) In accordance with the physical structure of the wiring, the inductance of the wiring connecting the oscillation nodes of the respective LC resonant voltage controlled oscillators is set to a value at which the respective LC resonant voltage controlled oscillators oscillate in the same phase. An apparatus for generating and distributing a clock signal according to Appendix 2.

(Supplementary Note 6) The physical structure of the wiring is provided in Supplementary Note 5, wherein a ground plane or a ground line connected to a fixed potential is arranged in the vicinity of the wiring connecting between the oscillation nodes of the LC resonant voltage controlled oscillator. Apparatus for generating and distributing clock signals.

(Supplementary Note 7) The clock signal generation and distribution apparatus according to Supplementary Note 5, wherein the wiring is a microstrip line.

(Supplementary Note 8) The clock signal generating and distributing apparatus according to Supplementary Note 5, wherein the wiring is a strip line.

(Appendix 9) LC resonant voltage controlled oscillator whose oscillation frequency is controlled by the oscillation frequency control signal generated by the PLL, wherein the oscillation node is LC resonant voltage control connected by the one-dimensional wiring or mesh-shaped wiring. An apparatus for generating and distributing a clock signal according to Appendix 2, comprising an LC resonant voltage controlled oscillator connected to the wiring between the oscillation nodes of the oscillator and not connected to the other circuit without going through the wiring. .

(Appendix 10) An LC resonant voltage controlled oscillator is used as a voltage controlled oscillator of the PLL, and an LC resonant voltage controlled oscillator having the same configuration as the LC resonant voltage controlled oscillator is disposed in each part of the chip, and in the PLL By distributing the generated oscillation frequency control signal to each LC resonant voltage controlled oscillator and simultaneously oscillating each LC resonant voltage controlled oscillator by injection synchronization, a clock signal is generated by the LC resonant voltage controlled oscillator. And an LC resonant voltage controlled oscillator arranged in each part of the chip distributes clock signals from the oscillation node to corresponding circuits, respectively.

(Appendix 11) At least one buffer is connected between the oscillation nodes of the LC resonant voltage controlled oscillator by one-dimensional wiring or mesh-shaped wiring, and the wirings connected between the oscillation nodes of the respective LC resonant voltage controlled oscillators. Inserting and synchronizing the LC resonant voltage controlled oscillator on the output side of the buffer with the LC resonant voltage controlled oscillator on the input side of the buffer by injection synchronization.

(Appendix 12) The LC resonant voltage controlled oscillator on the output side of at least one of the buffers has a coupling input terminal, and the wiring on the output side of the buffer is connected to the coupling input terminal instead of the oscillation node. An apparatus for generating and distributing a clock signal according to Appendix 11.

(Appendix 13) Using at least one set of LC resonant voltage controlled oscillators having coupling input terminals together, each of the oscillating nodes of its LC resonant voltage controlled oscillator and the coupling input terminal of the opposing side is placed between the buffers. A clock signal generation and distribution device according to Appendix 11, which is connected by inserted wiring.

By the apparatus of the present invention, generation and distribution of clock signals with high accuracy can be realized. In addition, in the ultra-high frequency band of the 20 GHz class, each LC resonator oscillator can be oscillated at the same phase and at the same frequency.

Claims (10)

In the device for generating and distributing a clock signal, LC resonant voltage controlled oscillators; A divider for feeding back the outputs of the LC resonant voltage controlled oscillators; A phase comparator (PFD), a charge pump (CP), and a low pass filter (LF) for supplying a bias signal for oscillation control to each of the LC resonant voltage controlled oscillators by performing phase comparison between the divided output of the frequency divider and a reference clock. A PLL comprising; Resistance elements inserted between the oscillation nodes of the respective LC resonant voltage controlled oscillators; Buffers supplying a circuit clock of each LC resonant voltage controlled oscillator to a circuit Including; The LC resonant voltage controlled oscillator is used as the voltage controlled oscillator of the PLL, and the LC resonant voltage controlled oscillator having the same configuration as the LC resonant voltage controlled oscillator is arranged in each part of the chip, and the respective LC resonant voltages are arranged. The oscillation node of the control oscillator is connected by one-dimensional wiring or mesh-type wiring, and the oscillation frequency control signal generated in the PLL is distributed to each LC resonant voltage controlled oscillator, thereby clocking the LC resonant voltage controlled oscillator. And an LC resonant voltage controlled oscillator arranged in each part of the chip for distributing a clock signal from the oscillation node to a corresponding circuit, respectively. The clock signal generation according to claim 1, wherein the inductance of the wiring connecting the oscillation node of each LC resonant voltage controlled oscillator is a value at which each LC resonant voltage controlled oscillator oscillates in the same phase. And dispensing device. 3. The clock signal generation and distribution device according to claim 2, wherein a resistance element is inserted between oscillation nodes of the LC resonant voltage controlled oscillator connected to each other. The oscillation node of each LC resonant voltage controlled oscillator is connected by arranging a ground plane or a ground line connected to a fixed potential in the vicinity of a wiring connecting the oscillation nodes of the LC resonant voltage controlled oscillator. And the inductance of the wiring is set so that the LC resonant voltage controlled oscillators oscillate in the same phase. delete The LC resonant voltage controlled oscillator according to claim 2, wherein the oscillation frequency is controlled by the oscillation frequency control signal generated by the PLL, wherein the oscillation node is connected by the one-dimensional wiring or mesh-shaped wiring. And an LC resonant voltage controlled oscillator connected to the wiring between the oscillation nodes of the voltage controlled oscillator and not connected to the other circuit without passing through the wiring. In the device for generating and distributing a clock signal, LC resonant voltage controlled oscillators; A divider for feeding back the outputs of the LC resonant voltage controlled oscillators; A phase comparator (PFD), a charge pump (CP), and a low pass filter (LF) for supplying a bias signal for oscillation control to each of the LC resonant voltage controlled oscillators by performing phase comparison between the divided output of the frequency divider and a reference clock. A PLL comprising; Resistance elements inserted between the oscillation nodes of the respective LC resonant voltage controlled oscillators; Buffers supplying a circuit clock of each LC resonant voltage controlled oscillator to a circuit Including; Using the LC resonant voltage controlled oscillator as the voltage controlled oscillator of the PLL, an LC resonant voltage controlled oscillator having the same configuration as the LC resonant voltage controlled oscillator is disposed in each part of the chip, thereby generating the oscillation generated in the PLL. By distributing a frequency control signal to each LC resonant voltage controlled oscillator and simultaneously oscillating each LC resonant voltage controlled oscillator by injection synchronization, a clock signal is generated by the LC resonant voltage controlled oscillator to generate the clock signal. And an LC resonant voltage controlled oscillator disposed in each part of the apparatus distributes clock signals from the oscillation node to corresponding circuits, respectively. 8. The at least one buffer of claim 7, wherein the oscillation node of the LC resonant voltage controlled oscillator is connected by one-dimensional wiring or mesh type wiring, and is connected between the oscillation nodes of each LC resonant voltage controlled oscillator. Inserting and synchronizing the LC resonant voltage controlled oscillator on the output side of the buffer with an injection synchronization with the LC resonant voltage controlled oscillator on the input side of the buffer. 9. An LC resonant voltage controlled oscillator on the output side of at least one of the buffers having a coupling input terminal, wherein wiring at the output side of the buffer is connected to the coupling input terminal instead of an oscillation node. And a clock signal generation and distribution device. The method of claim 8, wherein at least one set of LC resonant voltage controlled oscillators having a coupling input terminal together is used to buffer the oscillating node of its LC resonant voltage controlled oscillator and the coupling input terminal of the opposing side, respectively. A clock signal generation and distribution device, characterized in that connected by wiring inserted therebetween.

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