KR100834915B1 - Embedded system for testing using PC and method - Google Patents

Abstract

The present invention relates to an embedded system and method for determining normal operation using a PC.

Embedded system according to the present invention, the selection unit for receiving a selection signal from the PC to select any one of the SPI or JTAG mode; A controller which receives a test signal from the PC through a mode selected by the selection unit and outputs a control signal for performing a command corresponding to the test signal; And a flash memory controlled by a control signal applied from the controller to store data included in a test signal applied from the PC or to delete data stored at a corresponding address.

Embedded Systems, Flash Memory, PCs, SPI, JTAG

Description

Embedded system to test using PC and method

1 is a block diagram illustrating an embedded system for testing using a prior art inspection equipment.

2 is a block diagram illustrating an embedded system for testing using prior art JTAG.

3 is a block diagram illustrating an embedded system for testing using a PC in accordance with the present invention.

Figure 4 is a flow chart showing the flow of the test method of the embedded system using a PC according to the present invention.

<Description of Symbols for Major Parts of Drawings>

300: embedded system 301: PC

310: selection unit 320: SPI interface

330: JTAG interface 340: control unit

350: flash memory

The present invention relates to an embedded system for testing using a PC and a method thereof, and more particularly, to an embedded system and a test that can perform a variety of tests in a simple test by testing an embedded flash memory using a commercial PC. It is about a method.

In recent years, the degree of integration of a circuit into a single chip is rapidly increasing with the development of design process technology along with the demand for high performance, high functionality, and miniaturization of a system.

Accordingly, since modules such as memory mounted outside the chip are also embedded in one chip, the most important and difficult part in the test of the highly integrated chip is the test of the embedded memory.

Then, the embedded system according to the prior art will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating an embedded system for testing using a conventional inspection apparatus, and FIG. 2 is a block diagram illustrating an embedded system for testing using a conventional JTAG.

First, as shown in FIG. 1, the embedded system 100 for testing by using the inspection apparatus of the prior art, the interface 110 electrically connected to the outside, the signal applied from the interface 110 The control unit 120 analyzes and outputs a control signal, and a flash memory 130 controlled by the control unit 120.

At this time, the inspection equipment 101 is used to test whether the embedded system 100 operates normally.

The inspection apparatus 101 is designed to test only the embedded system 100 and includes an address, data, chip enable, write enable, and output enable ( A test signal S1 to Sn formed of an output enable) is applied to the embedded system 100.

The embedded system 100 is electrically connected to the test equipment 101 through the interface 110 and is operated by test signals S1 to Sn applied from the test equipment 101.

If the test equipment 101 outputs test signals S1 to Sn for testing an operation for storing data or deleting stored data in the flash memory 130, the test equipment 101 and the test equipment 101 may be output. The electrically connected interface 110 transmits the test signals S1 to Sn to the controller 120 as signals such as addresses, data, and chip enable (ce).

The control unit 120 receiving the test signal through the interface 110 analyzes the test signal, and adds, data, programs, and deletes to control the flash memory 130. Outputs a control signal consisting of commands such as (erase).

In this case, if the test signals S1 to Sn are signals instructing a command to store data at an address designated by the test signals S1 to Sn, the controller 120 may determine that the flash memory 130 is in a state of the flash memory 130. The control signal includes an address signal add indicating the address, data to be stored, and a storage signal prog for storing. The flash memory 130 receiving the control signal stores the data at a corresponding address.

If the test signals S1 to Sn are signals instructing a command for deleting data stored at an address designated by the test signals S1 to Sn, the controller 120 may control the flash memory 130. A control signal including an address signal add indicating an address to be deleted and an erase signal (erase) for deleting stored data is transmitted, thereby deleting data stored at the corresponding address of the flash memory 130.

In addition, the same method may be used to delete the entire area of the flash memory 130 instead of deleting only one selected address among the addresses of the flash memory 130.

However, since the test of the embedded system 100 using the test equipment 101 as described above requires expensive test equipment 101 separately manufactured to test the embedded system 100, the test cost is increased. There was a problem in that only the test limited to the inspection equipment 101 should be performed.

In addition, as shown in FIG. 2, the embedded system 200 for determining whether to operate normally using a conventional JTAG includes an interface 210, a controller 220, and a flash memory 230.

In this case, the JTAG 201 is used to test whether the embedded system 200 operates normally.

The JTAG 201 may test an address, data, chip enable, write enable, and output enable to test only the embedded system 200. The test signal S made of the same is applied to the embedded system 100 in the form of a serial JTAG command.

The embedded system 200 is electrically connected to the JTAG 201 through the interface 210, and stores and deletes data at a corresponding address by a test signal S applied from the JTAG 201. Perform the command of.

At this time, the inspection process using the JTAG 201 proceeds to the same process as the process for testing the embedded system 100 using the inspection equipment 100 of FIG. 1 to test the embedded system 200.

However, in the test of the embedded system 200 using the JTAG 201, a separate JTAG 201 equipment is required to test whether the embedded system 200 is normally operated, and thus the test cost increases. As a test using only the JTAG 201 equipment, there was a problem that a limitation occurs in the test method of the flash memory 230 mounted in the embedded system 200.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to test whether the embedded system is operating normally using a commercial PC, thereby reducing the test cost and performing various tests desired by the inspector. To provide an embedded system and its test method.

An embedded system for testing using a PC according to the present invention for achieving the above object, the selection unit for receiving a selection signal from the PC to select any one of the SPI or JTAG mode; A controller which receives a test signal from the PC through a mode selected by the selection unit and outputs a control signal for performing a command corresponding to the test signal; And a flash memory controlled by a control signal applied from the controller to store data included in a test signal applied from a PC or to delete data stored at a corresponding address.

Further, in the embedded system according to the present invention, the PC determines whether the command to be tested is normally performed by receiving feedback of the corresponding address of the flash memory according to the test signal after performing the command according to the test signal. Characterized in that.

In the embedded system according to the present invention, the control unit is an embedded system, characterized in that the test signal is serially applied through the SPI interface when the SPI mode is selected by the selection unit.

In the embedded system according to the present invention, the control unit is an embedded system, characterized in that the test signal is received as a JTAG command through a JTAG interface when the JTAG mode is selected by the selection unit.

In the embedded system according to the present invention, the control unit outputs a control signal for storing data at a corresponding address of the flash memory when the test signal applied from the PC is a signal for storing data in the flash memory. When the test signal is a signal for deleting data stored in a flash memory, a control signal for deleting data of a corresponding address of the flash memory may be output.

In addition, the test method of the embedded system using a PC according to the present invention, a) receiving a selection signal from the PC; b) selecting one of the SPI and JTAG modes according to the selection signal applied from step a); c) receiving a test signal from the PC through the mode selected in step b); d) generating a control signal for performing a command corresponding to the test signal applied in step c); e) storing data at a corresponding address of the flash memory or deleting data stored at the corresponding address controlled by the control signal generated in step d); And f) feeding back the information of the address stored or deleted in step e) to the PC to determine whether it is normal.

In the test method of the embedded system according to the present invention, when the SPI mode is selected in the step b), the test signal of the serial is received from the PC in the step c).

In the test method of the embedded system according to the present invention, when the JTAG mode is selected in step b), the test signal of the JTAG command is received from the PC in step c).

Further, in the test method of the embedded system according to the present invention, the step d) is for storing data at a corresponding address of the flash memory when the test signal applied from the PC is a signal for storing data in the flash memory. The control signal is output, and when the test signal is a signal for deleting data stored in the flash memory, a control signal for deleting data of a corresponding address of the flash memory is output.

The above objects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, whereby those skilled in the art may easily implement the technical idea of the present invention. There will be.

In addition, in describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

Next, an embedded system and a method thereof for testing using a PC according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating an embedded system for testing using a PC in accordance with the present invention.

As shown in FIG. 3, the embedded system 300 according to the present invention includes a selector 310, an SPI interface 320 connected to the outside, and a JTAG interface 330. ), The controller 340, and the flash memory 350.

The embedded system 300 having the above configuration uses a commercial PC 301 to check whether it is operating normally.

In this case, the commercial PC 301 may use a variety of PCs, such as a personal PC and a PC used in the production line generally used, a selection signal for selecting an interface to be electrically connected to the embedded system 300 S0 and test signals S1 and S2 programmed by the inspector are transmitted to the embedded system 300.

The selection unit 310 of the embedded system 300 is connected to the PC 301, the SPI interface 320, and the JTAG interface 330, and receives the selection signal S0 from the PC 301 to receive the SPI. Any one of the interface 320 or the JTAG interface 330 selects an interface mode corresponding to the selection signal SO.

If the SPI interface 320 is selected by the selection signal S0 in the selection unit 310, the PC 301 may serially set an address, data, chip enable, write enable, output enable, and the like. The test signal S1 applied in a serial form is transmitted to the SPI interface 320.

The SPI interface 320 receiving the test signal S1 transmits the applied test signal S1 to the controller 340 electrically connected thereto.

In addition, when the JTAG interface 330 is selected by the selection signal S0 in the selection unit 310, the PC 301 may perform address, data, chip enable, write enable, output enable, and the like. The test signal S2, which is a JTAG command of, is transmitted to the JTAG interface 330.

The controller 340 is connected to the SPI interface 320, the JTAG interface 330, and the flash memory 350, and transmits a test signal S1, which is transmitted through the SPI interface 320 or the JTAG interface 330. Analyzing the S2) and storing the data at the addresses specified by the test signals S1 and S2 in the flash memory 350 or deleting the data stored at the designated addresses. A control signal composed of a command for testing whether the memory 350 is normally operated is output.

At this time, if the test signal (S1, S2) is a signal indicating a command for storing data at the address of the flash memory 350 specified by the test signal (S1, S2), the control unit 340 corresponds to A control signal including an address signal add indicating an address, data to be stored, and a storage signal prog to be stored is transmitted to the flash memory 350.

Then, the flash memory 350 receiving the control signal for storing data at the designated address stores the data at the corresponding address. That is, if the flash memory 350 receives a control signal including an address '000F', data '55A', and a 'prog' signal of a storage command, the '000F' of the flash memory 350 The data '55A' is stored.

In addition, if the test signals S1 and S2 are signals instructing a command for deleting data stored in the flash memory 350 designated by the test signals S1 and S2, the controller 340 A control signal including an address signal add indicating a corresponding address and an erase signal erase indicating a delete command is transmitted to the flash memory 350.

Then, the flash memory 350 receiving the control signal for deleting the data stored at the designated address deletes the data stored at the address. That is, when the address is '00FF' and the flash memory 350 receives the control signal including the 'erase' signal of the delete command, the data stored in the '00FF' of the flash memory 350 is deleted. And only '0000' remains.

In the same manner, a command for deleting the entire area of the flash memory 130 may be performed instead of deleting only one selected address among the addresses of the flash memory 130.

After completing the above operation, if the address information of the flash memory 350 specified by the test signal (S1, S2) is fed back to the PC 301 through the control unit 340, the PC (301) ) May determine whether the embedded system 300 is normally operated by checking whether the command for storing or deleting the flash memory 350 is normally performed based on the feedback information.

Accordingly, the test of the embedded system 300 using a PC according to the present invention, by directly testing the performance of the operation of storing and deleting the flash memory 350 mounted on the embedded system 300 using a commercial PC, There is an advantage that can reduce the test cost than the test required a separate inspection equipment.

In addition, by using a commercial PC, the tester can directly program a test command for testing the flash memory 350, and thus, there are advantages in that various types of tests can be performed.

Next, a test method of an embedded system using a PC according to the present invention will be described in more detail with reference to FIG. 4.

Figure 4 is a flow chart showing the flow of the test method of the embedded system using a PC according to the present invention.

As shown in FIG. 4, in the method of testing an embedded system using a PC according to the present invention, first, a selection signal is received from a PC for testing an embedded system (S401).

One of the SPI mode and the JTAG mode is selected by the applied selection signal (S402).

In this case, when the mode selected by the selection signal is the SPI mode, the serial test signal is received from the PC (S403). When the selected mode is the JTAG mode, the test signal of the JTAG command is received from the PC (S404).

A control signal is generated to perform a command corresponding to the test signal applied through the selected mode (S405).

If the test signal applied from the PC is a signal indicating a command for storing data in a flash memory of an embedded system for testing, a control signal for storing data at a corresponding address of the flash memory is generated, and the test signal Is a signal representing a command for deleting data stored in the flash memory, a control signal for deleting data of a corresponding address of the flash memory is generated.

As described above, the control signal generated in step S405 is controlled to store data at a corresponding address of the flash memory or to delete data stored at the corresponding address (S406).

The embedded system is tested by determining whether the embedded system is normally operated by feeding back the information of the address stored or deleted in the step S406 to the PC (S407).

Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and various substitutions, modifications, and changes within the scope without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It will be appreciated that such substitutions, changes, and the like should be considered to be within the scope of the following claims.

As described above, the embedded system and the method for testing using a PC according to the present invention, by using a commercial PC to test the normal operation of the embedded system, the test cost is reduced and the various types of testers want The effect is that you can perform the test.

Claims (9)

In the embedded system for testing the normal operation using a PC, A selection unit which receives a selection signal from the PC and selects one of SPI and JTAG modes; A controller which receives a test signal from the PC through a mode selected by the selection unit and outputs a control signal for performing a command corresponding to the test signal; And A flash memory controlled by a control signal applied from the controller to store data included in a test signal applied from a PC or to delete data stored at a corresponding address; Embedded system comprising a. The method of claim 1, And the PC determines whether the command to be tested is normally executed by receiving feedback of the corresponding address of the flash memory according to the test signal after performing the command according to the test signal. The method of claim 1, The control unit is an embedded system, characterized in that for receiving the test signal serially through the SPI interface when selecting the SPI mode. The method of claim 1, The controller may be configured to receive the test signal through a JTAG command through a JTAG interface when the JTAG mode is selected by the selector. The method of claim 1, The control unit, When the test signal applied from the PC is a signal for storing data in a flash memory, a control signal for storing data at a corresponding address of the flash memory is output, and the test signal is a signal for deleting data stored in the flash memory. And outputting a control signal for deleting data of the corresponding address of the flash memory. In the test method of the embedded system for determining the normal operation using a PC, a) receiving a selection signal from a PC; b) selecting one of the SPI and JTAG modes according to the selection signal applied from step a); c) receiving a test signal from the PC through the mode selected in step b); d) generating a control signal for performing a command corresponding to the test signal applied in step c); e) storing data at a corresponding address of the flash memory or deleting data stored at the corresponding address controlled by the control signal generated in step d); And f) determining whether the embedded system is operating normally by feeding back the information of the address stored or deleted in step e) to the PC; Embedded system test method comprising a. The method of claim 6, If the SPI mode is selected in the step b), in the step c) is the embedded system test method characterized in that receiving a serial test signal from the PC. The method of claim 6, If the JTAG mode is selected in the step b), in the step c), the test signal of the JTAG command is received from the PC. The method of claim 6, In step d), when the test signal applied from the PC is a signal for storing data in a flash memory, a control signal for storing data at a corresponding address of the flash memory is output, and the test signal is stored in the flash memory. And a control signal for deleting data of a corresponding address of the flash memory when the data is a signal for deleting data.

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