KR100838483B1 - Gate etching method of semiconductor device - Google Patents

Abstract

The present invention is to provide a gate etching method that can prevent the loss of the silicon substrate during the gate etching process of the semiconductor device, the present invention to prepare a substrate formed with a gate insulating film and a gate conductive film, and the gate conductive A method of etching a semiconductor device includes forming a gate pattern by etching a film, oxidizing a portion of the gate pattern to form a thermal oxide film, and removing the thermal oxide film.

Description

Gate etching method of semiconductor device {METHOD FOR ETCHING A GATE IN SEMICONDUCTOR DEVICE}

1A to 1E are cross-sectional views illustrating a gate etching method of a semiconductor device according to the related art.

2A to 2D are cross-sectional views illustrating a gate etching method of a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 110: substrate

11: gate oxide film

12, 112: polycrystalline silicon film

13, 114: photosensitive film pattern

14 silicon oxide film

15: natural oxide film

113: antireflection film

115: thermal oxide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a gate etching method of a semiconductor device, and more particularly, a gate etching method comprising a polycrystalline silicon film.

A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) used as a driving element in a semiconductor device usually uses a polycrystalline silicon film as its gate. Such a gate is formed through a dry etching process using plasma-reacted reaction gas, which is recognized as an important element in the manufacturing process.

1A to 1E are cross-sectional views illustrating a gate etching method according to the related art.

First, as shown in FIG. 1A, the gate oxide film 11 and the polycrystalline silicon film 12 having a predetermined thin thickness are sequentially formed on the silicon substrate 10, and then the photoresist pattern 13 is formed on the silicon substrate 10. Form.

Subsequently, as shown in FIG. 1B, the gate oxide film 11 of the end point detection (EPD) etch-polycrystalline silicon film 12 using the photoresist pattern 13 as an etch mask is subjected to a main etching process. The polycrystalline silicon film 12 (see Fig. 1A) is etched by etching until it is exposed. At this time, the etched polycrystalline silicon film 12A does not have a vertical profile but has a tapered profile. On the other hand, '13A' represents a photoresist pattern which is partially lost during the etching process.

Subsequently, as shown in FIG. 1C, an over etching process is performed to make the polycrystalline silicon film 12A having the tapered profile into the polycrystalline silicon film 12B having the vertical profile. In the transient etching process, plasma oxidation occurs on the silicon substrate 10 by the O ₂ plasma included in the plasma etching gas. Thus, a silicon oxide film (SiO) is formed on the silicon substrate 10 at a predetermined thickness. ₂ , 14) are formed.

Subsequently, as shown in FIG. 1D, the photoresist pattern 13A (see FIG. 1C) is removed and then a cleaning process is performed. At this time, the silicon oxide film 14 (see FIG. 1C) formed on the silicon substrate 10 is also removed. '11A' represents a gate oxide film pattern.

Subsequently, as shown in FIG. 1E, a native oxide layer 15 is formed on the exposed silicon substrate 10 after the silicon oxide layer 14 (see FIG. 1C) is removed.

As described above, in the gate etching method according to the related art, the transient etching process after the main etching process is essentially performed to form a gate having a stable vertical profile. However, part of the silicon substrate is oxidized by the plasma oxidation phenomenon during the excessive etching process, and the oxidized portion is removed by the subsequent cleaning process, resulting in loss of the substrate. This substrate loss makes the active region where the source and drain regions are to be formed through a subsequent process becomes difficult to control the gate channel, and at the same time, the driving current of the transistor is reduced, thereby degrading device characteristics.

Accordingly, an object of the present invention is to provide a gate etching method capable of preventing a loss of a silicon substrate during a gate etching process of a semiconductor device.

According to an aspect of the present invention, there is provided a method including preparing a substrate on which a gate insulating film and a gate conductive film are formed, forming a gate pattern by etching the gate conductive film, and forming a gate pattern. It provides a gate etching method of a semiconductor device comprising the step of oxidizing a portion to form a thermal oxide film, and removing the thermal oxide film.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity and may be formed directly on other layers or substrates when referred to as being on another layer or substrate. Or a third layer may be interposed therebetween. In addition, parts denoted by the same reference numerals (reference numbers) throughout the specification represent the same elements.

Example

2A through 2D are cross-sectional views illustrating a gate etching method of a semiconductor device in accordance with an embodiment of the present invention.

First, as shown in FIG. 2A, an oxide film 111 is formed as a gate insulating film on the silicon substrate 110. At this time, the gate oxide film 111 is formed of a silicon oxide film (SiO ₂ ) by using a wet oxidation or dry oxidation process, the thickness is formed to be about 10 ~ 30Å.

Next, a polycrystalline silicon film 112 is deposited on the gate oxide film 111. At this time, the polycrystalline silicon film 112 is deposited to a thickness of about 1000 ~ 2000Å by using a low pressure chemical vapor deposition (LPCVD) process using SiH ₄ as the source gas.

Next, a bottom anti-reflective coating 113 is formed on the polycrystalline silicon film 112.

Subsequently, after the photoresist is coated on the antireflection film 113, an exposure process and a development process using a photo mask are sequentially performed to form the photoresist pattern 114.

Subsequently, as shown in FIG. 2B, an end point etching using the photoresist pattern 114 as an etching mask is performed by the main etching process to etch the polycrystalline silicon film 112 (see FIG. 2A). In this case, the main etching process is performed using Cl ₂ or HBr and O ₂ using Reactive Ion Etching (RIE) or Magnetically Enhanced Reactive Ion Etching (MERIE). For example, the flow rate of HBr is 100 sccm, the flow rate of O ₂ is 4 sccm, and the pressure is 50 mTorr or less, the source power of 250 W or more, and the bias power of 150 W or less. Meanwhile, '112A' represents a polycrystalline silicon film pattern, '113A' represents an antireflection film pattern, and '114A' represents a photoresist film pattern partially lost in the main etching process.

Subsequently, a cleaning process may be performed to remove foreign substances such as particles generated during the main etching process.

Subsequently, as shown in FIG. 2C, a thermal oxidation process (rather than an excessive etching process) is performed to make the polycrystalline silicon film 112A having the taper profile into the polycrystalline silicon film 112B having the vertical profile (see FIG. 2D). A thermal oxidation film 115 is formed by performing a thermal oxidation process. At this time, the thermal oxidation process is carried out at a temperature of about 1000 ~ 1100 ℃ until the thermal oxide film 115 has a thickness of about 50 ~ 100Å.

Subsequently, as shown in FIG. 2D, the thermal oxide film 115 is formed using DHF (Dilute HF, HF diluted with H ₂ 0 at a ratio of 50 (or 49): 1) or BOE (Buffered Oxide Etchant) solution. Remove As a result, a polycrystalline silicon film 112B having a vertical profile is formed.

On the other hand, during the thermal oxide film 115 removal process, it is preferable to control the process to minimize the loss of the gate oxide film 111. In this case, if the process control is difficult, the thermal oxide film 115 is nitrided by nitriding a part of the gate oxide film 111. You can also have an etching selectivity with

As described above, although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, although the polycrystalline silicon film is described as an example in the embodiment of the present invention, any electrode material used in the semiconductor field may be used instead of the polycrystalline silicon film. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects can be obtained.

First, according to the present invention, a tapered profile portion formed after etching a polycrystalline silicon film through a main etching process is oxidized through a thermal oxidation process and then removed by a cleaning process, thereby having a vertical profile without loss of a silicon substrate as in the prior art. The gate can be formed, which makes it possible to secure the thickness of the active region where subsequent source and drain regions will be formed. As a result, gate channel control is easy and the driving current of the transistor can be increased to improve device characteristics. have.

Second, according to the present invention, the line width of the gate can be reduced by reducing the polycrystalline silicon film by a predetermined thickness through a thermal oxidation process and a cleaning process.

Claims (8)

Preparing a substrate on which a gate insulating film and a gate conductive film are formed; Etching the gate conductive layer to form a gate pattern; Oxidizing a portion of the gate pattern to form a thermal oxide film; And Removing the thermal oxide film, The forming of the thermal oxide layer may include performing etching so that all of the portions having the tapered profile of the gate pattern are oxidized after the forming of the gate pattern. The method of claim 1, The forming of the gate pattern may be performed so that the substrate is not lost. The method of claim 1, And forming the gate pattern until the gate insulating layer is exposed. The method of claim 1, And the gate conductive layer is formed of a polycrystalline silicon layer. The method of claim 1, Forming the thermal oxide film is a gate etching method of a semiconductor device performed at a temperature of 1000 ~ 1100 ℃. The method according to claim 1 or 5, The thermal oxide film is a gate etching method of a semiconductor device to form a thickness of 50 ~ 100Å. delete The method of claim 1, Removing the thermal oxide film is a gate etching method of a semiconductor device using a dilute HF (DHF) or buffered oxide etchant (BOE) solution.

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