KR100838752B1 - Semiconductor device having thin film transistor and manufacturing method thereof - Google Patents

Abstract

A semiconductor device having a TFT includes a substrate, an island-type semiconductor film functioning as an active layer on or over the substrate, a pair of source / drain regions formed in the semiconductor film, and a pair of source / drain regions in the semiconductor film. It includes a channel region formed in. The pair of source / drain regions are thinner than the rest of the semiconductor film other than the source / drain regions. The thickness difference between the pair of source / drain regions and the remaining portion of the semiconductor film is in a range of 10 ns to 100 ns. The total process steps are reduced and the operating characteristics and reliability of the device are improved.

Semiconductor device, thin film transistor

Description

Semiconductor device with thin-film transistor and method of manufacturing the same {Semiconductor device with thin-film transistors and method of fabricating the same}

1A is an enlarged partial sectional view showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 1B is a plan view illustrating a schematic layout of an island type polysilicon film (ie, a polysilicon island) and a second alignment mark of the semiconductor device according to the first embodiment of FIG. 1A.

2A to 2M are partial cross-sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention, respectively.

3A to 3I are partial cross-sectional views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention, respectively.

4A to 4M are partial cross-sectional views showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention, respectively.

5A to 5L are partial cross-sectional views showing a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention, respectively.

6A through 6I are partial cross-sectional views showing a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention, respectively.

7A to 7J are partial cross-sectional views illustrating a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention, respectively.

※ Explanation of symbols for main parts of drawing

1 ... semiconductor device 10 ... substrate

12 ... bottom 20a, 20b ... source / drain regions

20c ... channel area 45 ... polysilicon film

47a, 47b ... 2nd alignment mark 50 ... gate insulating film

55 gate electrode / wiring 60 interlayer insulating film

65a, 65b ... contact hole 70a, 70b ... source / drain wiring

The present invention relates to a semiconductor device having thin-film transistors (TFTs) and a method of manufacturing the same. The semiconductor device according to the present invention is applicable to circuit elements of a liquid-crystal display (LCD) device such as switching elements for pixels, elements for driving circuits, and the like. Here, it is preferable that the TFTs are formed of a polycrystalline silicon (ie, polysilicon) thin film with an active layer.

In general, an LCD device is referred to as a substrate on which TFTs are arranged in a matrix arrangement (hereinafter referred to as a "TFT substrate") and another substrate facing the TFT substrate at predetermined intervals (hereinafter referred to as "opposed substrate"). ), And a liquid crystal layer disposed between the TFT substrate and the counter substrate. In order to ensure manufacturing yield and TFT characteristic stability in the manufacturing process of the TFT substrate, it is important to properly control the alignment between patterns in each manufacturing process.

A conventional well-used method of manufacturing a TFT substrate is as follows:

First, a base insulating film made of silicon dioxide (SiO ₂ ), silicon nitride (SiN), silicon oxynitride (SiON), or the like is formed on a glass substrate, followed by chemical vapor deposition (CVD). An amorphous silicon film is formed on the underlying film. "Amorphous silicon" is hereinafter referred to as "a-Si". Thereafter, a first photosensitive resist film is formed on the a-Si film, and the thus formed a-Si film is subjected to selective exposure and development processes, whereby a first mask having a pattern for first alignment marks is formed. do. Using the thus formed first mask, the a-Si film is selectively etched to form the first alignment marks. After that, the first mask is removed.

Next, the a-Si film (the first alignment marks are formed) is crystallized by solid-phase growth, excimer laser annealing, or the like to form a polycrystalline silicon film (hereinafter simply referred to as a polysilicon film). . Next, a second photosensitive resist film is formed on the polysilicon film and a selective exposure process and development process are performed, whereby a second mask having a pattern for the semiconductor island and the second alignment marks is formed. In the selective exposure process of the second photosensitive resist film, alignment is performed using the above-described first alignment marks.

Next, using the thus formed second mask, the polysilicon film is selectively etched. As such, the polysilicon film is patterned to form semiconductor islands (ie, polysilicon islands). At the same time, the second alignment marks are formed by the same polysilicon film. Thereafter, the second mask is removed.

Subsequently, a third photosensitive resist film is formed and a third mask having a pattern for impurity injection is formed through a selective exposure and development process. Next, the impurity is selectively implanted into the source / drain formation regions (that is, regions to be later formed into source / drain regions) of the island-type polysilicon film (i.e., polysilicon island) using the third mask thus formed. . As such, a pair of source / drain regions is formed in each polysilicon islands. After the third mask is removed, impurity ions implanted into the polysilicon islands are activated by an excimer laser annealing process, a thermal annealing process, or the like.

Thereafter, sequential process steps for gate insulating film forming, gate electrode / wiring forming, interlayer insulating film forming, contact hole forming, and source / drain wiring forming are sequentially performed, and the TFT substrate is completed.

As described above, in the prior art manufacturing method of the TFT substrate, in order to form only the first alignment marks, exposure and development of the first photosensitive resist mask, etching of the a-Si film, removal of the first photosensitive resist mask, etc. It is necessary to carry out five process steps for molding. Therefore, there is a problem that the total number of necessary process steps increases and the manufacturing cost is high. Accordingly, various measures have been developed and disclosed to reduce the total number of process steps, an example of which is disclosed in Japanese Laid-Open Patent Publication No. 2003-332349 published on November 21, 2003. The measures disclosed in this publication 2003-332349 are as follows.

Specifically, in the step of forming the a-Si film on the underlying insulating film formed on the glass substrate, a region where the a-Si film is not disposed (a-Si film non-existing region) is formed on the edge of the glass substrate and simultaneously a-Si film is formed. The region in which the Si film is disposed (a-Si film forming region) is formed inside the a-Si film non-existing region on the glass substrate. The a-Si film free zone is formed by hiding or covering the edge of the glass substrate in the forming step of the a-Si film. Next, a photosensitive resist film is formed on the a-Si film free region and the a-Si film forming region, and the thus formed photosensitive resist film is selectively exposed and developed, thereby forming patterns for implanting impurities and forming alignment marks. A mask having a pattern is molded. The pattern for impurity implantation is disposed on the a-Si film forming region, and the pattern for alignment mark forming is disposed on the a-Si film nonexistent region.

Then, predetermined impurities are selectively implanted into the a-Si film using the mask described above, and then the underlying insulating film is selectively etched using the same mask. As a result, source / drain formation regions are formed in the a-Si film forming region of the a-Si film, and at the same time, alignment marks are formed in the a-Si film non-existing region by the underlying insulating film. After the etching process is completed, the mask is removed.

In the method disclosed in Japanese Patent Laid-Open No. 2003-332349, the above five process steps for forming the first alignment marks in the above-described prior art method for manufacturing a TFT substrate are omitted. In this way, an increase in manufacturing cost is suppressed.

Furthermore, the following method has been developed to shorten the manufacturing process sequence by omitting the activation process of the impurities implanted in the a-Si film. This method is disclosed in Japanese Patent No. 3211340, published July 19, 2001.

Specifically, an a-Si film is deposited on the insulating substrate, and predetermined impurities are selectively implanted into the source / drain formation regions of the a-Si film, thereby forming an impurity implantation region on the a-Si film. Thereafter, the excimer laser beam is irradiated directly to the impurity implantation region, whereby the a-Si film is changed into a polysilicon film (i.e. crystallization of the a-Si film) and simultaneously activates impurities present in the impurity implantation region. This method is called an excimer laser annealing method. In this method, crystallization of the a-Si film and activation of the implanted impurities can be performed simultaneously, thus shortening the manufacturing process procedure. As a result, an increase in manufacturing cost is prevented.

As can be clearly seen from the method disclosed in Japanese Patent Laid-Open No. 2003-332349, in order to shorten the manufacturing process (i.e. reduce the total number of necessary process steps), a single set of exposure and development processes are carried out. It is effective to form a pattern for impurity injection and an alignment mark molding, or to simultaneously perform crystallization of the a-Si film and activation of impurities injected into the a-Si film. However, if a pattern for impurity injection and a pattern for forming an alignment mark are formed through a single set of exposure and development processes using the method disclosed in Japanese Patent Laid-Open No. 2003-332349, the alignment marks are only glass substrates. Is placed on the edge of the. As such, a disadvantage arises in that alignment accuracy is degraded in the intermediate region of the glass substrate.

In addition, an area for forming alignment marks needs to be provided on the edge of the glass substrate, so that the area for forming TFTs is narrowed. As a result, another disadvantage arises that the manufacturing cost increases.

Furthermore, if similar to the method disclosed in Japanese Patent No. 3211340, a desired impurity is selectively implanted into the source / drain formation regions of the a-Si film, and then crystallization of the a-Si film and activation of impurity ions are performed by excimer laser. If proceeded simultaneously by irradiation, heavy metal impurities (which are inevitably injected into the surface of the a-Si film together with the desired impurities) diffuse toward the inside of the a-Si film during the irradiation of the excimer laser. If so, the diffused heavy metal impurities will deteriorate the characteristics and reliability of the TFTs formed using the a-Si film.

The present invention has been invented in view of the above disadvantages.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a TFT or TFTs which reduces the total number of necessary process steps and improves operation characteristics and reliability, and a method of manufacturing the device.

It is another object of the present invention to provide a semiconductor device having a TFT or TFTs which guarantees higher alignment accuracy than this type of conventional semiconductor device and a method of manufacturing the device.

It is still another object of the present invention to provide a semiconductor device having a TFT or TFTs which reduces manufacturing costs than a conventional semiconductor device of this type and a method of manufacturing the device.

Other objects, as well as those not specifically mentioned above, will become apparent to those skilled in the art from the following descriptions.

According to a first aspect of the present invention, there is provided a semiconductor device having a TFT, which semiconductor device,

Board;

An island-type semiconductor film formed directly on the substrate or over the substrate, and functioning as an active layer of the TFT;

A pair of source / drain formation regions of the TFT formed in the semiconductor film; And

A channel region of the TFT formed between the pair of source / drain formation regions in the semiconductor film,

The pair of source / drain formation regions are smaller in thickness than the rest of the semiconductor film;

The thickness difference between the pair of source / drain formation regions and the rest of the semiconductor film

A semiconductor device having a TFT characterized by being set in a range of 10 Hz to 100 Hz.

Here, the reason why the thickness difference between the pair of source / drain formation regions and the rest of the semiconductor film is set in the range of 10 k? To 100 k? Is as follows.

The minimum value of 10 ms has been determined by the fact that the minimum reading depth (ie, minimum thickness difference) of the alignment marks by the exposure apparatus is 10 ms.

The maximum value of 100 Hz was determined for the following reasons. When the semiconductor film is formed by crystallization of the amorphous semiconductor film by excimer laser annealing, the maximum possible depth of the alignment marks (ie, under the condition that the shape of the alignment marks can be maintained at a level at which the alignment marks can be read by the exposure apparatus) , Maximum thickness difference) is 100Å.

In the semiconductor device according to the first aspect of the present invention, the thickness of the pair of source / drain formation regions is less than the thickness of the rest of the semiconductor film by an arbitrary value in the range of 10 kV to 100 kV. This means that the surface of the pair of source / drain regions (ie, semiconductor film) is selectively removed. As such, when a desired impurity is implanted into a pair of semiconductor films (i.e. source / drain formation regions) that will later become source / drain regions, a pair of heavy metal impurities injected into the semiconductor film with the desired impurity It is removed by selective removal of the surfaces of the source / drain regions.

Therefore, when the crystallization of the amorphous semiconductor film and activation of the implanted impurities proceed simultaneously by excimer laser annealing, the heavy metal impurities injected into the amorphous semiconductor film together with the desired impurities are formed in the amorphous semiconductor film (ie, source / drain regions). It will not spread inward. As a result, the operating characteristics and reliability of the TFT (i.e., the semiconductor device including the TFT) can be improved.

Furthermore, by forming a pattern for impurity injection and alignment mark molding through a single set of exposure and development processes, and simultaneously performing crystallization of the semiconductor film and activation of impurities implanted into the semiconductor film. The total number can be reduced. As a result, manufacturing costs can be lowered.

It is preferable that a semiconductor film is polycrystal. More preferably, the polycrystalline semiconductor film is formed by crystallizing the amorphous semiconductor film.

In a preferred embodiment of the semiconductor device according to the first aspect of the present invention, alignment marks are additionally provided near the outside of the semiconductor film. These alignment marks are made of the same material as that of the semiconductor film. In this embodiment, the alignment marks are arranged near the outside of the semiconductor film, unlike the structure disclosed in Japanese Patent Laid-Open No. 2003-332349, in which the alignment marks are arranged around the substrate. Therefore, alignment marks can be used for the arrangement or arrangement of the upper (ie high level) pattern with respect to the semiconductor film. In conclusion, there is an additional advantage of achieving higher array accuracy than anything else.

In another preferred embodiment of the semiconductor device according to the first aspect of the present invention, the alignment marks are the same in thickness as the rest of the semiconductor film. In this embodiment, there is still an additional advantage that a high arrangement accuracy can be obtained.

In another preferred embodiment of the semiconductor device according to the first aspect of the present invention, an additional island type semiconductor film serving as an active layer of the additional TFT is formed on the substrate directly or via the underlying film. Additional pairs of source / drain regions of additional TFTs are formed in the additional semiconductor film. Additional channel regions of the additional TFTs are formed between additional pairs of source / drain regions in the additional semiconductor film. The additional pair of source / drain regions are the same thickness as the rest of the additional semiconductor film. In this embodiment, there is an additional advantage that an auxiliary TFT structure can be obtained.

According to a second aspect of the present invention, a method of manufacturing a semiconductor device having a TFT is provided, which method

Forming an amorphous semiconductor film directly on or over the substrate;

Forming a first mask on the amorphous semiconductor film, the first mask having a first pattern for source / drain regions and a second pattern for first alignment marks;

Selectively implanting impurities into the amorphous semiconductor film using the first mask to form first impurity implantation regions by a first pattern and second impurity implantation regions by a second pattern;

Selectively etching the surfaces of the first impurity injecting regions and the surfaces of the second impurity injecting regions using a first mask;

First impurity injection regions etched on the surface and second impurity injection regions etched on the surface so that the amorphous semiconductor film crystallizes to form a polycrystalline semiconductor film and activates impurities implanted into the first impurity injection regions and the second impurity injection regions. Irradiating a laser light to the amorphous semiconductor film including the;

Forming a second mask on the polycrystalline semiconductor film, the second mask having a third pattern for a semiconductor island; And

Selectively etching the polycrystalline semiconductor film using the second mask to form a semiconductor island by the third pattern;

Irradiating a laser light to an amorphous semiconductor film, wherein a pair of source / drain regions are formed by first impurity implantation regions and first alignment marks are formed by second impurity implantation regions in the polycrystalline semiconductor film Become;

Selectively etching a polycrystalline semiconductor film, wherein the pair of source / drain regions are included in the semiconductor island, and first alignment marks are excluded from the semiconductor island.

In the method of manufacturing a semiconductor device according to the second aspect of the present invention, the surface-etched first impurity implantation regions and the surface-etched second impurity implantation regions are exposed and developed of the resist film for the first mask, and impurities in the amorphous semiconductor film. Is obtained by performing a series of only molding operations of implantation of, and selective etching of the amorphous semiconductor film. By irradiating the amorphous semiconductor film with the laser light, the first impurity implantation region etched into the surface is changed to a pair of source / drain regions of the TFT and at the same time the second impurity implantation regions etched into the first alignment marks.

Further, by irradiating an amorphous semiconductor film including the surface-etched first and second impurity implantation regions, the amorphous semiconductor film is crystallized to form a polycrystalline semiconductor film and simultaneously implanted into the first and second impurity implantation regions. Impurities are activated. Therefore, no additional process steps for activating the impurities are required.

Thus, the total number of manufacturing process steps required for a semiconductor device (ie, a semiconductor device according to the first aspect of the present invention) is reduced. This means that the manufacturing cost is reduced.

In addition, since the surfaces of the first and second impurity implantation regions in the amorphous semiconductor film are selectively etched using the first mask, the removal of heavy metal impurities injected into the surface of the amorphous semiconductor film together with the desired impurities is ensured. . Therefore, compared with the prior art method in which heavy metal impurities are not removed, variations in the initial characteristics of the TFT (i.e., semiconductor device) formed using the pair of source / drain regions are improved, and reliability is also improved.

In a preferred embodiment of the method according to the second aspect of the present invention, alignment is performed using the first alignment marks in the step of selectively etching the polycrystalline semiconductor film using the second mask. This embodiment has the additional advantage that the semiconductor island can be formed with higher alignment accuracy than any conventional one.

In another preferred embodiment of the method according to the second aspect of the invention, the second mask has a fourth pattern for the second alignment marks in addition to the third pattern for the semiconductor island. In the step of selectively etching the polycrystalline semiconductor film using the second mask to form the semiconductor island, the second alignment marks are formed near the semiconductor island by the fourth pattern. In this embodiment, unlike the structure disclosed in Japanese Patent Laid-Open No. 2003-332349, in which the alignment marks are disposed at the edge of the substrate, the first alignment marks are a pair of source / drain regions in the polycrystalline semiconductor film. And second alignment marks are formed near and outside the semiconductor islands. Therefore, the second alignment marks can be used for alignment or arrangement of the upper (high level) pattern than the semiconductor islands. Therefore, there is an additional advantage that higher alignment accuracy can be obtained for the upper pattern than any conventional one.

In another preferred embodiment of the method according to the second aspect of the present invention, there is additionally provided a step of implanting impurities for threshold control on the surface of the amorphous semiconductor film. This additional step is performed before the step of irradiating the laser light onto the amorphous semiconductor film. This additional step is preferably performed after the first mask is removed. However, impurities for threshold control may be selectively implanted into the channel region of the TFT using an appropriate mask. In this embodiment, there is an additional advantage that the threshold of the TFT can be controlled or adjusted.

In a more preferred embodiment of the method according to the second aspect of the present invention, there is additionally provided a step of injecting impurities for forming the LDD structure into the surface of the amorphous semiconductor film. This additional step is performed before the step of irradiating the laser light onto the amorphous semiconductor film. In this embodiment, there is an additional advantage that a TFT having an LDD structure can be formed.

According to a third aspect of the present invention, a method of manufacturing a semiconductor device having a TFT of a first conductivity type and a TFT of a second conductivity type is provided. This way:

Forming an amorphous semiconductor film directly on the substrate or via an underlying film;

Forming a first mask on the amorphous semiconductor film, the first mask having a first pattern for the source / drain regions of the first TFT of the first conductivity type and a second pattern for the first alignment marks;

Selectively implanting impurities of a first conductivity type into the amorphous semiconductor film using a first mask to form a first impurity implantation region by a first pattern and a second impurity implantation region by a second pattern;

Selectively etching the surface of the first impurity implantation region and the surface of the second impurity implantation region using a first mask;

Forming a second mask on the amorphous semiconductor film, the second mask having a third pattern for the source / drain regions of the second TFT of the second conductivity type;

Selectively implanting impurities of the second conductivity type into the amorphous semiconductor film using a second mask to form a third impurity implantation region by a third pattern;

A first impurity implantation region, a surface etched first, etched surface to crystallize the amorphous semiconductor film to form a polycrystalline semiconductor film and to activate impurities implanted into the first impurity implantation region, the second impurity implantation region, and the third impurity implantation region Irradiating a laser light to an amorphous semiconductor film having a second impurity implantation region and a third impurity implantation region;

Forming a third mask on the polycrystalline semiconductor film, the third mask having a fourth pattern for the first and second semiconductor islands; and

Selectively etching the polycrystalline semiconductor film using the third mask to form a first semiconductor island for the first TFT and a second semiconductor island for the second TFT by the fourth pattern;

In the step of irradiating the laser light to the amorphous semiconductor film, a pair of source / drain regions of the first TFT are formed by the first impurity implantation regions in the polycrystalline semiconductor film, and the first alignment is performed by the second impurity implantation regions. Marks are formed, and a pair of source / drain regions of the second TFT are formed by the third impurity injection regions; And,

Selectively etching the polycrystalline semiconductor film, the pair of source / drain regions of the first TFT are included in a first semiconductor island, the pair of source / drain regions of a second TFT are included in a second semiconductor island, and The first alignment marks are excluded from the first and second semiconductor islands.

In the method of manufacturing a semiconductor device according to the third aspect of the present invention, the surface-etched first and second impurity implantation regions are exposed to a molding operation, that is, exposure of the first mask resist film for the first TFT of the first conductive type and It is obtained by performing development, impurity implantation of the first conductive impurity into the amorphous semiconductor film, and selective etching of the amorphous semiconductor film. The third impurity implantation regions are obtained by performing molding operations, that is, exposing and developing the second mask resist film for the second TFT of the second conductive type, and impurity implantation of the second conductive impurity into the amorphous semiconductor film. In addition, by irradiating the amorphous semiconductor film with laser light, the first impurity implanted regions etched into the surface are changed into a pair of source / drain regions of the first TFT, and the second impurity implanted regions etched into the first alignment marks. And the third impurity injection regions are changed into a pair of source / drain regions of the second TFT.

Furthermore, by irradiating the laser light to the amorphous semiconductor film including the first and second impurity implantation regions and the third impurity implantation regions etched on the surface, the amorphous semiconductor film is crystallized to form a polycrystalline semiconductor film, and simultaneously The first conductive impurity implanted in the second impurity implantation regions and the second conductive impurity implanted in the third impurity implantation regions are activated. Therefore, no additional processing step for activating the impurities is required.

Thus, the total number of manufacturing process steps for a semiconductor device (eg, semiconductor device according to the first aspect of the present invention) is reduced. This means that the manufacturing cost is reduced.

In addition, since the surfaces of the first and second impurity implantation regions in the amorphous semiconductor film are selectively etched using the first mask, the removal of heavy metal impurities injected into the surface of the amorphous semiconductor film together with the desired impurities is ensured. . Therefore, compared with the prior art method in which heavy metal impurities are not removed, the initial characteristic change of the first TFT formed using the corresponding pair of source / drain regions is improved and its reliability is also improved.

As such, for the same reasons as the method according to the second aspect, the same advantages as those of the method according to the second aspect are obtained.

In the method according to the third aspect, the first alignment marks can be used in common for the first and second TFTs, and therefore the second mask does not have a pattern for alignment marks corresponding to the first alignment marks. However, needless to say, the second mask may have a pattern for alignment marks corresponding to the first alignment marks. This can be applied to the second alignment marks.

In a preferred embodiment of the method according to the third aspect of the invention, in the step of selectively etching the polycrystalline semiconductor film using the third mask, the alignment is performed using the first alignment marks. In this embodiment, there is an additional advantage that the first and second semiconductor islands can be formed with higher alignment accuracy than any.

In another preferred embodiment of the method according to the third aspect of the invention, the third mask has a fifth pattern for the second alignment marks in addition to the fourth pattern for the semiconductor islands. In the step of selectively etching the polycrystalline semiconductor film using the third mask to form the first and second semiconductor islands, the second alignment marks are formed near the first and second semiconductor islands by the fifth pattern. In this embodiment, unlike the structure disclosed in Japanese Patent Laid-Open No. 2003-332349, in which the alignment marks are disposed at the edge of the substrate, the first alignment marks are formed by two of the first and second TFTs in the polycrystalline semiconductor film. Formed near the pair of source / drain regions, and second alignment marks are formed outside and near the first and second semiconductor islands. Therefore, the second alignment marks may be used for the alignment or placement of the upper (ie, higher level) pattern than the first and second semiconductor islands. In conclusion, there is an additional advantage that higher alignment accuracy than any can be obtained for the upper pattern.

In another preferred embodiment of the method according to the third aspect of the present invention, an additional step of injecting impurities for threshold control into the surface of the amorphous semiconductor film is additionally provided. This additional step is performed before the step of irradiating the laser light onto the amorphous semiconductor film. This additional step may be performed in such a way that the impurity for threshold control is only injected into the channel region of the amorphous semiconductor film using an appropriate mask, or that the impurity for threshold control is injected into the entire surface of the amorphous semiconductor film. In this embodiment, there is an additional advantage that the thresholds of the first and second TFTs can be controlled or adjusted.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

(First embodiment)

(Structure of Semiconductor Device)

FIG. 1A shows a schematic structure of a semiconductor device 1 according to a first embodiment of the present invention, and FIG. 1B shows a schematic arrangement of an island type polysilicon film (ie, polysilicon island) and its second alignment marks. Giving.

As shown in Figs. 1A and 1B, the semiconductor device 1 of the first embodiment includes a substrate 10 and an underlying insulating film 12 formed on the substrate 10. Figs. Here, the substrate 10 is formed by a square glass plate. On the base film 12, the patterned polysilicon film 45 is formed to have an island shape, and a pair of second alignment marks 47a and 47b are formed. This polysilicon film 45 may be referred to as "polysilicon island" below. The channel region 20c is formed in the middle of the polysilicon island 45. A pair of source / drain regions 20a and 20b are formed on each side of the channel region 20c in the island 45. As such, the channel region 20c is sandwiched by a pair of source / drain regions 20a and 20b. On the left side of the source / drain area 20a, the second alignment mark 47a is disposed away from the source / drain area 20a. On the right side of the source / drain area 20b, the second alignment mark 47b is disposed away from the source / drain area 20b.

The thickness Ta of the source / drain region 20a and the thickness Tb of the source / drain region 20b are smaller than the thickness Tc of the polysilicon island 45. That is, Ta = Tb <Tc. The thickness of the second alignment marks 47a and 47b is the same as the thickness Tc of the island 45.

The difference ΔTa (= Tc-Ta) between the thickness Tc of the island 45 and the thickness Ta of the source / drain region 20a and the thickness Tc of the island 45 and the source / drain region 20b The difference DELTA Tb (= Tc-Tb) between the thicknesses Tb) is set to a value between 10 ms and 100 ms, respectively. this is

10Å ≤ ΔTa ≤ 100Å,

10 μs ≦ ΔTb ≦ 100 μs, and

ΔTa = ΔTb

Means to be.

The reasons why ΔTa and ΔTb are set in the range of 10 Hz to 100 Hz are as follows:

The reason why the minimum value of ΔTa and ΔTb becomes 10 ms is that the minimum readable depth (that is, the minimum readable thickness difference) of the alignment marks (formed from the same polysilicon film as the island 45) using the exposure apparatus. ) Is 10Å.

The reason why the maximum value of ΔTa and ΔTb is 100 μs is as follows: The polysilicon island 45 is formed by crystallizing the a-Si film by an excimer laser annealing method and patterning the crystallized a-Si film as such. It is assumed that the alignment marks are formed by the same polysilicon film as the island 45. In this case, the shape of the alignment marks is because the maximum possible depth (ie maximum possible thickness difference) of the alignment marks under the condition that the alignment marks can be maintained at a level that can be read by the exposure apparatus is 100 ms.

If these conditions are satisfied for ΔTa and ΔTb, the thickness of the second alignment marks 47a and 47b may not be equal to the thickness Tc of the polysilicon island 45. In addition, the difference between ΔTa and ΔTb may be different from each other (that is, ΔTa ≠ ΔTb).

The pair of polysilicon islands 45 and the second alignment marks 47a and 47b are covered with the gate insulating film 50. This film 50 is formed on the base film 12. The gate insulating film 50 covers the entire surface of the substrate 10. On the gate insulating film 50, a gate electrode / wiring 55 is formed. The gate electrode / wiring 55 overlaps the entire channel region 20c of the island 45, and this overlapping portion functions as a gate electrode of the TFT and the remaining portion functions as a gate wiring. The gate electrode / wiring 55 is covered with a thick interlayer insulating film 60 formed on the gate insulating film 50. The interlayer insulating film 60 covers the entire surface of the substrate 10. The surface of this film 60 is planarized.

The pair of source / drain regions 20a and 20b, the gate insulating film 50, and the gate electrode / wiring 55 constitute a TFT.

On the interlayer insulating film 60, a pair of source / drain lines 70a and 70b are formed. The source / drain wiring 70a is connected to the source / drain region 20a mechanically and electrically by a conductive plug filled in the contact hole 65a penetrating through the gate insulating film 50 and the interlayer insulating film 60. It is done. Similarly, the source / drain wiring 70b is mechanically and electrically connected to the source / drain region 20b by a conductive plug filled in the contact hole 65b penetrating through the gate insulating film 50 and the interlayer insulating film 60. It is connected.

As described above, in the semiconductor device 1 according to the first embodiment of the present invention shown in FIGS. 1A and 1B, the thicknesses Ta and Tb of the pair of source / drain regions 20a and 20b are shown. ) Is set to be smaller than the thickness Tc of the remainder of the polysilicon island (45, i.e., the channel region 20c) by a selection value within the range of 10 ms to 100 ms. This merely means that the surfaces of the source / drain regions 20a and 20b of the polysilicon island 45 are selectively removed.

Therefore, when desired impurities are later implanted into portions of the polysilicon island 45 (ie, source / drain forming regions) for formation into the source / drain regions 20a and 20b, together with the desired impurities Heavy metal impurities implanted into the island 45 are removed by selective removal of the surfaces of the source / drain regions 20a and 20b.

Thus, when crystallization of the a-Si film and activation of the implanted impurities are simultaneously performed by excimer laser annealing, unwanted heavy metal impurities present in the a-Si film are introduced into the source / drain regions 20a and 20b. There is no possibility of spread. As a result, compared with the conventional method in which heavy metal impurities are not removed, the initial characteristic change of the TFT (i.e., the semiconductor device 1) including the source / drain regions 20a and 20b is improved, and the reliability is likewise Is improved. As such, the operating characteristics and the reliability of the TFT (semiconductor device 1) can be improved.

Furthermore, unlike the structure disclosed in Japanese Patent Laid-Open No. 2003-332349, where the alignment marks are disposed on the edge of the substrate 10, the pair of second alignment marks 47a and 47b is formed of polysilicon island ( 45 and disposed near the pair of source / drain regions 20a and 20b in the island 45, respectively (i.e., the pair of second alignment marks 47a and 47b are formed on the substrate (e.g. 10) for each TFT formed on it}. Therefore, in the above-described structure of Japanese Patent Laid-Open No. 2003-332349, the second alignment marks 47a and 47b arranged in the "a-Si film formation area" are aligned or arranged at the top or high level pattern or patterns. May be used for In conclusion, higher alignment accuracy than any is obtained for upper patterns such as patterns for gate electrodes / wiring.

Furthermore, by forming an impurity injection pattern and an alignment mark forming pattern through a single set of exposure and development processes for the mask, and simultaneously proceeding crystallization of the a-Si film and activation of impurities implanted in the a-Si film. The number of exposure / development processes can be reduced. As a result, the total number of necessary process steps for the apparatus 1 can be reduced. This means that the manufacturing cost of the device 1 is further reduced.

In the above-described semiconductor device 1, although a higher alignment accuracy than any is obtained in subsequent steps such as forming the gate electrode / wiring 55, a pair of second alignment marks ( 47a, 47b) may be omitted.

(Method of manufacturing semiconductor device)

Next, a method of manufacturing the semiconductor device 1 according to the first embodiment of the present invention will be described with reference to FIGS. 2A to 2M.

First, as shown in FIG. 2A, an underlying insulating film 12 is formed on a glass substrate (i.e., substrate) 10 in a predetermined size. The base film 12 is provided to prevent films formed directly on or on the glass substrate 10 from contamination due to impurities present in the substrate 10. The base film 12 is formed of a silicon dioxide (SiO ₂ ) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiON) film, or a laminate of a SiO ₂ film and a SiNx film. The thickness of the base film 12 is selectively set to a value within the range of 1000 mV to 5000 mV. Here, the base film 12 is formed by the SiO ₂ film to a thickness of 5000 kPa.

Next, as shown in FIG. 2B, the a-Si film 14 is formed on the base film 12 by a low-pressure chemical vapor deposition (LPCVD) method or a plasma-enhanced CVD (PECVD) method. Since the a-Si film is used as the active layer of the TFT after crystallization, the thickness of the film 14 is preferably as small as possible in view of suppressing the leakage current. However, in consideration of the process margin for the subsequent crystallization process of the a-Si film 14, the thickness of the film 14 is preferably set to a value within the range of 300 mW to 3000 mW. Here, the thickness of the film 14 is set to 600 kPa.

Next, as shown in Fig. 2C, a photosensitive resist film having a predetermined thickness is formed on the a-Si film 14 by coating. The photosensitive resist film is then patterned by exposure and development to form a pair of first alignment marks 18a and 18b and a pair of source / drain regions 20a and 20b. To form. The mask 16 has openings 16a corresponding to the pair of first alignment marks 18a and 18b and openings 16a corresponding to the pair of source / drain regions 20a and 20b. , 16b).

Next, as shown in FIG. 2D, a desired p-type impurity such as boron (B) is selectively introduced into the a-Si film 14 by ion implantation using the mask 16. In this ion implantation step, the dose is 1 × 10 ¹⁵ cm ⁻² . As a result, certain p-type impurity ions are selectively implanted into the a-Si film 14 through the openings 16a, 16b, 16c, 16d of the mask 16. As such, a pair of p-type impurity implantation regions 20a 'and 20b' are formed in the a-Si film 14 and a pair of p-type impurity implantation regions 18a 'and 18b' are formed at the same time. do. Since a pair of impurity implantation regions 18a 'and 18b' are formed simultaneously with a pair of impurity implantation regions 20a 'and 20b', this method is performed so that alignment marks are formed only on the edge of the substrate. There is a difference from the method disclosed in Japanese Patent Laid-Open No. 2003-332349. As such, in the method of the first embodiment, since the impurity injection regions 18a 'and 18b' (hereinafter referred to as first alignment marks 18a and 18b) are formed at this stage, the subsequent polysilicon island ( The alignment accuracy is improved in the exposing process of the a-Si film 14 for forming 45).

In the step of FIG. 2D, the implantation depth of the p-type impurity ions is set to almost the entire thickness of the a-Si film 14. As such, the implanted ions spread throughout the thickness of the film 14 due to the subsequent activation process of the impurity ions.

Impurity implantation regions 18a 'and 18b' formed near the impurity implantation regions 20a 'and 20b', respectively, by the ion implantation step in FIG. 2D do not affect the TFT characteristics. This is because the impurity injection regions 18a 'and 18b' are removed in a later process.

Next, as shown in FIG. 2E, the surfaces of the p-type impurity implantation regions 18a 'and 18b' of the a-Si film 14 and the p-type impurity implantation regions 20a 'and 20b'. The surfaces of are selectively etched using the same mask 16. After the etching is completed, the mask 16 is removed. Here, the surface-etched impurity implantation regions 18a 'and 18b' are designated 18a '' and 18b '', respectively. Similarly, surface-etched impurity implantation regions 20a 'and 20b' are denoted by 20a '' and 20b '', respectively.

In the etching process of FIG. 2E, the etching depth of the a-Si film 14 is selectively set to a value within the range of 10 kPa to 100 kPa, for the following reason: Here, the etching depth is set to 50 kPa.

(i) The minimum readable depth of the first alignment marks 18a and 18b that can be read by the exposure apparatus (ie, the minimum values of the thickness differences ΔTa and ΔTb) is 10 μs.

(ii) when the a-Si film 14 is crystallized by the excimer laser annealing (ELA) method in a subsequent process to be described later, the level at which the first alignment marks 18a and 18b can be read into the exposure apparatus. The maximum possible depth of the first alignment marks 18a and 18b under the condition that the shape of the first alignment marks 18a and 18b is maintained (that is, the maximum values of the thickness differences ΔTa and ΔTb) is 100 μs.

As described above, the surface-etched p-type impurity implantation regions (such as molding, exposure and development for the mask 16, and etching of the a-Si film 14, etc.) are simply performed by performing a series of operations. 18a '', 18b '', 20a '', 20b '') are obtained.

As shown in Fig. 2E, the surfaces of the impurity implantation regions 20a &quot; and 20b &quot;, which will later be the source / drain regions 20a and 20b, are etched away. As such, the unwanted heavy metal impurities introduced into the a-Si film 14 together with the desired impurity (ie boron) ions are removed. According to the experiments of the inventors, the initial characteristic degradation of the TFT (i.e., the semiconductor device 1) including the source / drain regions 20a and 20b is 10% or more as compared to the conventional method in which heavy metal impurities are not removed. Improvements were found. In addition, it has, of course, been found that the reliability is also improved. Specifically, reliability is more than doubled in the conventional method in which heavy metal impurities are not removed.

Next, as shown in FIG. 2F, the excimer laser light B is subjected to the entire surface of the a-Si film 14 (surface-etched impurity implantation regions 18a '', 18b '', and 20a 'by the ELA method. And &quot; 20b &quot;) &quot; to thereby crystallize the a-Si film 14. In this way, the polysilicon film 35 is obtained. At this time, the impurity (i.e., boron) implanted in the impurity implantation regions 20a '' and 20b '' is activated, so no additional activation process for the implanted impurity is required. Furthermore, due to the crystallization of the a-Si film 14, the p-type impurity implantation regions 18a '' and 18b '' become the first alignment marks 18a and 18b, respectively, and the p-type impurity implantation Regions 20a '' and 20b '' become p-type source / drain regions 20a and 20b, respectively.

Next, as shown in Fig. 2G, a photosensitive resist film is formed on the polysilicon film 35 by a coating process, and then exposed and developed, thereby thereby making the polysilicon island 45 and the second alignment marks 47a. , Mask 39 for 47b). The mask 39 has a pattern including a portion 40 for forming the polysilicon island 45 and portions 42a and 42b for forming the second alignment marks 47a and 47b. The remainder of (39) is removed. Alignment of the mask 39 is performed using previously formed first alignment marks 18a and 18b. Since the first alignment marks 18a and 18b are disposed near the source / drain regions 20a and 20b, respectively, the arrangement of the mask 39 can be performed with an accuracy of ± 0.1 mu m or less.

Here, for the sake of simplicity, in the case where one TFT (including a pair of source / drain regions 20a and 20b and a gate electrode / wiring 55) is formed on the substrate 10 Explain. In practice, however, many TFTs are arranged in a matrix arrangement on the substrate 10. In the first embodiment of the present invention, the first alignment marks 18a and 18b are disposed close to the source / drain regions 20a and 20b of each of the TFTs, and thus the first alignment marks 18a. , 18b is disposed on the entire substrate 10 according to the arrangement of the source / drain regions 20a, 20b. Therefore, the arrangement of the TFTs can be performed with an accuracy of ± 0.1 mu m or less. On the other hand, in the method disclosed in Japanese Patent Laid-Open No. 2003-332349, alignment marks are only disposed on the edge of the substrate. Therefore, the obtainable arrangement accuracy of the TFTs is more than ± 0.3 μm, which is considerably deteriorated compared with the first embodiment of the present invention.

Next, as shown in FIG. 2H, the polysilicon film 35 is selectively etched using the mask 39, thereby forming the island-type polysilicon film 35, that is, the polysilicon island 45. do. At the same time, a pair of second alignment marks 47a and 47b are formed by the polysilicon film 35 on each side of the polysilicon island 45. Second alignment marks 47a and 47b are disposed near island 45 away from island 45. The island 45 is formed to include a pair of source / drain regions 20a and 20b and a channel region 20c and exclude the second alignment marks 47a and 47b. The pair of first alignment marks 18a and 18b are removed in this step.

Next, as shown in FIG. 2I, a gate insulating film 50 is formed on the base film 12 to cover the polysilicon island 45 and the second alignment marks 47a and 47b. The gate insulating film 50 covering the entire surface of the substrate 10 has a thickness of 1000 mW. The gate insulating film 50 is formed by a SiO ₂ film, a SiNx film, a SiON film, or a laminated film of a SiO ₂ film and a SiNx film. Here, the gate insulating film 50 is formed of a SiO ₂ film.

Next, as shown in FIG. 2J, the gate electrode / wiring 55 is formed on the gate insulating film 50 so as to overlap the channel region 20c. The gate electrode / wiring 55 is made of a conductive material such as Si, Al, Cr, Mo, W, WSi, or the like. Here, the gate electrode / wiring 55 is formed of a Cr film patterned to a thickness of 2000 kPa. The arrangement in the forming process of the gate electrode / wiring 55 is performed using the polysilicon island 45 and the second alignment marks 47a and 47b.

Next, as shown in FIG. 2K, an interlayer insulating film 60 is formed on the gate insulating film 50 so as to cover the gate electrode / wiring 55. This interlayer insulating film 60 covering the entire surface of the substrate 10 is formed of a SiO ₂ film with a thickness of 4000 kPa. The surface of the interlayer insulating film 60 is planarized by a known method.

Next, as shown in FIG. 2L, a pair of contact holes 65a and 65b are formed to penetrate the interlayer insulating film 60 and the gate insulating film 50 in a known manner. These contact holes 65a and 65b reach the source / drain regions 20a and 20b of the polysilicon island 45, respectively.

Next, as shown in FIG. 2M, a metal film is formed on the interlayer insulating film 60 and patterned in a known manner, whereby a pair of source / drain wirings 70a and 70b on the interlayer insulating film 60. ). These source / drain wires 70a and 70b are connected to the source / drain regions 20a and 20b mechanically and electrically through contact holes 65a and 65b, respectively. The structure of FIG. 2M is the same as that of FIG. 1A.

Through the above-described process steps, a TFT (ie, polysilicon TFT) having a polysilicon film 35 as an active layer is completed on the substrate 10. As a result, the semiconductor device 1 according to the first embodiment is manufactured.

In the above-described manufacturing method of the semiconductor device 1 according to the first embodiment, molding, exposure and development of a resist film for the mask 16, impurity injection into the a-Si film 14, and a-Si film 14 Surface-etched p-type impurity implantation regions 18a '' and 18b '' and surface-etched p-type impurity implantation regions 20a '' and 20b by performing a series of operations of selective etching of '') Is obtained. Further, the impurity-infused a-Si film 14 is crystallized by irradiating the laser beam B on the entire surface of the a-Si film 14 to form the polysilicon film 35 (FIG. 2F). Therefore, the p-type impurity (i.e., boron) injected into the impurity implantation regions 20a '' and 20b '' (which later becomes the source / drain regions 20a and 20b) is activated. Thus, no additional processing steps for the activation of the implanted p-type impurities are required. Thus, the total number of manufacturing process steps required for the semiconductor device 1 according to the first embodiment is reduced, and the manufacturing cost of the device 1 is reduced.

In addition, since the surfaces of the p-type impurity implantation regions 20a '' and 20b '' (which later become the source / drain regions 20a and 20b) are selectively etched (FIG. 2E), the desired The removal of heavy metal impurities injected into the a-Si film 14 together with impurities (i.e., boron) of is ensured. Therefore, compared with the conventional method in which heavy metal impurities are not removed, the initial characteristic deterioration of the TFT (i.e., the semiconductor device 1) including the pair of source / drain regions 20a and 20b is also improved, and the reliability is improved. This is improved. This means that the operation characteristics and the reliability of the TFT are improved.

In addition, unlike the structure disclosed in Japanese Patent Laid-Open No. 2003-332349, where alignment marks are only disposed on the edge of the substrate, the first alignment marks 18a and 18b are formed in the polysilicon film 35. It is formed near the pair of source / drain regions 20a and 20b and the second alignment marks 47a and 47b are formed near the outer side of the polysilicon island 45. Therefore, the first alignment marks 18a and 18b may not be arranged or arranged in an upper pattern (e.g., a pattern for the gate electrode / wiring 55) with respect to the source / drain regions 20a and 20b. Can be used. Similarly, the second alignment marks 47a and 47b may be used to arrange or arrange the upper pattern with respect to the island 45. In conclusion, there is an additional advantage that the arrangement accuracy higher than that of any conventional one can be obtained for the upper pattern.

Second Embodiment

(Method of manufacturing semiconductor device)

Next, a method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 3A to 3I.

The method according to the second embodiment corresponds to the addition of a process step of injecting impurities for threshold control into the channel region of the TFT to the method of the first embodiment. Therefore, the semiconductor device 1a manufactured by the method of the second embodiment corresponds to that obtained by adding an impurity injection region for threshold control to the channel region of the TFT of the semiconductor device 1 of the first embodiment.

First, in the method of the first embodiment, the process steps shown in Figs. 2A to 2E are performed. As such, as shown in FIG. 2E, the surface-etched p-type impurity implantation regions 18a ″ and 18b ″ and the surface etched p-type impurity implantation regions 20a ″ and 20b ″ are formed. It is formed in the a-Si film 14. In this etching step, the etching depth of the a-Si film 14 is selectively determined within the range of 10 Pa to 100 Pa, similarly to the first embodiment. In this way, by performing a series of operations of molding, exposing and developing the resist film for the mask 16, implanting impurities into the a-Si film 14, and selective etching of the a-Si film 14 only once. Surface-etched impurity implantation regions 18a 'and 18b' and surface-etched impurity implantation regions 20a 'and 20b' are obtained.

Next, after removing the mask 16, the p-type impurity (i.e., boron) for threshold control of the TFT is a-Si at a dose of 1 x 10 ¹² cm ^-2 as shown in FIG. 3A. Ions are implanted into the membrane 14. Since the ion implantation process is performed for the entire surface of the substrate 10, the p-type impurity ions are not only p-type impurity implantation regions 18a '', 18b '', 20a '', 20b ''. It is also injected into the rest of the a-Si film 14. Here, the p-type impurity injection regions 18a '' and 18b '' into which the p-type impurity is implanted are denoted as 18aa '' and 18bb '', respectively. Similarly, the p-type impurity implantation regions 20a '' and 20b '' into which the p-type impurity is implanted are denoted as 20aa '' and 20bb '', respectively. The p-type impurity implantation regions of the a-Si film 14 other than the regions 18aa '', 18bb '', 20aa '', and 20bb '' are designated by 14a. The state at this stage is shown in FIG. 3A.

Here, the concentration of the p-type impurity implanted for the threshold control is at least one dimension lower than the concentration of the impurity implanted in the regions 18aa ″, 18bb ″, 20aa ″, 20bb ″. Therefore, the p-type impurity implanted for threshold control does not affect the operation of the TFT.

Next, similar to the step of FIG. 2F in the first embodiment, the entire surface of the a-Si film 14 by the ELA method {p-type) so that the excimer laser light B crystallizes the a-Si film 14. Including impurity implantation regions 18aa '', 18bb '', 20aa '', 20bb '', and 14a, thereby forming a polysilicon film 35a, as shown in FIG. 3B. do. At this time, p-type impurities (eg, boron) present in the impurity injection regions 20aa '' and 20bb '' are activated by the laser light B, and an additional process for activation of the impurities is performed. The step becomes unnecessary. In addition, due to the crystallization of the a-Si film 14, the p-type impurity implantation regions 18aa '' and 18bb '' become the first alignment marks 18aa and 18bb, respectively, and the p-type impurity The injection regions 20aa '' and 20bb '' become source / drain regions 20aa and 20bb, respectively. The p-type impurity implantation region 14a becomes an impurity implantation region 35aa.

The subsequent process steps are the same as in the method of the first embodiment. Specifically, as shown in Fig. 3C (see Fig. 2G), a photosensitive resist film is coated on the polysilicon film 35, and then exposed and developed, thereby thereby making the polysilicon island 45a and the second alignment marks A mask 39a for forming 47aa and 47bb is formed. The mask 39a has a pattern including a portion 40a for forming the polysilicon island 45a and portions 42aa and 42bb for forming the second alignment marks 47aa and 47bb, and the mask The remainder of 39a is removed. The arrangement of the mask 39a is performed using previously formed first alignment marks 18aa and 18bb. Since the first alignment marks 18aa and 18bb are disposed near the source / drain regions 20aa and 20bb, respectively, the arrangement of the mask 39a is performed with an accuracy of ± 0.1 μm or less on the entire substrate 10. Can be. This is superior to the method disclosed in Japanese Patent Laid-Open No. 2003-332349, in which the obtainable arrangement accuracy of the TFTs is ± 0.3 μm or more.

Next, as shown in Fig. 3D (see Fig. 2H), the polysilicon film 35a is selectively etched using the mask 39a, whereby the island-type polysilicon film 35a, i.e., the polysilicon island ( 45a). At the same time, a pair of second alignment marks 47aa and 47bb are formed near the island 45a on each side of the polysilicon island 45a. This island 45a includes a pair of p-type source / drain regions 20aa and 20bb and a channel region 20cc.

Next, as shown in FIG. 3E (see FIG. 2I), the gate insulating film 50 (here, an SiO ₂ film having a thickness of 1000 μs) is formed of the polysilicon island 45a and the second alignment marks 47aa and 47bb. It is formed on the base film 12 so as to cover. The gate insulating film 50 covers the entire surface of the substrate 10. The material and thickness of this gate insulating film 50 may be the same as those in the method of the first embodiment.

Next, as shown in FIG. 3F (see FIG. 2J), a gate electrode / wiring 55 is formed on the gate insulating film 50. Similarly to the first embodiment, the gate electrode / wiring 55 is formed by a Cr film patterned to a thickness of 2000 k ?. The arrangement in the forming process of the gate electrode / wiring 55 is performed using the polysilicon island 45a and the second alignment marks 47aa and 47bb.

Next, as shown in FIG. 3G (see FIG. 2K), an interlayer insulating film 60 (formed by a SiO ₂ film with a thickness of 4000 s) is formed on the gate insulating film 50 to cover the gate electrode / wiring 55. Is formed. The interlayer insulating film 60 covers the entire surface of the substrate 10. The surface of the interlayer insulating film 60 is planarized by a known method.

Next, as shown in FIG. 3H (see FIG. 2L), a pair of contact holes 65a and 65b are formed to penetrate the interlayer insulating film 60 and the gate insulating film 50 by a known method. These contact holes 65a and 65b reach the source / drain regions 20aa and 20bb of the polysilicon island 45a, respectively.

Next, as shown in FIG. 3I (see FIG. 2M), a metal film is formed on the interlayer insulating film 60 and patterned in a known manner, whereby a pair of source / drain wirings on the interlayer insulating film 60 are formed. Fields 70a and 70b are formed. These source / drain lines 70a and 70b are connected to the source / drain regions 20aa and 20bb mechanically and electrically through contact holes 65a and 65b, respectively.

Through the above-described process steps, a TFT (that is, polysilicon TFT) having a polysilicon film 35a as an active layer is completed on the substrate 10. As a result, the semiconductor device 1a according to the second embodiment is manufactured. The apparatus 1a is the apparatus of the first embodiment except that the p-type impurity injection regions 35aa are formed on the surface of the channel region 20cc and the surfaces of the second alignment marks 47aa and 47bb, respectively. It is the same as the structure in (1).

In the above-described method of manufacturing the semiconductor device 1a according to the second embodiment, for the same reason as the method of the first embodiment, the same advantages as those in the first embodiment listed below (a), (b) ) And (c) are obtained.

(a) The total process steps required for the manufacture of the semiconductor device 1a are reduced, and the manufacturing cost thereof is reduced.

(b) The operation characteristics and reliability of the TFT (that is, the device 1a) are improved.

(c) Higher array accuracy is obtained for the upper patterns than anything else.

In addition, in the second embodiment, the same advantages as in the following (d) are also obtained.

(d) The threshold of the TFT is well adjusted or controlled.

(Third Embodiment)

(Method of manufacturing semiconductor device)

Next, a method of manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. 4A to 4M.

The method of the third embodiment forms two different conductivity types (i.e., n-channel and p-channel) TFTs in the method of the first embodiment, in which one conductive type (i.e., n-channel or p-channel) TFTs are formed. Corresponds to that obtained by Therefore, the semiconductor device 1b manufactured by the method of the third embodiment corresponds to that obtained by changing the semiconductor device 1 of the first embodiment to a complementary type.

First, as shown in FIG. 4A, an underlying insulating film 12 (formed by a SiO ₂ film having a thickness of 5000 kPa) is formed on a glass substrate (i.e., substrate) 10 having a desired size. On the base film 12, an a-Si film 14 (600 mm thick) is formed. Thereafter, a photosensitive resist film having a desired thickness is formed on the a-Si film 14 by the coating method. This photosensitive resist film is patterned by exposure and development, whereby a mask 17A for forming a pair of first alignment marks 19Aa and 19Ab and a pair of source / drain regions 21Aa and 21Ab. To form. These process steps are performed in the same manner as those used in the second embodiment. The mask 17A includes openings 17Ac and 17Ad corresponding to the pair of first alignment marks 19Aa and 19Ab, and openings 17Aa corresponding to the pair of source / drain regions 21Aa and 21Ab. , 17Ab).

Next, as shown in Fig. 4B, a desired n-type impurity such as phosphorus (P) is selectively implanted into the a-Si film 14 by ion implantation using the mask 17A. In this ion implantation step, the dose is 1 × 10 ¹⁵ cm ^-2 . As a result, n-type impurity ions are selectively implanted into the a-Si film 14 through the openings 17Aa, 17Ab, 17Ac, 17Ad of the mask 17A. As such, a pair of n-type impurity implantation regions 21Aa 'and 21Ab' are formed in the a-Si film 14 and a pair of n-type impurity implantation regions 19Aa 'and 19Ab' are formed at the same time. do. Since the pair of n-type impurity implantation regions 19Aa 'and 19Ab' are formed together with the pair of n-type impurity implantation regions 21Aa 'and 21Ab' simultaneously, this method requires that alignment marks only be used for the substrate. There is a difference from the method disclosed in Japanese Laid-Open Patent Publication No. 2003-332349 formed on the edge of the. As a result, there is an advantage that alignment accuracy is improved in the subsequent exposing process of the a-Si film 14 to form the polysilicon island 45. Here, impurity implantation regions 19Aa ', 19Ab' (which later become first alignment marks 19Aa, 19Ab) are used for the arrangement.

In the step of Fig. 4B, the implantation depth of the n-type impurity ions (i.e., phosphorus ions) is set to almost the entire thickness of the a-Si film 14. As such, the implanted impurity ions spread throughout the thickness of the film 14 due to the subsequent activation process of the impurity ions. Further, impurity implantation regions 19Aa 'and 19Ab' are formed near impurity implantation regions 21Aa 'and 21Ab', respectively, by the ion implantation step of FIG. 4B. However, the impurity implantation regions 19Aa 'and 19Ab' do not affect the TFT characteristics. This is because the impurity injection regions 19Aa 'and 19Ab' are removed in a later process.

Next, as shown in FIG. 4C, the surfaces of the n-type impurity implantation regions 19Aa 'and 19Ab' of the a-Si film 14 and the n-type impurity implantation regions 21Aa 'and 21Ab'. The surfaces of are selectively etched using the same mask 17A. After the etching process is completed, the mask 17A is removed. Here, the surface-etched impurity implantation regions 19Aa 'and 19Ab' are denoted by 19Aa '' and 19Ab '', respectively. Similarly, the surface-etched impurity implantation regions 21Aa 'and 21Ab' are designated as 21Aa '' and 21Ab '', respectively.

In the etching process of Fig. 4C, the etching depth of the a-Si film 14 is set to 50 mV similarly to the first embodiment.

As described above, the surface-etched n-type impurity implantation regions 19Aa 'by simply performing a series of operations such as resist film forming, exposure and development thereof, and etching of the a-Si film 14, and the like. ', 19Ab' ', 21Aa' ', 21Ab' ') are obtained in the a-Si film 14. Thereafter, the mask 17A is removed.

As shown in Fig. 4C, the surfaces of the n-type impurity implantation regions 21Aa '' and 21Ab '', which will later be n-type source / drain regions 21Aa and 21Ab, are etched away. As such, the heavy metal impurities introduced into the a-Si film 14 together with the desired n-type impurity ions are removed. According to the inventors' experiments, it was found that the initial characteristic degradation of the TFT including the source / drain regions 21Aa and 21Ab is improved by at least 10% compared to the conventional method in which heavy metal impurities are not removed. In addition, it has been found that the reliability of the TFT is more than doubled in the conventional method in which heavy metal impurities are not removed.

Next, as shown in FIG. 4D, a photosensitive resist film having a desired thickness is formed on the a-Si film 14, and patterned by exposure and development, whereby a p-type source of the p-channel TFT A mask 17B for forming the / drain regions 21Ba and 21Bb is formed. The method of forming this mask 17B is the same as the method of forming the mask 17A. The mask 17B has openings 17Ba and 17Bb corresponding to the pair of p-type source / drain regions 21Ba and 21Bb.

Next, as shown in Fig. 4E, a desired p-type impurity such as boron (B) is selectively introduced into the a-Si film 14 by ion implantation using the mask 17B. In this ion implantation step, the dose is 1 × 10 ¹⁵ cm ^-2 . As a result, p-type impurity ions are selectively implanted into the a-Si film 14 through the openings 17Ba and 17Bb of the mask 17B. As such, a pair of p-type impurity implantation regions 21Ba 'and 21Bb' are formed between the impurity implantation regions 21b '' and 19b ''. The surfaces of the impurity injection regions 21Ba ', 21Bb' are not etched.

In the step of FIG. 4E, the implantation depth of the p-type impurity ions (ie, B ions) is set to a value required for forming the p-type source / drain regions 21Ba and 21Bb. This depth will be lower than that of the n-type impurity ions in the step of FIG. 4B. This is because the surfaces of the impurity injection regions 21Ba 'and 21Bb' have not been etched.

As described above, p-type impurity implantation regions 21Ba 'and 21Bb' are formed in the a-Si film 14 by simply performing a series of operations such as resist film formation, its exposure and development, etc. only at once. ) (The surface is not etched) is obtained. Thereafter, the mask 17B is removed.

Next, as shown in FIG. 4F, the excimer laser light B crystallizes the a-Si film 14 by the ELA method to form the a-Si film 14 {n-type impurity implantation regions 19Aa '. ', 19Ab', 21Aa ', 21Ab'), and p-type impurity implantation regions 21Ba ', 21Bb') are irradiated to the entire surface of the polysilicon film 35b. To form. At this point, the n-type impurities (i.e., phosphorus) and the p-type impurity injection regions 21Ba 'and 21Bb' are injected into the n-type impurity injection regions 21Aa '' and 21Ab ''. The p-type impurity (ie boron) is activated and therefore no additional activation process for the implanted impurities is required. Further, due to the crystallization of the a-Si film 14, the n-type impurity implantation regions 19Aa '' and 19Ab '' become first alignment marks 19Aa and 19Ab, respectively. Similarly, the n-type impurity implantation regions 21Aa '' and 21Ab '' become n-type source / drain regions 21Aa and 21Ab, respectively. The p-type impurity implantation regions 21Ba 'and 21Bb' become p-type source / drain regions 21Ba and 21Bb, respectively.

Next, as shown in FIG. 4G, a photosensitive resist film is formed on the polysilicon film 35b by a coating process, and the photosensitive resist film is exposed and developed to form the polysilicon islands 45a and 45b and the second alignment. A mask 39a for forming the marks 47a and 47b is formed. This mask 39a is part 40a for forming polysilicon island 45a (for n-channel TFT) and part 40b for forming polysilicon island 45b (for p-channel TFT) ) And portions 42a and 42b for forming the second alignment marks 47a and 47b, and the remaining portions of the mask 39a are removed. The arrangement of the mask 39a It is performed using the preformed first alignment marks 19Aa and 19Ab. Since the first alignment marks 19Aa and 19Ab are disposed near the n-type source / drain region 21Aa and the p-type source / drain regions 21Bb, respectively, the arrangement of the mask 39a is ± 0.1. It can be performed with an accuracy of less than or equal to μm.

Here, for the sake of simplicity, a description will be given of a pair of n- and p-channel TFTs formed on the substrate 10. In practice, however, many pairs of n- and p-channel TFTs are arranged in a matrix arrangement on the substrate 10. In the third embodiment of the present invention, the first alignment marks 19Aa and 19Ab are disposed near the n-type source / drain region 21Aa and the p-type source / drain regions 21Bb, respectively. Therefore, the first alignment marks 19Aa and 19Ab are arranged on the entire substrate 10 according to the arrangement or layout of the source / drain regions 21Aa, 21Ab, 21Ba, 21Bb. Thus, the arrangement of the TFTs can be performed with an accuracy of ± 0.1 mu m or less. On the other hand, in the method disclosed in Japanese Patent Laid-Open No. 2003-332349, alignment marks are only arranged at the edge of the substrate. Therefore, the arrangement accuracy of the obtained TFTs will be ± 0.3 µm or more, which is considerably deteriorated compared to the above embodiment of the present invention.

Next, as shown in FIG. 4H, the polysilicon film 35b is selectively etched using the mask 39a, whereby the island type polysilicon film 35b, i.e., polysilicon islands 45A and 45B To form. At the same time, a pair of second alignment marks 47a and 47b are formed near the islands 45A and 45B by the polysilicon film 35b, respectively. Island 45A includes a pair of n-type source / drain regions 21Aa and 21Ab, and a channel region 21Ac disposed between source / drain regions 21Aa and 21Ab. Similarly, island 45B includes a pair of p-type source / drain regions 21Ba and 21Bb and a channel region 21Bc disposed between the source / drain regions 21Ba and 21Bb. As can be seen from Fig. 4H, the first alignment marks 19Aa and 19Ab are removed in this step.

Next, as shown in FIG. 4I, the gate insulating film 50 (here, 1000 microseconds) is formed on the base film 12 to cover the polysilicon islands 45A and 45B and the second alignment marks 47a and 47b. SiO ₂ film having a thickness) is formed. The gate insulating film 50 covers the entire surface of the substrate 10. The method for forming the film 50 may be the same as that of the first embodiment.

Next, as shown in Fig. 4J, gate electrodes / wirings 55a and 55b (here, formed of a patterned Cr film having a thickness of 2000 microseconds) are superimposed on the channel regions 21Ac and 21Bc, respectively. Is formed on the gate insulating film 50. The method for forming these gate electrodes / wirings 55a and 55b may be the same as in the first embodiment. The arrangement in this process is performed using the polysilicon islands 45A and 45B and the second alignment marks 47a and 47b.

Next, as shown in FIG. 4K, an interlayer insulating film 60 (here, an SiO ₂ film having a thickness of 4000 μs) is formed on the gate insulating film 50 so as to cover the gate electrodes / wirings 55a and 55b. . The interlayer insulating film 60 covers the entire surface of the substrate 10. The surface of the interlayer insulating film 60 is planarized by a known method.

Next, as shown in FIG. 4L, the interlayer insulating film 60 and the gate insulating film 50 are formed by a pair of contact holes 65a and 65b and a pair of contact holes 65c and 65d in a known manner. It is formed to penetrate through. The holes 65a and 65b reach the n-type source / drain regions 21Aa and 21Ab of the polysilicon island 45A, respectively. The holes 65c and 65d reach the p-type source / drain regions 21Ba and 21Bb of the polysilicon island 45B, respectively.

Next, as shown in FIG. 4M, a metal film is disposed on the interlayer insulating film 60 and patterned by a known method, whereby a pair of source / drain wires 70a and 70b are placed on the interlayer insulating film 60. ) And a pair of source / drain lines 70c and 70d. Source / drain lines 70a and 70b are connected to n-type source / drain regions 21Aa and 21Ab mechanically and electrically through contact holes 65a and 65b, respectively. Source / drain wires 70c and 70d are connected to p-type source / drain regions 21Ba and 21Bb mechanically and electrically through contact holes 65c and 65d, respectively.

Through the process steps described above, a pair of n- and p-channel TFTs (i.e., a pair of n- and p-channel polysilicon TFTs) each having polysilicon islands 45A and 45B as their active layers ) Is completed on the substrate 10. As a result, the semiconductor device 1b according to the third embodiment is obtained.

In the manufacturing method of the semiconductor device 1b according to the third embodiment described above, formation, exposure and development of a resist film for the mask 17A, implantation of impurities into the a-Si film 14, and a-Si film By performing a series of operations of the selective etching of Fig. 14 (FIGS. 4A to 4C) only once, the surface-etched n-type impurity implantation regions 19Aa &quot; and 19Ab &quot; Water injection regions 21Aa '' and 21Ab '' are obtained. Similarly, by performing a series of operations of formation, exposure and development of a resist film for the mask 17B, and implantation of impurities into the a-Si film 14 (FIGS. 4D to 4E) only once, surface-etching is performed. P-type impurity implantation regions 21Ba 'and 21Bb' are obtained.

Furthermore, the a-Si film 14 is crystallized by scanning the laser light B over the entire surface of the a-Si film 14 containing n- and p-type impurity ions, thereby producing a polysilicon film ( 35b) is formed (FIG. 4F). As such, at the same time as the crystallization of the a-Si film 14, the n-type in the n-type impurity implantation regions 21Aa '' and 21Ab '' (which will later be the source / drain regions 21Aa and 21Ab). P-type impurity ions (i.e., phosphorus ions) and p-type impurity implantation regions 21Ba ', 21Bb' (which will later become source / drain regions 21Ba, 21Bb) (i.e. Boron ions) are activated.

Therefore, no additional processing step for activating the n- and p-type impurity ions is required. Thus, the total number of manufacturing process steps required for the semiconductor device 1b according to the third embodiment is reduced, as well as the manufacturing cost is reduced.

Moreover, since the surfaces of the n-type impurity implantation regions 21Aa '' and 21Ab '' (which will later become the source / drain regions 21Aa and 21Ab) are selectively etched (FIG. 4C), the desired n The removal of undesirable heavy metal impurities injected into the a-Si film 14 together with the -type impurities (i.e. phosphorus) is ensured. Therefore, the initial characteristic degradation of the n-channel TFT including the pair of n-type source / drain regions 21Aa and 21Ab is improved and its reliability is high compared with the conventional method in which heavy metal impurities are not removed. This means that the operation characteristics and reliability of the TFT (therefore, the device 1b) are improved.

Additionally, unlike the structure disclosed in Japanese Patent Laid-Open No. 2003-332349, where alignment marks are only disposed on the edge of the substrate, the first alignment marks 19Aa and 19Ab are formed in the polysilicon film 35b. formed near the n-type source / drain region 21Aa and p-type source / drain region 21Bb, and second alignment marks 47a and 47b are formed near the polysilicon islands 45A and 45B, respectively. It is. Therefore, the first alignment marks 19Aa and 19Ab may be used for the top pattern or the arrangement of the patterns with respect to the source / drain regions 21Aa, 21Ab, 21Ba and 21Bb. The second alignment marks 47a and 47b may be used for the top pattern or the arrangement of the patterns with respect to the polysilicon islands 45A and 45B. In conclusion, there is an additional advantage that the arrangement accuracy higher than that of any conventional one can be obtained for the upper patterns for the n- and p-channel TFTs.

(Example 4)

(Method of manufacturing semiconductor device)

Next, a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS. 5A to 5L.

The method of the fourth embodiment corresponds to that obtained by adding process steps of injecting n- and p-type impurities into the channel regions of the threshold control n- and p-channel TFTs, respectively, to the method of the third embodiment. Therefore, the semiconductor device 1c manufactured by the method of the fourth embodiment adds impurity implantation regions for threshold control to the channel regions of the n- and p-channel TFTs in the semiconductor device 1b of the third embodiment, respectively. Corresponds to that obtained.

First, the process steps of Figs. 4A to 4E in the method of the third embodiment are performed. Therefore, as shown in Fig. 4E, a pair of n-type impurity implantation regions 19Aa '' and 19Ab '', a pair of n-type impurity implantation regions 21Aa '' and 21Ab '', And a pair of p-type impurity implantation regions 21Ba 'and 21Bb' are formed in the a-Si film 14. The surfaces of the n-type impurity implantation regions 19Aa '', 19Ab '', 21Aa '', and 21Ab '' are etched away, but the p-type impurity implantation regions 21Ba ', 21Bb' are not etched. Do not. In the etching process of Fig. 4C, the etching depth of the a-Si film 14 is set to 50 kV similar to that of the first embodiment. After the ion implantation process of the p-type impurity, the mask 17B is removed.

Next, as shown in FIG. 5A, a mask 26 having one opening 26a is formed on the a-Si film 14. This opening 26a is disposed at a position corresponding to the channel region 21Ac of the n-channel TFT. Then, as shown in Fig. 5B, p-type impurity ions (e.g., boron ions) for adjusting the threshold of the n-channel TFT are formed using an a-Si film (using a mask 26). 14) optionally injected into the stomach. In this ion implantation step, the dose is set to 1 x 10 ¹² cm ^-2 . As such, the p-type impurity ions are selectively implanted into the a-Si film 14 through the opening 26a of the mask 26, and as a result, the p-type impurity implantation region (a) in the a-Si film 14 14b1). After completion of the ion implantation process, the mask 26 is removed.

Next, as shown in FIG. 5C, a mask 28 having an opening 28a is formed on the a-Si film 14. This opening 28a is disposed at a position corresponding to the channel region 21Bc of the p-channel TFT. Then, as shown in Fig. 5D, n-type impurity ions (e.g., phosphorus ions) for adjusting the threshold of the TFT are introduced into the a-Si film 14 using the mask 28. Is optionally injected. In this ion implantation step, the dose is set to 1 x 10 ¹² cm ^-2 . As such, the n-type impurity ions are selectively implanted into the a-Si film 14 through the opening 28a of the mask 28, and as a result, the n-type impurity implantation region (a) in the a-Si film 14 14b2). After completion of the ion implantation process, the mask 28 is removed.

Subsequent process steps are the same as in the third embodiment. Specifically, as shown in FIG. 5E (FIG. 4F), the excimer laser light B is irradiated to the entire surface of the a-Si film 14 by ELA method to crystallize the a-Si film 14 Thus, the polysilicon film 35c is formed. At this point, n-type impurities (i.e., phosphorus) and p-type impurity injection regions 21Ba ', 21Bb', implanted into the n-type impurity injection regions 21Aa '', 21Ab '', and 14b2, And the p-type impurity (ie boron) implanted in 14b1) is activated and therefore no additional activation process for the implanted impurities is required. Further, due to the crystallization of the a-Si film 14, the n-type impurity implantation regions 19Aa '' and 19Ab '' become first alignment marks 19Aa and 19Ab, respectively. Similarly, the n-type impurity implantation regions 21Aa '' and 21Ab '' become n-type source / drain regions 21Aa and 21Ab of the n-channel TFT, respectively. The p-type impurity implantation region 14b1 becomes the p-type impurity implantation region 35c1 of the n-channel TFT. The p-type impurity implantation regions 21Ba '' and 21Bb '' become the p-type source / drain regions 21Ba and 21Bb of the p-channel TFT, respectively. The n-type impurity implantation region 14b2 becomes the n-type impurity implantation region 35c2 of the p-channel TFT.

Next, as shown in FIG. 5F (FIG. 4G), a mask 39a is formed on the polysilicon film 35c. The mask 39a comprises a portion 40a for forming the polysilicon island 45A ', a portion 40b for forming the polysilicon island 45B', and second alignment marks 47a and 47b. It has a pattern including portions 42a and 42b for forming, and the remaining portions of the mask 39a are removed. The arrangement of the mask 39a is performed using preformed first alignment marks 19Aa and 19Ab. Since the first alignment marks 19Aa and 19Ab are disposed near the n-type source / drain region 21Aa and the p-type source / drain regions 21Bb, respectively, the arrangement of the mask 39a is ± 0.1. It can be performed with an accuracy of less than or equal to μm.

Next, as shown in FIG. 5G (FIG. 4H), the polysilicon film 35c is selectively etched using the mask 39a, whereby the island-type polysilicon film 35c, i.e., polysilicon islands ( 45A ', 45B'). At the same time, a pair of second alignment marks 47a and 47b are formed near the islands 45A 'and 45B' by the polysilicon film 35c, respectively. Island 45A 'includes a pair of n-type source / drain regions 21Aa and 21Ab, and a channel region 21Ac disposed between source / drain regions 21Aa and 21Ab. Similarly, island 45B 'includes a pair of p-type source / drain regions 21Ba and 21Bb and a channel region 21Bc disposed between source / drain regions 21Ba and 21Bb.

Next, as shown in FIG. 5H (FIG. 4I), the gate insulating film 50 on the base film 12 to cover the polysilicon islands 45A 'and 45B' and the second alignment marks 47a and 47b. ) Is formed. The gate insulating film 50 covers the entire surface of the substrate 10. The method for forming the film 50 may be the same as that of the third embodiment.

Next, as shown in FIG. 5I (FIG. 4J), gate electrodes / wires 55a and 55b are formed on the gate insulating film 50. The method for forming these gate electrodes / wirings 55a and 55b may be the same as in the third embodiment. The arrangement in this process is carried out using polysilicon islands 45A ', 45B' and second alignment marks 47a, 47b.

Next, as shown in FIG. 5J (FIG. 4K), an interlayer insulating film 60 is formed on the gate insulating film 50 so as to cover the gate electrodes / wires 55a and 55b. The interlayer insulating film 60 covers the entire surface of the substrate 10. The formation method of this film 60 may be the same as that of the third embodiment. The surface of the interlayer insulating film 60 is planarized by a known method.

Next, as shown in FIG. 5K (FIG. 4L), the interlayer insulating film 60 and the gate insulating film are in a known manner by the pair of contact holes 65a and 65b and the pair of contact holes 65c and 65d. It is formed to penetrate 50. The holes 65a and 65b reach the n-type source / drain regions 21Aa and 21Ab of the polysilicon island 45A ', respectively. The holes 65c and 65d reach the p-type source / drain regions 21Ba and 21Bb of the polysilicon island 45B ', respectively.

Next, as shown in FIG. 5L (FIG. 4M), a metal film is disposed on the interlayer insulating film 60 and patterned by a known method, whereby a pair of source / drain wirings on the interlayer insulating film 60 70a and 70b and a pair of source / drain lines 70c and 70d are formed. Source / drain lines 70a and 70b are connected to n-type source / drain regions 21Aa and 21Ab mechanically and electrically through contact holes 65a and 65b, respectively. Source / drain wirings 70c and 70d are connected to p-type source / drain regions 21Ba and 21Bb mechanically and electrically through contact holes 65c and 65d, respectively.

Through the above-described process steps, a pair of n- and p-channel TFTs (that is, n- and p-channel polysilicon TFTs) having a polysilicon film 35c as an active layer is completed on the substrate 10. do. As a result, the semiconductor device 1c according to the fourth embodiment is obtained.

In the above-described semiconductor device 1c according to the fourth embodiment and the manufacturing method of the device 1c, for the same reasons as those in the semiconductor device 1 and the manufacturing method according to the first embodiment, the following ( The advantages of a) to (d) are obtained.

(a) The total number of process steps required for manufacturing the semiconductor device 1c according to the fourth embodiment is reduced, and the manufacturing cost thereof is reduced.

(b) The operating characteristics and reliability of the n-channel TFT (therefore, the device 1C) are improved.

(c) Higher array accuracy is obtained for the upper patterns.

(d) The threshold of n- and p-channel TFTs is well controlled or adjustable.

(Example 5)

(Method of manufacturing semiconductor device)

Next, a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. 6A to 6I.

The method of the fifth embodiment is a process of implanting impurities (n-type or p-type) into the channel regions of the n- and p-channel TFTs for threshold control in the method of the third embodiment, similarly to the method of the fourth embodiment. Corresponds to that obtained by adding steps. However, the method of the fifth embodiment differs from the method of the fourth embodiment in that the ion implantation step of the impurity for threshold control is performed on the entire surface of the substrate 10 without using any mask.

First, the process steps of Figs. 4A to 4E in the method of the third embodiment are performed. As such, as shown in FIG. 4E, a pair of surface-etched n-type impurity implantation regions 19Aa ″ and 19Ab ″ and a pair of surface-etched n-type impurity implantation regions 21Aa ″. , 21Ab ''), and a pair of surface-non-etched p-type impurity implantation regions 21Ba 'and 21Bb' are formed. In the etching process of Fig. 4C, the etching depth of the a-Si film 14 is set to 50 mV similarly to the first embodiment. After the ion implantation process of the p-type impurity, the mask 17B is removed.

Next, as shown in Fig. 6A, the n- or p-type impurity ions (e.g., boron ions) are a-Si film without any mask to control the threshold of the n- and p-channel TFTs. It is injected into the entire surface of (14). In this ion implantation step, the dose is set to 1 x 10 ¹² cm ^-2 . As such, the p-type impurity ions (ie, boron ions) are not only the n-type impurity implantation regions 19Aa '', 19Ab '', 21Aa '', and 21Ab '' but also the p-type impurity implantation region. It is also injected into the fields 21Ba 'and 21Bb'. P-type impurity implantation regions 14b are also formed on the remaining surface of the film 14 other than these regions 19Aa '', 19Ab '', 21Aa '', 21Ab '', 21Ba ', and 21Bb'. .

The concentration of the impurity (ie, boron) implanted for the threshold control is higher than the concentration of the impurity in the n-type impurity implantation regions 21Aa '' and 21Ab '' and the p-type impurity implantation regions 21Ba '', 21 Bb '') is at least one dimension or scale lower than the concentration of impurities. Therefore, the impurity implanted for threshold control does not affect the operation of the n- and p-channel TFTs.

The subsequent process steps are the same as in the third embodiment. Specifically, as shown in FIG. 6B (FIG. 4F), the excimer laser light B is irradiated onto the entire surface of the a-Si film 14 by the ELA method in order to crystallize the a-Si film 14. Thus, the polysilicon film 35d is formed. At this point, n-type impurities (i.e., phosphorus) and p-type impurity injection regions 21Ba ', 21Bb', and 14b present in the n-type impurity injection regions 21Aa '' and 21Ab ''. The p-type impurity (ie boron) present in is activated and therefore no additional activation process for the implanted impurities is required. Further, due to the crystallization of the a-Si film 14, the n-type impurity implantation regions 19Aa '' and 19Ab '' become first alignment marks 19Aa and 19Ab, respectively. Similarly, the n-type impurity implantation regions 21Aa '' and 21Ab '' become n-type source / drain regions 21Aa and 21Ab of the n-channel TFT, respectively. The p-type impurity implantation regions 21Ba 'and 21Bb' become the p-type source / drain regions 21Ba and 21Bb of the p-channel TFT, respectively. The p-type impurity implantation regions 14b become the p-type impurity implantation regions 35dd.

Next, as shown in Fig. 6C (Fig. 4G), a mask 39a is formed on the polysilicon film 35d. The mask 39a has a portion 40a for forming the polysilicon island 45A '', a portion 40b for forming the polysilicon island 45B '', and second alignment marks 47a, 47b. Has a pattern including portions 42a and 42b to form the remaining portions of the mask 39a. The arrangement of the mask 39a is performed using preformed first alignment marks 19Aa and 19Ab. Since the first alignment marks 19Aa and 19Ab are disposed near the n-type source / drain region 21Aa and the p-type source / drain regions 21Bb, respectively, the arrangement of the mask 39a is ± 0.1. It can be performed with an accuracy of less than or equal to μm.

Next, as shown in Fig. 6D (Fig. 4H), the polysilicon film 35d is selectively etched using the mask 39a, whereby the island-type polysilicon film 35d, i.e., polysilicon islands ( 45A '', 45B ''). At the same time, a pair of second alignment marks 47a and 47b are formed near the islands 45A '' and 45B '' by the polysilicon film 35d, respectively. Island 45A '' includes a pair of n-type source / drain regions 21Aa and 21Ab and a channel region 21Ac disposed between source / drain regions 21Aa and 21Ab. Similarly, island 45B '' includes a pair of p-type source / drain regions 21Ba and 21Bb and a channel region 21Bc disposed between the source / drain regions 21Ba and 21Bb. .

Next, as shown in FIG. 6E (FIG. 4I), a gate insulating film on the underlayer 12 to cover the polysilicon islands 45A '' and 45B '' and the second alignment marks 47a and 47b. 50 is formed. The gate insulating film 50 covers the entire surface of the substrate 10. The method for forming the film 50 may be the same as that of the third embodiment.

Next, as shown in FIG. 6F (FIG. 4J), gate electrodes / wires 55a and 55b are formed on the gate insulating film 50. The method for forming these gate electrodes / wirings 55a and 55b may be the same as in the third embodiment. The arrangement in this process is carried out using polysilicon islands 45A '', 45B '' and second alignment marks 47a, 47b.

Next, as shown in Fig. 6G (Fig. 4K), an interlayer insulating film 60 is formed on the gate insulating film 50 so as to cover the gate electrodes / wires 55a and 55b. The interlayer insulating film 60 covers the entire surface of the substrate 10. The method of forming this film 60 may be the same as in the third embodiment. The surface of the interlayer insulating film 60 is planarized by a known method.

Next, as shown in FIG. 6H (FIG. 4L), the interlayer insulating film 60 and the gate insulating film are known by a pair of contact holes 65a and 65b and a pair of contact holes 65c and 65d. It is formed to penetrate 50. The holes 65a and 65b reach the n-type source / drain regions 21Aa and 21Ab of the polysilicon island 45A '', respectively. The holes 65c and 65d reach the p-type source / drain regions 21Ba and 21Bb of the polysilicon island 45B ″, respectively.

Next, as shown in FIG. 6I (FIG. 4M), a metal film is disposed on the interlayer insulating film 60 and patterned by a known method, whereby a pair of source / drain wirings on the interlayer insulating film 60. 70a and 70b and a pair of source / drain lines 70c and 70d are formed. Source / drain lines 70a and 70b are connected to n-type source / drain regions 21Aa and 21Ab mechanically and electrically through contact holes 65a and 65b, respectively. Source / drain wires 70c and 70d are connected to p-type source / drain regions 21Ba and 21Bb mechanically and electrically through contact holes 65c and 65d, respectively.

Through the above-described process steps, a pair of n- and p-channel TFTs (that is, n- and p-channel polysilicon TFTs) having a polysilicon film 35d as an active layer is completed on the substrate 10. do. As a result, the semiconductor device 1d according to the fifth embodiment is obtained.

The manufacturing method of the semiconductor device 1d according to the fifth embodiment is equivalent to that obtained by adding a process step of injecting impurities for threshold control into the channel region of the n- and p-channel TFTs to the method of the third embodiment. do. Therefore, the semiconductor device 1d manufactured by this method is applied to the semiconductor device obtained by adding the p-type impurity injection regions 35dd to the respective channel regions 21Ac and 21Bc of the n- and p-channel TFTs. It is considerable.

In the above-described semiconductor device 1d according to the fifth embodiment and the manufacturing method of the device 1c, for the same reasons as those in the semiconductor device 1 and the manufacturing method according to the first embodiment, the following ( The advantages of a) to (d) are obtained.

(a) The total number of process steps required for manufacturing the semiconductor device 1d according to the fifth embodiment is reduced, and the manufacturing cost thereof is reduced.

(b) The operating characteristics and reliability of the n-channel TFT (therefore, the device 1d) are improved.

(c) Higher array accuracy is obtained for the upper patterns.

(d) The threshold of n- and p-channel TFTs is well controlled or adjustable.

(Example 6)

(Method of manufacturing semiconductor device)

Next, a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIGS. 7A to 7J.

The method of the sixth embodiment is equivalent to that obtained by adding a process step of forming LDD (Lightly-Doped Drain) regions of the TFT in the method of the first embodiment. Therefore, the semiconductor device 1e according to the sixth embodiment corresponds to that obtained by adding the LDD structure to the semiconductor device 1 according to the first embodiment.

First, the process steps of Figs. 2A to 2E in the method of the first embodiment are performed. As such, as shown in FIG. 2E, a pair of surface-etched p-type impurity implantation regions 18a '' and 18b '' and a pair of surface-etched p-type impurity implantation regions 20a ' ', 20b' ') is formed in the a-Si film 14. The etching depth of the a-Si film 14 is set to 50 kV similarly to the first embodiment.

After removing the mask 16, as shown in FIG. 7A, a mask 30 for forming LDD regions is formed on the a-Si film 14. This mask 30 is obtained by forming a photosensitive resist film by coating, and exposing and developing this resist film. Thereafter, suitable impurities (here, boron) for forming LDD regions are selectively implanted into the a-Si film 14 using the mask 30. In this ion implantation step, the dose is set to 1 x 10 ¹³ cm ^-2 .

As such, p-type impurity ions (i.e., boron ions) are selectively implanted into the a-Si film 14 through the openings 30a, 30b of the mask 30 and thereby shown in FIG. 7B. As described above, a pair of p-type impurity implantation regions 22a '' and 22b '' is formed between the pair of p-type impurity implantation regions 20a '' and 20b ''. The p-type impurity injection regions 22a '' and 22b '' which are separated from each other are in contact with the p-type impurity injection regions 20a '' and 20b '', respectively. After the ion implantation is completed, the mask 30 is removed.

Subsequent process steps are the same as in the first embodiment. Specifically, as shown in FIG. 7C (FIG. 2F), the excimer laser light B is irradiated onto the entire surface of the a-Si film 14 by the ELA method in order to crystallize the a-Si film 14. Thus, the polysilicon film 35e is formed. At this time, the impurity (i.e., boron) implanted in the impurity implantation regions 20a '', 20b '', 22a '', and 22b '' is activated, and thus any additional activation process for the implanted impurities Is also not required. Furthermore, due to the crystallization of the a-Si film 14, the p-type impurity implantation regions 18a '' and 18b '' become the first alignment marks 18a and 18b, respectively, and the p-type impurity Injection regions 20a '' and 20b '' are respectively p-type source / drain regions 20a and 20b. The p-type impurity implantation regions 22a '' and 22b '' become p-type LDD regions 22a and 22b, respectively.

Next, as shown in FIG. 7D (FIG. 2G), a photosensitive resist film is formed on the polysilicon film 35e by coating, and then the resist film is exposed and developed, whereby the polysilicon island 45b and agent are formed. The mask 39 for forming the two alignment marks 47a and 47b is formed. The mask 39 has a pattern including a portion 40 for forming the polysilicon island 45b and portions 42a and 42b for forming the second alignment marks 47a and 47b. The remainder of (39) is removed. Alignment of the mask 39 is performed using previously formed first alignment marks 18a and 18b. Since the first alignment marks 18a and 18b are disposed near the source / drain regions 20a and 20b, respectively, the arrangement of the mask 39 can be performed with an accuracy of ± 0.1 mu m or less.

Next, as shown in FIG. 7E (FIG. 2H), the polysilicon film 35e is selectively etched using the mask 39, whereby the island-type polysilicon film 35e, i.e., the polysilicon island 45b ). At the same time, a pair of second alignment marks 47a and 47b are formed near the island 45b on each side of the island 45b. Island 45b is a channel disposed between a pair of p-type source / drain regions 20a and 20b, a pair of p-type LDD regions 22a and 22b and LDD regions 22a and 22b. The area 20c is included.

Next, as shown in FIG. 7F (FIG. 2I), the gate insulating film 50 is formed on the base film 12 to cover the polysilicon island 45b and the second alignment marks 47a and 47b. The gate insulating film 50 covers the entire surface of the substrate 10. This gate insulating film 50 may be formed in the same processes as used in the first embodiment.

Next, as shown in FIG. 7G (FIG. 2J), a gate electrode / wiring 55 is formed on the gate insulating film 50 so as to overlap the channel region 20c and the LDD regions 22a and 22b. The gate electrode / wiring 55 may be formed by the same processes as used in the first embodiment. The arrangement in this process is carried out using the polysilicon island 45b and the second alignment marks 47a and 47b.

Next, as shown in FIG. 7H (FIG. 2K), an interlayer insulating film 60 is formed on the gate insulating film 50 so as to cover the gate electrode / wiring 55. This film 60 covers the entire surface of the substrate 10. This film 60 may be formed by the same processes as used in the first embodiment. The surface of the interlayer insulating film 60 is planarized by a known method.

Next, as shown in FIG. 7I (FIG. 2L), a pair of contact holes 65a and 65b are formed to penetrate the interlayer insulating film 60 and the gate insulating film 50 by a known method. These contact holes 65a and 65b reach the source / drain regions 20a and 20b of the polysilicon island 45b, respectively.

Next, as shown in FIG. 7J (FIG. 2M), a metal film is formed on the interlayer insulating film 60 and patterned in a known manner, whereby a pair of source / drain wirings on the interlayer insulating film 60. (70a, 70b) are formed. These source / drain wires 70a and 70b are connected to the source / drain regions 20a and 20b mechanically and electrically through contact holes 65a and 65b, respectively.

Through the above-described process steps, a TFT (ie, polysilicon TFT) having a polysilicon film 35e as an active layer is completed on the substrate 10. As a result, the semiconductor device 1e according to the sixth embodiment is manufactured.

In the above-described semiconductor device 1e according to the sixth embodiment and the manufacturing method thereof, for the same reasons as those in the semiconductor device 1 and the manufacturing method according to the first embodiment, the following (a) to (d) Advantages are obtained.

(a) The total number of process steps required for manufacturing the semiconductor device 1e according to the sixth embodiment is reduced, and the manufacturing cost thereof is reduced.

(b) The operation characteristics and reliability of the TFT (therefore, the device 1e) are improved.

(c) Higher array accuracy is obtained for the upper patterns.

(d) Due to the LDD structure, the drain breakdown voltage of the TFT is improved.

(Other embodiments)

Since the above described first to sixth embodiments are concrete examples of the present invention, needless to say, the present invention is not limited to these examples and modifications. Any other change is possible to these examples and variations.

For example, in the third embodiment of the present invention described above, an impurity implantation process for the source / drain forming regions of the n-channel TFT is performed, and then an impurity for the source / drain forming region of the p-channel TFT is performed. Injection process is performed. However, the order of these two processes may be reversed. In other words, an impurity implantation process for the source / drain forming regions of the p-channel TFT may be performed, followed by an impurity implantation process for the source / drain forming regions of the n-channel TFT.

In the fourth embodiment of the present invention described above, an impurity implantation process for threshold control of the n-channel TFT is performed, followed by an impurity implantation process for threshold control of the p-channel TFT. However, the order of these two steps may be reversed. That is, an impurity implantation process for threshold control of the p-channel TFT may be performed, and then an impurity implantation process for threshold control of the n-channel TFT may be performed.

In the sixth embodiment described above, an impurity implantation process for forming the source / drain forming regions of the TFT is performed, followed by an impurity implantation process for forming the LDD regions. However, the order of these two processes may be reversed. In other words, an impurity implantation process for forming the LDD regions of the TFT may be performed, and then an impurity implantation process for the source / drain forming region may be performed.

While the preferred forms of the invention have been disclosed, it will be apparent to those skilled in the art that various changes may be made without departing from the spirit of the invention. Therefore, the scope of the present invention is determined by the claims that follow.

As described above, the semiconductor device and the manufacturing method thereof according to the present invention can reduce the total number of necessary process steps, thus reducing the manufacturing cost and improving the operating characteristics and reliability. In addition, it is possible to ensure higher alignment accuracy than this type of conventional semiconductor device.

Claims (15)

In a semiconductor device having a TFT, Board; An island-type semiconductor film formed directly on the substrate or on the substrate via an underlying film, and functioning as an active layer of the TFT; A pair of source / drain regions of the TFT formed in the semiconductor film; And A channel region of the TFT formed between the pair of source / drain regions in the semiconductor film, The pair of source / drain regions are smaller in thickness than the rest of the semiconductor film; And a thickness difference between the pair of source / drain regions and the remaining portion of the semiconductor film is set in a range of 10 k? To 100 k ?. The semiconductor device of claim 1, further comprising alignment marks provided near the outside of the semiconductor film; And the alignment marks are made of the same material as the semiconductor film. The semiconductor device according to claim 2, wherein the alignment marks have the same thickness as the rest of the semiconductor film. The semiconductor device according to claim 1, further comprising: an additional island-type semiconductor film formed on the substrate directly or on a substrate via an underlying film, and functioning as an active layer of an additional TFT; A pair of additional source / drain regions of additional TFTs are formed in the additional semiconductor film; An additional channel region of an additional TFT is formed between the pair of additional source / drain regions of the additional semiconductor film; And And the pair of additional source / drain regions are equal in thickness to the rest of the additional semiconductor film. In the method of manufacturing a semiconductor device having a TFT, Forming an amorphous semiconductor film directly on the substrate or on the substrate via the underlying film; Forming a first mask on the amorphous semiconductor film, the first mask having a first pattern for source / drain regions and a second pattern for first alignment marks; Selectively implanting impurities into an amorphous semiconductor film using the first mask to form first impurity implantation regions by a first pattern and to form second impurity implantation regions by a second pattern; Selectively etching the surfaces of the first impurity injecting regions and the surfaces of the second impurity injecting regions using a first mask; First impurity injection regions and surface etched second impurity implant regions where the amorphous semiconductor film crystallizes to form a polycrystalline semiconductor film and the impurities implanted into the first impurity implantation regions and the second impurity implantation regions are activated. Irradiating a laser light to the amorphous semiconductor film including the; Forming a second mask on the polycrystalline semiconductor film, the second mask having a third pattern for a semiconductor island; And Selectively etching the polycrystalline semiconductor film using the second mask to form a semiconductor island by the third pattern; Irradiating a laser light to an amorphous semiconductor film, wherein a pair of source / drain regions are formed by first impurity implantation regions and first alignment marks are formed by second impurity implantation regions in the polycrystalline semiconductor film Become; And Selectively etching a polycrystalline semiconductor film, wherein the pair of source / drain regions are included in the semiconductor island, and first alignment marks are excluded from the semiconductor island. 6. The method of manufacturing a semiconductor device with a TFT according to claim 5, wherein in the step of selectively etching the polycrystalline semiconductor film using the second mask, the arrangement is performed using first alignment marks. The semiconductor device of claim 5, wherein the second mask has a fourth pattern for second alignment marks in addition to the third pattern for semiconductor islands; Selectively etching the polycrystalline semiconductor film using the second mask to form a semiconductor island, wherein the second alignment marks are formed near the semiconductor island by a fourth pattern. The semiconductor device of claim 6, wherein the second mask has a fourth pattern for second alignment marks in addition to a third pattern for semiconductor islands; Selectively etching the polycrystalline semiconductor film using the second mask to form a semiconductor island, wherein the second alignment marks are formed near the semiconductor island by a fourth pattern. 6. The method of claim 5, further comprising the step of implanting a threshold control impurity into the surface of the amorphous semiconductor film between the selective etching step using the first mask and the step of irradiating the laser light to the amorphous semiconductor film. A manufacturing method of a semiconductor device having a TFT. 6. The method of claim 5, further comprising injecting impurities for forming an LDD structure to the surface of the amorphous semiconductor film between the selective etching step using the first mask and the step of irradiating the laser light to the amorphous semiconductor film. A manufacturing method of a semiconductor device having a TFT characterized by the above-mentioned. In the manufacturing method of a semiconductor device having a TFT of a first conductivity type and a TFT of a second conductivity type, Forming an amorphous semiconductor film directly on the substrate or on the substrate via the underlying film; Forming a first mask on the amorphous semiconductor film, the first mask having a first pattern for source / drain regions of a first TFT having a first conductivity type and a second pattern for first alignment marks; Selectively implanting impurities of a first conductivity type into the amorphous semiconductor film using the first mask to form first impurity implantation regions by a first pattern and to form second impurity implantation regions by a second pattern Doing; Selectively etching the surfaces of the first impurity injecting regions and the surfaces of the second impurity injecting regions using a first mask; Forming a second mask on the amorphous semiconductor film, the second mask having a third pattern for source / drain regions of a second conductive TFT; Selectively implanting a second conductivity type impurity into an amorphous semiconductor film using the second mask to form third impurity implantation regions by a third pattern; First impurity injection regions, surface-etched, to crystallize the amorphous semiconductor film to form a polycrystalline semiconductor film and to activate impurities implanted into the first impurity injection regions, the second impurity injection regions and the third impurity injection regions, Irradiating a laser light to the amorphous semiconductor film including the etched second impurity implantation regions and the third impurity implantation regions; Forming a third mask on the polycrystalline semiconductor film, the third mask having a fourth pattern for semiconductor islands; And Selectively etching a polycrystalline semiconductor film using the third mask to form a first semiconductor island for a first TFT and a second semiconductor island for a second TFT by the fourth pattern; Irradiating a laser beam onto an amorphous semiconductor film, wherein a pair of source / drain regions of a first TFT are formed by first impurity implantation regions in the polycrystalline semiconductor film, and first alignment marks are formed by a second impurity implantation region And a pair of source / drain regions of the second TFT are formed by the third impurity injection regions; And Selectively etching the polycrystalline semiconductor film, wherein the pair of source / drain regions of the first TFT are included in the first semiconductor island, and the pair of source / drain regions of the second TFT are included in the second semiconductor island. And the first alignment marks are excluded from the first and second semiconductor islands. 12. The method of manufacturing a semiconductor device according to claim 11, wherein in the step of selectively etching the polycrystalline semiconductor film using the third mask, the arrangement is performed using the first alignment marks. The semiconductor device of claim 11, wherein the third mask includes a fifth pattern for second alignment marks in addition to a fourth pattern for semiconductor islands; Selectively etching the polycrystalline semiconductor film using the third mask to form the first and second semiconductor islands, wherein the second alignment marks are formed near the first and second semiconductor islands by a fifth pattern. A semiconductor device manufacturing method. The semiconductor device of claim 12, wherein the third mask has a fifth pattern for second alignment marks in addition to a fourth pattern for semiconductor islands; In the step of selectively etching the polycrystalline semiconductor film using the third mask to form the first and second semiconductor islands, the second alignment marks are formed near the first and second semiconductor islands by the fifth pattern. A semiconductor device manufacturing method. 12. The method of claim 11, wherein a threshold control impurity is implanted into a surface of an amorphous semiconductor film between the step of selectively injecting a second conductive impurity using the second mask and irradiating a laser light to the amorphous semiconductor film. The method of manufacturing a semiconductor device, further comprising the step.

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