KR100856062B1 - Semiconductor memory device and driving method thereof - Google Patents

Abstract

The present invention is to provide a semiconductor memory device that can control the delay locked loop circuit in the power-down mode in order to reduce the current consumed as much as possible. To this end, the present invention receives a system clock is delayed fixed through the delay lock operation A delay locked clock generation circuit for generating a clock; A mode signal generator for generating an active precharge power down mode signal activated in an active precharge power down mode; And a delay lock operation controller configured to control the delay lock clock generation circuit to activate the delay lock operation of the delay lock clock generation circuit at predetermined intervals in response to the active precharge power down mode signal. do.

Description

Semiconductor memory device and its driving method {SEMICONDUCTOR MEMORY DEVICE AND THE METHOD FOR OPERATING THE SAME}

1 is a block diagram of a semiconductor memory device.

FIG. 2 is a circuit diagram illustrating a buffer controller of the semiconductor memory device shown in FIG.

3 is a circuit diagram illustrating a clock buffer unit of the semiconductor memory device shown in FIG. 1;

4 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 5 is a circuit diagram of a buffer controller of the semiconductor memory device shown in FIG. 4; FIG.

FIG. 6 is a circuit diagram illustrating a clock buffer unit of the semiconductor memory device shown in FIG. 4; FIG.

FIG. 7 is a circuit diagram showing a delay lock operation control unit shown in FIG.

Fig. 8 is a block diagram of a semiconductor memory device for showing a second preferred embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: DLL control unit 200: clock buffer unit

300: buffer control unit 400A: first delay unit

400B: second delay unit 500: mode control unit

600: phase comparator 700: delay model

800: duty correction circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a delay locked loop (DLL) circuit of a semiconductor memory device.

In a system having a plurality of semiconductor devices operating various functions, the semiconductor memory device is a device for storing data. The semiconductor memory device outputs data corresponding to an address input from a data processing device, for example, a central processing unit, to a data requesting device, or transmits data transferred from the data processing device to a data input device in correspondence with the address inputted with the data. Store in the unit cell of the device.

As the operating speed of a system increases, the data input / output speed required of the semiconductor memory device in the data processing apparatus included in the system also increases. However, until recently, in the process of technology development of semiconductor integrated circuits, the operation speed of the data processing device is getting faster and faster. The data input / output speed of the semiconductor memory device that exchanges data with the data processing device does not depend on the speed of the data processing device. have.

Various types of semiconductor memory devices have been developed to increase the data input / output speed of the semiconductor memory device to a level required by the data processing device. Until recently, the most widely used semiconductor memory device has been proposed a synchronous memory device for outputting data every cycle of a system clock equipped with a data processing device. The synchronous memory device receives a system clock and outputs data to a data processing device in response to a cycle of the input system clock, or receives data from the data processing device every cycle of the system clock. However, even as a synchronous memory device does not match the operation speed of the data processing device, a DDR synchronous memory device has been developed. DDR synchronous memory devices output or receive data at every transition of the system clock. That is, data is input or output in synchronization with the rising and falling transitions of the system clock, respectively.

However, the system clock input to the memory device inevitably arrives at the data output circuit with a delay time by a clock input buffer disposed in the semiconductor memory device, a transmission line for transmitting a clock signal, and the like. Therefore, when the data output circuit outputs data in synchronization with the system clock that has already passed the delay time, the external device receiving the output data of the semiconductor memory device receives data that is not synchronized with the rising and falling edges of the system clock. You will be delivered.

In order to solve this problem, the semiconductor memory device includes a delay lock loop circuit which fixes a delay of a clock signal. The delay locked loop circuit is a circuit for correcting a value delayed by an internal circuit of the memory device until the system clock is input to the memory device and transferred to the data output circuit. The delay locked loop circuit finds a time at which the system clock is delayed by the clock input buffer and the clock signal transmission line of the semiconductor memory device, and delays the system clock in response to the found value to output the data to the data output circuit. That is, the system clock input to the memory device is transmitted to the data output circuit with the delay value fixed by the delay lock loop circuit. The data output circuit outputs data in synchronization with a delayed clock, and externally determines that data is output in synchronization with the system clock.

In the actual operation, at a determined point before the data should be output, the delay lock clock output from the delay lock loop circuit is transferred to the output buffer, and the data is output in synchronization with the delay lock clock. Therefore, the system clock outputs data faster than the delay of the internal circuit of the memory device. By doing so, it appears that data is output from the memory device in synchronization with the rising edge and the falling edge of the system clock input to the memory device. After all, a delay locked loop circuit is a circuit that finds out how much faster data must be output to correct the delay of the system clock inside the memory device.

As technology advances, an operation mode in which a semiconductor memory device can operate to maintain an optimal operation state according to an operation state of a system is also increasing. The power down mode is an operation mode for saving power when the semiconductor memory device does not access data. Recently, the power down mode of the semiconductor memory device has been developed into a precharge power down mode and an active power down mode. The active power multiple mode refers to a case of entering a power down mode while a word line for accessing data is activated, and the precharge power down mode refers to a case of entering a power down mode from a precharge state.

In general, the delay locked loop circuit outputs a delay locked clock in the active power down mode despite the power down mode, and stops output of the delay locked clock in the precharge power down mode. In precharge power-down mode, the delayed clock is not needed immediately after the power-down mode exits. In the active power-down mode, delay lock is performed immediately after exiting the power-down mode. This is because a clock is needed.

In the active power-down mode, it is impossible to unilaterally keep the delay lock loop circuit inactive. Therefore, although the active power-down mode is a power-down mode, a lot of current is consumed due to the delay locked loop circuit.

An object of the present invention is to provide a semiconductor memory device capable of appropriately controlling a delay locked loop circuit in accordance with an operation mode.

It is an object of the present invention to provide a semiconductor memory device capable of controlling a delay locked loop circuit in a power-down mode in order to minimize current consumption. In particular, an object of the present invention is to provide a semiconductor memory device capable of appropriately controlling the operation of a delay locked loop circuit in an active power down mode.

The present invention provides a delay locked clock generation circuit for receiving a system clock to generate a delay locked clock through a delay lock operation; A mode signal generator for generating an active precharge power down mode signal activated in an active precharge power down mode; And a delay lock operation controller configured to control the delay lock clock generation circuit to activate the delay lock operation of the delay lock clock generation circuit at predetermined intervals in response to the active precharge power down mode signal. do.

The present invention also provides a clock buffer unit for generating a reference clock by receiving a system clock; A clock buffer controller for activating the clock buffer unit at predetermined intervals in an active precharge power-down mode; And a delay lock loop circuit configured to receive the reference clock and generate a delay lock clock through a delay lock operation.

In addition, the present invention comprises the steps of generating a reference clock by receiving a system clock; Comparing phases of the reference clock and the feedback clock; Delaying and outputting the reference clock in response to the phase comparison result; Generating the feedback clock by delaying the delayed reference clock to a modeled delay value; And controlling generation of a feedback clock at predetermined intervals in an active power-down mode.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

1 is a block diagram of a semiconductor memory device. In particular, it is shown mainly in the delay locked loop circuit.

Referring to FIG. 1, the semiconductor memory device may include a control clock generator 5, a DLL controller 10, a clock buffer unit 20, a buffer controller 30, a first delay unit 40A, and a second delay unit. 40B, the mode controller 50, the phase comparator 60, the delay model 70, the duty cycle correction circuit 80, and the clock driver 90 are provided. The control clock generator 5 receives the enable signal DCC_ENb and the control clock CONTCLK to generate the update reference clock P2. The DLL control unit 10 receives the control signals DLL_REDELB and CIS_DLL and generates a reset signal RST. The clock buffer unit 20 receives the system clocks CLK and CLKB and buffers the first and second internal clocks CLKIN1 and CLKIN2 to generate the reference clock REFCLK and the control clock CONTCLK. The buffer controller 30 receives the internal clock enable signal CKEB_COM, the active idle signal RASIDLE, and the MRS setting signal SAPC, and enables the clock buffer unit 20 to enable the clock buffer unit 20. CLKBUF_ENB) is generated. The internal clock enable signal CKEB_COM is a signal that buffers the clock enable signal input to the semiconductor memory device. The active idle signal RASIDLE is a signal generated by decoding a command signal input from an external device by a command decoder (not shown) and is a signal for indicating an active state. The MRS setting signal SAPC is a signal provided corresponding to the information stored in the MRS register, and is a signal indicating which mode is operated in the fast precharge mode or the slow precharge mode.

The first delay unit 40A outputs a clock MIXOUT_R obtained by delaying the first internal clock CLKIN1 under the control of the mode controller 50. The second delay unit 40B outputs a clock MIXOUT_F in which the second internal clock CLKIN2 is delayed according to the control of the mode controller 50. In general, the delay delay loop circuit has a core delay unit having a unit delay unit as a chain, and a core delay unit and a phase comparator according to the result of the fine delay unit and the phase comparator for controlling the delay of the delay time that is finer than the delay time of the unit delay unit. A delay control unit for controlling the fine delay unit is provided. For convenience, the core delay unit, the fine delay unit, and the delay unit are represented by one circuit block like the first delay unit 40A and the second delay unit 40B. In addition, the first delay unit 40A and the second delay unit 40B modify the delay locked values of the clocks MIXOUT_R and MIXOUT_F that are delayed and locked in synchronization with the update reference clock P2.

The mode controller 50 receives the fast mode control signals FM_PDOUT_R and FM_PDOUT_F and the normal mode control signals CO_R, FI_R, CO_F and FI_F, and receives the fast mode locking signals ACT_MODE_END, ACT_MODE_ENDF and the normal locking signals LOCK_STATE and LOCK_STATEF. Create The fast mode locking signals ACT_MODE_END and ACT_MODE_ENDF are signals for controlling the start and end of the fast locking operation, and the normal locking signals LOCK_STATE and LOCK_STATEF are core delays provided in the first and second delay units 40A and 40B, respectively. This is a signal for controlling the unit and the fine delay unit. The normal locking signals LOCK_STATE and LOCK_STATEF are generated in response to the coarse control signals CO_R.CO_F and the fine control signals FI_R and FI_L, and the fast mode locking signals ACT_MODE_END respond to the fast mode control signals FM_PDOUTR. Is generated. The reset signal RST is a signal for the reset operation of the mode controller 50 and is a signal provided from the DLL controller 10.

The phase comparator 60 compares the phases of the reference clock REFCLK and the rising feedback clock FBCLKR with the phase differences of the reference clock REFCLK and the falling feedback clock FBCLKF, respectively, and generates corresponding result signals. The phase comparator 30 compares the phases of the reference clock REFCLK and the rising feedback clock FBCLKR to generate a fast locking signal FM_PDOUT when a fast locking operation is required, and a normal locking operation when a normal locking operation is required. Generate signals (COARSE, FINE). The fast locking operation changes the adjustment of the delay value relatively rapidly when the delay lock loop circuit performs the delay fixing operation, and the normal locking operation changes the adjustment of the delay value within a relatively small range. In other words, the phase comparator 60 outputs a coarse signal COARSE for controlling the delay operation of the coarse delay included in the delay units 40A and 40B, and a fine signal FINE for controlling the delay operation of the fine delay. It is. As described above, the coarse delay and the fine delay are provided in the first delay unit 40A and the second delay unit 40B, respectively. In addition, the phase comparator 30 compares the phases of the reference clock REFCLK and the falling feedback clock FBCLKF to generate a fast locking signal FM_PDOUTF when a fast locking operation is required, and when a normal locking operation is required. Generate a normal locking signal (COARSEF, FINEF).

The duty cycle correction circuit 80 corrects the duty ratios of the clocks MIXOUT_R and MIXOUT_F output from the first delay unit 40A and the second delay unit 40B and outputs them to the delay model 70. The delay model 80 delays the duty-corrected clocks IFBCLKR and IFBCLKF by a modeled value to generate a rising feedback clock and a polling feedback clock FBCLKR and FBCLKF. The modeled values model the delay time until the system clock is input to the semiconductor memory device and transferred to a circuit for outputting data. The output driver 90 generates and outputs the delay locked clocks IRCLKDLL and IFCLKDLL using duty-corrected clocks IFBCLKR and IFBCLKF. The circuit for outputting data outputs the data to the outside in response to the transition of the delay lock clocks IRCLKDLL and IFCLKDLL. When the semiconductor memory device outputs data to the outside in synchronization with the transition of the delay lock clocks IRCLKDLL and IFCLKDLL, the data appears to be output to the outside from the semiconductor memory device in synchronization with the transition of the system clock.

FIG. 2 is a circuit diagram illustrating a buffer controller of the semiconductor memory device shown in FIG. 1. As shown in FIG. 2, the buffer controller 30 receives the internal clock enable signal CKEB_COM, the active idle signal RASIDLE, and the MRS setting signal SAPC, and the NAND gate ND1. Inverter I1 outputs the clock buffer enable signal CLKBUF_ENB by inverting its output.

FIG. 3 is a circuit diagram illustrating a clock buffer unit of the semiconductor memory device shown in FIG. 1. As shown in FIG. 3, the clock buffer unit 20 is activated to the clock buffer enable signal CLKBUF_ENB to receive and buffer the system clocks CLK and CLKB so that the first and second internal clocks CLKIN1 and CLKIN2 are buffered. The buffer 21, the NAND gates ND2 and ND3, and the inverters I2 to I5 are provided to generate the over reference clock REFCLK and the control clock CONTCLK.

As described above, the semiconductor memory device enters a power down mode when data is not accessed, and there is an active power down mode and a precharge power down mode in the power down mode. The delay locked loop circuit shown in FIG. 1 performs a normal delay lock operation and outputs a delay locked clock despite the power down mode in the active power down mode. Therefore, in the active power down mode, even though the power down mode consumes a lot of current is a problem.

The present invention provides a semiconductor memory device capable of maximally reducing the amount of current consumed by a delay locked loop circuit in an active power-down mode.

4 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 4, in the semiconductor memory device according to the present exemplary embodiment, a control clock generator 50, a DLL controller 100, a clock buffer 200, a buffer controller 300, and a first delay may be used. A unit 400A, a second delay unit 400B, a mode control unit 500, a phase comparator 600, a delay model 700, a duty correction circuit 800, and a clock driver 900 are provided. The control clock generator 50, the DLL controller 100, the first delay unit 400A, the second delay unit 400B, the mode control unit 500, the phase comparator 600, the delay model 700, the duty The correction circuit 800 and the clock driver 900 perform substantially the same operations as the blocks of the same name shown in the semiconductor memory device shown in FIG.

The buffer controller 300 activates an active idle signal RASIDLE activated in response to an active mode, an internal clock enable signal CKEB_COM, and an MRS register for detecting whether the fast precharge power down mode or the slow precharge power down mode is used. The MRS setting signal SAPC having the information of the input signal is input to generate an active power down mode signal ACT_PD and a clock buffer enable signal CLKBUF_ENB. The clock buffer unit 200 receives the system clocks CLK and CLKB and generates the internal clocks CLKIN1 and CLKIN2, the reference clock REFCLK, the control clock CONTCLK, and an update signal. In particular, the clock buffer unit 200 is activated in response to the clock buffer enable signal CLKBUF_ENB to generate the internal clocks CLKIN1 and CLKIN2, the reference clock REFCLK, and the control clock CONTCLK. When the ACT_PD is activated, the reference clock REFCLK and the control clock CONTCLK are generated at predetermined predetermined periods. That is, the clock buffer unit 200 generates the reference clock REFCLK and the control clock CONTCLK at regular intervals while the mode signal ACT_PD is activated and input. The update signal UPDATA_EN is a signal for periodically enabling the update in the power down mode, and here, controls the activation of the delay model 700.

Therefore, the semiconductor memory device according to the present embodiment does not always perform the delay lock operation in the active power down mode. The delay lock operation is performed every predetermined period. Previously, even if the semiconductor memory device enters the active power-down mode while accessing data using the delayed clock, the same delay lock operation is performed as during the data access. This wastes a lot of unnecessary current. However, the semiconductor memory device according to the present invention does not continuously perform the delay lock operation after entering the active power-down mode, but may reduce the current consumed since it is performed at predetermined periods.

Before entering the active power down mode, the delay locked loop circuit typically outputs a delay locked clock, so in the active power down mode, fine tuning of the delay locked clock is mainly performed. When the active power down mode is released, the delay locked loop circuit can directly output the delayed clock and the semiconductor memory device can output data using the delayed clock so that the active power down mode can be exited. The access time of time data can be effectively reduced.

Of course, as described above, the clock driver 900 outputs delayed fixed clocks IRCLKDLL and IFCLKDLL even in the active power-down mode. Therefore, a circuit in the path through which the clock is transmitted in the power-down mode, for example, the first delay unit 400A, the second delay unit 400B, the duty cycle correction circuit 800, and the clock driver 900 may perform an operation. However, the delay model 700 and the circuit for delay lock operation, such as the phase comparator 600, operate every predetermined period. Therefore, in the active power-down mode, the delay locked clock is output, but the delay lock operation is performed periodically. Specifically, in the present embodiment, the delay lock operation is periodically performed by controlling the clock buffer unit and the delay model in the active power down mode.

On the other hand, the period of the delay lock operation in the active power-down mode can be appropriately determined according to the operating conditions of the semiconductor memory device, in the present embodiment is to operate for about 16 cycles of the system clock every 1024 clock of the system clock It was.

FIG. 5 is a circuit diagram illustrating a buffer control unit of the semiconductor memory device shown in FIG. 4.

Referring to FIG. 5, the buffer controller 300 includes a clock buffer enable signal generator 310 and a mode signal generator 320. The clock buffer enable signal generator 310 may include the NAND gate ND4 and the NAND gate ND4 that receive the active idle signal RASIDLE, the internal clock enable signal CKEB_COM, and the MRS setting signal SAPC. An inverter I6 for inverting the output and outputting the clock buffer enable signal CLKBUF_ENB is provided.

The mode signal generator 320 may include an inverter I7 for inverting and outputting an active idle signal RASIDLE, a NAND gate ND5 for receiving an output of an internal clock enable signal CKEB_COM and an inverter I7, and And an inverter I8 for inverting the output of the NAND gate ND5 to output the active power-down mode signal ACT_PD.

FIG. 6 is a circuit diagram illustrating a clock buffer unit of the semiconductor memory device shown in FIG. 4.

Referring to FIG. 6, the clock buffer unit 200 receives and updates a buffer 210 that outputs an internal clock ICLK by buffering the system clocks CLK and CLKB, and receives an active power down mode signal ACT_PD. Delay-fixed operation control unit 220 for generating a signal (UPDATA_EN), and a clock transfer unit for transmitting the internal clock (CLKIN1, CLKIN2, REFCLK, CONTCLK) in response to the clock buffer enable signal (CLKBUF_ENB) and the update signal (UPDATA_EN) 230.

FIG. 7 is a circuit diagram illustrating a delay lock operation control unit shown in FIG. 6. The delay lock operation controller 220 refers to a cycle signal generator 221 for generating a clock signal of various cycles using an internal clock ICLK and a clock signal 1024K output from the cycle signal generator 221. The update signal generator 222 generates an update signal UPDATA_EN in response to the clock signal 16K. In particular, the periodic signal generator 221 is activated in response to the active power-down mode signal ACT_PD, the first flip-flop receives the internal clock ICLK, and a plurality of serially connected T-s receiving the output clock of the preceding stage. A flip flop is provided.

Fig. 8 is a block diagram of a semiconductor memory device for showing a second preferred embodiment of the present invention.

Referring to FIG. 8, a semiconductor memory device according to an exemplary embodiment of the present invention may include a delay locked loop circuit 1000 including a clock buffer unit 1100, a delay locked operation control unit 2000, and a mode signal generator. And a clock buffer enable signal 4000. The clock buffer unit 1100 performs the same function as the clock buffer unit 200 of FIG. 4, and the circuit 1200 for delay lock operation includes all remaining circuits except the clock buffer unit 200 shown in FIG. 4. It is a circuit that includes. The delay lock operation controller 2000 performs the same function as the delay lock operation controller 220 of FIG. 6, and the mode signal generator 3000 performs the same function as the mode signal generator 320 of FIG. 5. The clock buffer enable unit 4000 performs the same function as the clock buffer enable signal generator 310.

Since each block shown in FIG. 8 performs the same operation as the blocks of the same name described above, a detailed description of the operation is omitted. Like the semiconductor memory device shown in Fig. 4, the semiconductor memory device shown in Fig. 8 performs a delay lock operation at predetermined intervals in the active power-down mode, and thus consumes more energy than the case where the delay lock operation is always performed in the power-down mode. Current can be reduced.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The semiconductor memory device according to the present embodiment can reduce the amount of current consumed in the power down mode. Therefore, when the semiconductor memory device according to the present invention is applied to a low power system or a mobile system, current consumption can be greatly reduced.

Claims (13)

A delay locked clock generation circuit configured to receive a system clock and generate a delay locked clock through a delay lock operation; A mode signal generator for generating an active precharge power down mode signal activated in an active precharge power down mode; And A delay lock operation controller for controlling the delay lock clock generation circuit to activate the delay lock operation of the delay lock clock generation circuit at predetermined intervals in response to the active precharge power down mode signal; A semiconductor memory device having a. The method of claim 1, The delay lock operation control unit And dividing the system clock to control the delay locked clock generation circuit. The method of claim 1, The delay locked clock generation circuit A clock buffer unit which receives the system clock and outputs a reference clock; And And a delay lock loop circuit configured to receive the reference clock and perform a delay lock operation to generate a delay locked clock, wherein an operation control signal output from the delay lock operation controller controls the clock buffer unit. Device. The method of claim 3, wherein The mode signal generation unit And generating an active power down mode signal by receiving an active signal activated in response to an active mode and a clock enable signal. The method of claim 4, wherein The delay lock operation control unit A plurality of flip-flops connected in series and activated in response to the mode signal, the first flip-flop receiving the system clock and the output clock of the preceding stage; And And a control signal output unit configured to output an output of a second flip flop selected from the plurality of flip flops as a control signal for controlling the clock buffer unit in response to an output clock of the first flip flop selected from the plurality of flip flops. A semiconductor memory device characterized by the above-mentioned. The method of claim 1, The delay locked clock generation circuit A clock buffer which receives the system clock and generates a reference clock; A phase comparator for comparing phases of the reference clock and the feedback clock; A delay unit for delaying and outputting the reference clock in response to a comparison result of the phase comparator; And A delay model for delaying a clock output from the delay unit to a modeled delay value and outputting the delayed clock to the feedback clock; And the delay model is activated every predetermined period under the control of a delay lock operation controller. A clock buffer unit for receiving a system clock and generating a reference clock; A clock buffer controller for activating the clock buffer unit at predetermined intervals in an active precharge power-down mode; And A delay lock loop circuit for generating a delay lock clock through the delay lock operation by receiving the reference clock. A semiconductor memory device having a. The method of claim 7, wherein The clock buffer control unit, A mode signal generator for generating an active precharge power down mode signal activated in an active precharge power down mode; And And a delay lock operation controller configured to generate an update signal to perform a delay lock operation of the delay lock loop circuit at predetermined intervals in response to the active precharge power down mode signal. The method of claim 8, The delay lock operation control unit, And dividing the system clock to generate the update signal. The method of claim 9, The mode signal generation unit And generating the mode signal by receiving an active signal activated in response to an active mode and a clock enable signal. The method of claim 10, The delay lock operation control unit A plurality of flip-flops connected in series and activated in response to the active power-down mode signal, the first flip-flop receiving the system clock and the output clock of the preceding stage being input; And And a control signal output unit configured to output an output of a second flip flop selected from the plurality of flip flops as a control signal for controlling the clock buffer unit in response to an output clock of the first flip flop selected from the plurality of flip flops. A semiconductor memory device characterized by the above-mentioned. Receiving a system clock to generate a reference clock; Comparing phases of the reference clock and the feedback clock; Delaying and outputting the reference clock in response to the phase comparison result; Generating the feedback clock by delaying the delayed reference clock to a modeled delay value; And Controlling generation of the feedback clock at predetermined intervals in the active power-down mode Method of driving a semiconductor memory device comprising a. The method of claim 12, Controlling the generation of the feedback clock Generating a mode signal by receiving an active signal activated in response to the active mode and a clock enable signal; And Controlling the generation of the feedback clock in response to the mode signal.

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