KR100850096B1 - Method for manufacturing mos transistor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOS transistor. In particular, a gate insulating film, a gate electrode, and a blocking film are sequentially formed on a semiconductor substrate, and an insulating thin film is formed on the sidewalls of the gate electrode and the substrate surface, and then the blocking film is removed and the gate An LDD region is formed in the substrate near the electrode edge, an insulating film is formed on the entire surface of the substrate, the insulating film and the insulating thin film are etched to form an insulating thin film pattern and a spacer wall on the gate electrode sidewall, and a source / After the drain region is formed, a silicide film is formed on the top surface of the gate electrode or the source / drain regions, respectively. Therefore, the present invention prevents the insulating thin film for the LDD from being formed on the gate electrode by the blocking film, thereby preventing the reduction of the silicide film area on the gate electrode.

Silicide film, LDD, blocking film, thermal oxidation

Description

Method of manufacturing MOS transistors {METHOD FOR MANUFACTURING MOS TRANSISTOR}

1A to 1G are process flowcharts sequentially illustrating a manufacturing process of a MOS transistor according to the prior art;

2A to 2G are process flowcharts sequentially illustrating a manufacturing process of a MOS transistor according to the present invention;

3A and 3B are vertical cross-sectional views of MOS transistors fabricated in accordance with the prior art and the invention, respectively.

<Description of the code | symbol about the principal part of drawing>

100 silicon substrate 102 field region

104: gate insulating film 106: gate electrode

108: blocking film 110: insulating thin film

112: LDD region 114a: spacer wall

116 source / drain region 118 silicide layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a MOS transistor capable of improving the yield of a semiconductor device by preventing reduction of a silicide area located on an upper surface of a gate electrode.

At present, as the degree of integration of semiconductor devices increases, the width of the wiring decreases, thereby increasing the sheet resistance of the wiring. As the sheet resistance of the wiring increases, the signal transmission time of the device in the integrated circuit is delayed.

In order to prevent this, the sheet resistance and contact resistance of the wiring were lowered by adding a high melting silicide material having a low specific resistance and stable at high temperature as well as a source / drain junction as well as the gate electrode of the transistor. Such silicide materials mainly utilize rare earth metals that react with silicon. Examples of the silicide include tungsten silicide (WSi ₂ ), titanium silicide (TiSi ₂ ), cobalt silicide (CoSi ₂ ), and the like.

1A to 1G are process flowcharts sequentially illustrating a manufacturing process of a MOS transistor according to the prior art.

Referring to these drawings, a manufacturing process of a MOS transistor including a conventional silicide proceeds as follows.

First, as shown in FIG. 1A, as the semiconductor substrate 10, a trench is formed by etching a field region 12, for example, a silicon substrate 10, which defines an active region in a silicon substrate to a predetermined depth, and forming a trench. The insulating material filling the gap is buried and the insulating material is polished by a chemical mechanical polishing (CMP) process to form a field region 12 in the form of a shallow trench isolation (STI). The insulating film and the gate conductive film are sequentially stacked on the silicon substrate 10 having the field region 12 formed thereon, and then patterned to form the gate electrode 16 having the gate insulating film 14 interposed therebetween. The gate conductive layer may be formed of polysilicon, silicon germanium (SiGe), cobalt (Co), tungsten (W), titanium (Ti), nickel (Ni), tantalum (Ta), titanium nitride (TiN), or tantalum doped with impurities. It may be composed of any one of a nitride film TaN and a tungsten nitride film WN.

Then, as shown in Figure 1b, in order to serve as a sacrificial film during the low concentration ion implantation process, a thin insulating film 18 is formed on the entire surface of the substrate. For example, an insulating thin film 18 made of silicon oxide (SiO ₂ ) is formed on the top and side surfaces of the gate electrode 16 and the substrate surface by a thermal oxidation process.

Subsequently, as shown in FIG. 1C, a lightly doped drain (LDD) region 20 is formed by performing a low concentration ion implantation process (for example, by implanting an N-type dopant at low concentration) using the gate electrode 16 as an ion implantation mask. ).

Subsequently, as shown in FIGS. 1D and 1E, an insulating material 22, for example, a silicon nitride film (SiN) or a silicon oxynitride film (SiON) is deposited on the entire surface of the silicon substrate 10. The spacer material 22a and 18 may be formed on the sidewalls of the gate electrode 16 by dry etching the insulating material 22 and the insulating thin film 18. That is, the insulating material 22 and the insulating thin film 18 are removed from the upper surface of the gate electrode 16 and the surface of the substrate 10.

Then, as shown in FIG. 1F, a high concentration ion implantation process (for example, high concentration ion implantation with an N-type dopant) is performed using the spacer walls 22a and 18 and the gate electrode 16 as an ion implantation mask. The source / drain regions 24 are formed. Here, the source / drain region 24 has an LDD structure including a low concentration LDD region 20 on the substrate surface.

Then, as illustrated in FIG. 1G, a silicide metal material is deposited on the entire surface of the substrate, and a heat treatment process is performed to form the silicide layer 26 on the gate electrode 16 and the top surface of the source / drain region 24, respectively. . Here, the silicide material may be, for example, rare earth metals such as cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), Pt (platinum), Hf (hafnium), Pd (palladium) or the like. It is made of any one metal in the alloy. The silicide film 26 may be, for example, tungsten silicide (WSi ₂ ), titanium silicide (TiSi ₂ ), cobalt silicide (CoSi), or the like.

Thereafter, silicide material that is not silicided is removed by a process such as washing.

In the MOS transistor manufacturing process having the silicide film according to the related art as described above, after the gate electrode 16 and the gate insulating film 14 are patterned, the insulating thin film 18 is thinly formed on the entire surface of the substrate structure by a thermal oxidation process or the like. Doing. The silicon oxide film 18 manufactured by the thermal oxidation process serves to compensate for damage to the edge of the gate insulating layer 14 while protecting the surface of the substrate during the low concentration ion implantation process for LDD.

However, the silicon oxide film 18 produced by the thermal oxidation process is formed on the sidewalls and the entire upper portion of the gate electrode 16, wherein the oxidation reaction is performed on the upper surface of the gate electrode 16 rather than the sidewall of the gate electrode 16. Because of this further occurrence, the formation of the silicon oxide film 18 is formed thicker than the sidewalls near the upper edge of the gate electrode 16.

As such, the silicon oxide film 18 thickly formed on the upper edge of the gate electrode 16 may reduce the open area of the upper surface of the gate electrode 16 during the silicide process, and thus the silicide formed on the upper surface of the gate electrode 16. The area of the film 26 is also reduced. Therefore, the sheet resistance and the contact resistance of the contact connected to the silicide on the upper surface of the gate electrode are increased, thereby acting as a cause of delaying signal transmission of the MOS transistor.

An object of the present invention is to solve the problems of the prior art as described above, after forming a blocking film on the upper surface of the gate electrode and an insulating thin film for LDD ion implantation on the gate electrode sidewall and the entire surface of the substrate after the low concentration ion implantation process The present invention provides a method of manufacturing a MOS transistor that can prevent the cause of the reduction of the open area of the upper surface of the gate electrode, thereby reducing the reduction of the silicide film area of the upper portion of the gate electrode.

In order to achieve the above object, the present invention, in the manufacturing method of the MOS transistor having a silicide film, the step of sequentially forming a gate insulating film, a gate electrode and a blocking film on the semiconductor substrate, and an insulating thin film on the gate electrode sidewall and the substrate surface Forming, removing the blocking film, forming an LDD region in the substrate near the edge of the gate electrode, forming an insulating film on the entire surface of the substrate, and etching the insulating film and the insulating thin film to form an insulating thin film pattern on the sidewall of the gate electrode. And forming a spacer wall, forming a source / drain region in the substrate near the spacer wall edge, and forming a silicide film on the gate electrode top surface or the source / drain region, respectively.

According to another aspect of the present invention, a method of manufacturing a MOS transistor having a silicide film includes sequentially forming a gate insulating film, a gate electrode, and a blocking film on a semiconductor substrate, and forming a gate electrode sidewall and a substrate surface. Forming an insulating thin film, forming an LDD region in the substrate near the gate electrode edge, removing the blocking film, forming an insulating film over the entire surface of the substrate, and etching the insulating film and the insulating thin film to insulate the gate electrode sidewalls. Forming a thin film pattern and a spacer wall; forming a source / drain region in the substrate near the spacer wall edge; and forming a silicide film on the gate electrode top surface or the source / drain region, respectively.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

2A to 2G are process flowcharts sequentially illustrating a manufacturing process of a MOS transistor according to the present invention.

Referring to these drawings, a manufacturing process of a MOS transistor including a silicide according to an embodiment of the present invention proceeds as follows.

First, as shown in FIG. 2A, a trench is formed by etching a field region 102, for example, a silicon substrate 100, which defines an active region on a silicon substrate as a semiconductor substrate 100 to a predetermined depth, and forming a trench. Filling the insulating material filling the gap and polishing the insulating material by a chemical mechanical polishing (CMP) process to form the field region 102 of the STI.

An insulating film, for example, a silicon oxide film (SiO ₂ ) and a gate conductive film, are sequentially stacked on the silicon substrate 100 having the field region 102 formed thereon, and then a blocking film 108 such as a silicon nitride film (SiN) is laminated thereon. do. The gate conductive layer may be formed of polysilicon, silicon germanium (SiGe), cobalt (Co), tungsten (W), titanium (Ti), nickel (Ni), tantalum (Ta), titanium nitride (TiN), or tantalum doped with impurities. It may be composed of any one of a nitride film TaN and a tungsten nitride film WN.

After the photolithography and the dry etching process using the gate mask are performed, the blocking film 108 is patterned, the gate conductive film below is patterned to form the gate electrode 106, and then the insulating film is patterned to form the gate insulating film 104. do. In this case, the blocking film 108 serves to prevent the insulating film from being formed on the upper surface of the gate electrode during the insulating film (for example, thermally oxidized silicon oxide) process on the front surface of the substrate, which is performed before the low concentration ion implantation process for the LDD. . Here, the blocking film 108 is formed to a thickness of 50 kV to 500 kV.

As shown in FIG. 2B, the insulating thin film 110 is thinly formed on the entire surface of the substrate to serve as a sacrificial film during the low concentration ion implantation process. For example, an insulating thin film 110 made of silicon oxide (SiO ₂ ) is formed on the side of the gate electrode 106 and the surface of the substrate 100 by a thermal oxidation process.

Thereafter, a wet etching or cleaning process is performed to remove the blocking layer 108 located on the upper surface of the gate electrode 106.

Next, as shown in FIG. 2C, the LDD region 112 is formed by performing a low concentration ion implantation process (eg, implanting an N-type dopant at a low concentration) using the gate electrode 106 as an ion implantation mask.

Subsequently, as shown in FIGS. 2D and 2E, an insulating material 114, for example, a silicon nitride film (SiN) or a silicon oxynitride film (SiON) is deposited on the entire surface of the substrate 100. The spacer material 114a and 110 are formed on the sidewalls of the gate electrode 106 by dry etching the insulating material 114 and the insulating thin film 110. That is, the insulating material 114 and the insulating thin film 110 are removed from the upper surface of the gate electrode 106 and the surface of the substrate 100.

Next, as shown in FIG. 2F, a high concentration ion implantation process (for example, high concentration ion implantation using an N-type dopant) is performed using the spacer walls 114a and 110 and the gate electrode 106 as an ion implantation mask. Source / drain regions 116 are formed. Here, the source / drain region 116 has an LDD structure including a low concentration LDD region 112 on the substrate surface.

Then, as shown in FIG. 2G, a silicide metal material is deposited on the entire surface of the substrate and subjected to a heat treatment to form a silicide layer 118 on the gate electrode 106 and the top surface of the source / drain region 116, respectively. . Here, the silicide material may be, for example, rare earth metals such as cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), Pt (platinum), Hf (hafnium), Pd (palladium) or the like. It is made of any one metal in the alloy. The silicide film 118 is, for example, tungsten silicide (WSi ₂ ), titanium silicide (TiSi ₂ ), cobalt silicide (CoSi), or the like.

Thereafter, silicide material that is not silicided is removed by a process such as washing.

As described above, in the MOS transistor manufacturing process having the silicide film according to the present invention, the blocking film 108 is formed on the upper surface of the gate electrode 106, and the gate electrode 106 sidewall and the entire surface of the substrate 100 are formed by a thermal oxidation process or the like. The insulating thin film 110 is formed thin. The silicon oxide film 110 manufactured by the thermal oxidation process serves to compensate for the damage of the edge of the gate insulating film 104 while protecting the surface of the substrate during the low concentration ion implantation process for the LDD, but the upper surface of the gate electrode 106. Except for the gate electrode 106 is formed only on the sidewall and the substrate 100 surface.

Since the silicon oxide film 110 on the gate electrode 106 is removed before or after the low concentration ion implantation process, the upper surface of the gate electrode 106 may be formed on the silicon oxide film ( It is possible to secure an area of the silicide film 118 having a desired size without being lost by the thermal oxidation process of 110.

On the other hand, in the embodiment of the present invention, the blocking film 108 on the upper surface of the gate electrode 106 is removed before the low concentration ion implantation process is performed, but after the low concentration ion implantation process is performed, the upper portion of the gate electrode 106 is performed. The blocking film 108 on the surface may be removed.

3A and 3B are vertical cross-sectional views of MOS transistors manufactured according to the prior art and the present invention, respectively.

As shown in FIG. 3A, in the MOS transistor manufacturing method having a silicide film according to the related art, a silicon oxide film 18 manufactured by a thermal oxidation process is formed on a top surface, a sidewall, and a substrate 10 surface of a gate electrode 16. Because it is formed in the upper side of the gate electrode 16, the oxidation reaction occurs more than the side wall. As shown by reference numeral A, the silicon oxide film 18 thickly formed on the upper edge of the gate electrode 16 reduces the open area of the upper surface of the gate electrode 16 during a silicide process, thereby increasing the upper portion of the gate electrode 16. The area of the silicide film 26 formed on the surface is reduced.

On the other hand, as shown in Figure 3b, in the MOS transistor manufacturing method having a silicide film according to the present invention, the silicon oxide film 110 manufactured by a thermal oxidation process using a blocking film to the upper surface of the gate electrode 106 Since the gate electrode 106 is formed on the sidewall of the gate electrode 106 and the surface of the substrate 100, the upper surface of the gate electrode 106 is protected from oxidation. As shown by reference numeral B, the silicon oxide film 110 formed only on the sidewall of the gate electrode 106 is maintained while the upper surface of the gate electrode 106 remains intact, and then the upper surface of the gate electrode 106 is left open during the silicide process. As a result, the area of the silicide film 118 formed on the upper surface of the gate electrode 106 is increased.

As described above, the present invention provides a insulating film for LDD ion implantation by forming a blocking film on the top surface of the gate electrode and forming an insulating thin film for LDD ion implantation on the gate electrode sidewall and the entire surface of the substrate. Due to the reduction of the open area of the upper surface of the gate electrode can be prevented.

Therefore, the present invention can reduce the reduction of the silicide film area on the top of the gate electrode, thereby lowering the sheet resistance and contact resistance of the contact connected to the silicide on the top surface of the gate electrode, thereby speeding up the signal transfer of the MOS transistor.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (6)

In the manufacturing method of the MOS transistor which has a silicide film, Sequentially forming a gate insulating film, a gate electrode, and a blocking film on the semiconductor substrate; Forming an insulating thin film on a side of the gate electrode and on the semiconductor substrate; Removing the blocking film; Forming an LDD region in an area near an edge of the gate electrode; Forming an insulating film on the entire surface of the semiconductor substrate, and etching the insulating film and the insulating thin film to form an insulating thin film pattern and a spacer wall on sidewalls of the gate electrode; Forming a source / drain region in an area near an edge of the spacer wall; Forming a silicide layer on an upper surface of the gate electrode or the source / drain regions, respectively Method of manufacturing a MOS transistor comprising a. The method of claim 1, The blocking film is 50 mW to 500 mW. The method of claim 1, The blocking film is a method of manufacturing a MOS transistor, characterized in that the insulating thin film and the silicon nitride film having an etching selectivity. delete The method of claim 1, The insulating thin film is a method of manufacturing a MOS transistor, characterized in that the silicon oxide film formed by a thermal oxidation process. In the manufacturing method of the MOS transistor which has a silicide film, Sequentially forming a gate insulating film, a gate electrode, and a blocking film on the semiconductor substrate; Forming an insulating thin film on a side of the gate electrode and on the semiconductor substrate; Forming an LDD region in an area near an edge of the gate electrode; Removing the blocking film; Forming an insulating film on the entire surface of the semiconductor substrate, and etching the insulating film and the insulating thin film to form an insulating thin film pattern and a spacer wall on sidewalls of the gate electrode; Forming a source / drain region in an area near an edge of the spacer wall; Forming a silicide layer on an upper surface of the gate electrode or the source / drain regions, respectively Method of manufacturing a MOS transistor comprising a.

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