KR100850379B1 - Method for fabricating high aperture ratio lcd device - Google Patents

Abstract

The present invention discloses a method of manufacturing a high-aperture liquid crystal display device, and the disclosed method includes a step of applying a resin film having a low dielectric constant thickly on a transparent insulating substrate having a pixel portion and a pad portion, and locally etching the resin film. Forming first and second via holes exposing the thin film transistor portion in the pixel portion and the pads in the pad portion, depositing ITO on the resin film, and patterning the ITO to form the first via hole. A method of manufacturing a high aperture liquid crystal display device, the method comprising: forming an ITO pattern contacting a pad through a pixel electrode contacting a thin film transistor and a second via hole through a process of forming the first and second via holes. When the substrate is tested by half-toning the area between adjacent second via hole forming regions while fully exposing the second via hole forming region. The resin film of the pad portion in which the second via hole is formed to have a thickness such that the resin film is not recessed due to the pressurization of the groove pin is formed to have a lower level than the resin film of the pixel portion in which the first via hole is formed. The half-tone exposure is performed by using an exposure mask having an opening pattern in a mask region corresponding to each pad, and a slit pattern of a relatively fine width in a mask region corresponding to an area between adjacent pads.

Description

Manufacturing method of high-aperture liquid crystal display device {METHOD FOR FABRICATING HIGH APERTURE RATIO LCD DEVICE}

1 is a cross-sectional view showing an array substrate of a conventional top ITO structure.

FIG. 2 is a cross-sectional view illustrating an array substrate of a conventional high aperture liquid crystal display device. FIG.

FIG. 3 is a cross-sectional view illustrating an array substrate of a high aperture liquid crystal display device manufactured according to an exemplary embodiment of the present invention. FIG.

4 and 5 are a schematic view of the pad portion of the exposure mask used in the via hole formation according to the prior art and the present invention, and a cross-sectional view of the pad portion in the array substrate formed through the same.

Explanation of symbols on the main parts of the drawings

1 glass substrate 2 gate electrode

3: gate insulating film 4: channel layer

5: ohmic contact layer 6: source / drain electrode

7: protective film 8,8a: pixel electrode

9,9a, 9b: ITO pattern 10: resin film

21: opening pattern 22: slit pattern

The present invention relates to a method for manufacturing a high-aperture liquid crystal display device, and more particularly, to a method for preventing contact failure between a pad and a probe pin due to depression of a thick resin film in a pad portion during a test.

Liquid crystal displays have been developed in place of the CRT (Cathod-ray tube). In particular, a thin film transistor liquid crystal display device having a thin film transistor as a switching element for each pixel realizes high quality, large size, and color screen comparable to a CRT.

Such a thin film transistor liquid crystal display device has a structure in which an array substrate including a thin film transistor and a pixel electrode, and a color filter substrate including a color filter and a counter electrode are bonded to each other under a liquid crystal layer.

On the other hand, in manufacturing such a thin film transistor liquid crystal display device, it is very important to reduce the number of manufacturing steps, in particular, the number of manufacturing steps of the array substrate. This is because, as the number of manufacturing processes is reduced, the manufacturing cost and time of the thin film transistor liquid crystal display device can be reduced, so that a larger amount of thin film transistor liquid crystal display device can be supplied at a lower cost.

Here, the reduction in the number of manufacturing processes is realized by the reduction in the number of masks, and conventional array substrates have been mass-produced through a 7-mask process, but recently mass-produced through a 5-mask process using BCE (Back Channel Etch) technology. In addition, it is also manufactured by a 3-mask or 4-mask process using half-tone exposure.                         

In the 5-mask process to which the BCE technique is applied, the ITO pixel electrode is disposed on the top of the array substrate, and the schematic structure of the array substrate having the top ITO structure is shown in FIG. 1.

Referring to FIG. 1, a gate electrode 2, a gate insulating film 3, a channel layer 4 made of a-Si, an etch stopper made of n + a-Si, and a glass electrode 1, which are transparent insulating substrates, are placed in place. (5) and a thin film transistor (TFT) including a source / drain electrode (6) are formed, and a protective film (7) made of PVX is formed on the entire surface of the substrate (1) including the thin film transistor (TFT). A pixel electrode 8 made of ITO contacting the thin film transistor TFT is formed on the passivation layer corresponding to the pixel portion, and the pad 2a is contacted through the via hole on the passivation layer corresponding to the pad portion. The ITO pattern 9 is formed.

On the other hand, in such a thin film transistor liquid crystal display device, in order to obtain high image quality, the improvement of the aperture ratio, which is the actual light transmission ratio with respect to the area of the pixel electrode, is a priority, and for this purpose, the area of the pixel electrode must be increased. However, if only the area of the pixel electrode is increased, the parasitic capacitance is increased, which may result in deterioration of image quality.

Therefore, as an effort to obtain a high opening ratio, a resin film having a low dielectric constant is formed thick on a protective film made of PVX, thereby reducing parasitic capacitance by increasing the dielectric constant of the resin film itself and increasing the gap between the pixel electrode and the lower metal layer. A new array substrate structure has been proposed to reduce and additionally obtain a planarization effect by the resin film coating, the schematic array substrate structure of which is shown in FIG.                         

Referring to FIG. 2, an array substrate structure capable of obtaining a high opening ratio is similar to that of FIG. 1, except that the resin film 10 is thickly coated on the protective film 7 made of PVX, and made of ITO. 8a and ITO pattern 9a are in contact with the thin film transistor TFT and the pad 2a through via holes formed by etching the resin film 10, the protective film 7, and the gate insulating film 3.

However, the high-permeability liquid crystal display device as described above is related to the resin film applied to reduce the parasitic capacitance thickly applied to the pad portion, so that the thick resin can be pressed by pressing the probe pin during the subsequent test of the array substrate. A phenomenon in which the film may be recessed may occur, thereby causing a poor contact between the pad and the probe pin, thereby preventing test reliability.

Accordingly, the present invention has been made to solve the above problems, and the manufacturing method of the high-aperture ratio liquid crystal display device which can prevent the contact failure between the pad and the probe pin caused by the depression of the thick resin film of the pad portion. The purpose is to provide.

In order to achieve the above object, the present invention provides a method of manufacturing a high-aperture rate liquid crystal display device, comprising: applying a resin film having a low dielectric constant thickly on a transparent insulating substrate having a pixel portion and a pad portion, and locally etching the resin film. Forming first and second via holes exposing the thin film transistor portion in the pixel portion and pads in the pad portion, depositing ITO on the resin film, and patterning the ITO to form a first via hole. The method of manufacturing a high aperture liquid crystal display device comprising forming a pixel electrode contacting a thin film transistor and an ITO pattern contacting a pad through a second via hole through the forming of the first and second via holes. During the test of the substrate by half-tone exposure of the region between adjacent second via hole forming regions while fully exposing the second via hole forming region. The resin film of the pad portion having the second via hole is formed to have a lower level than the resin film of the pixel portion having the first via hole.

The half-tone exposure is performed by using an exposure mask having an opening pattern in a mask area corresponding to each pad, and having a slit pattern of a relatively fine width in a mask area corresponding to an area between adjacent pads.

According to the present invention, by lowering the thickness of the resin film between the pads, the ITO pattern can be formed without a large step, thereby preventing the occurrence of contact failure during the array test, and consequently, the test reliability. Can improve.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view illustrating an array substrate of a high-aperture liquid crystal display device manufactured according to an exemplary embodiment of the present invention. 1 and 2 are denoted by the same reference numerals.

First, the gate electrode 2, the gate insulating film 3, the channel layer 4 of a-Si, n + a according to a well-known process of the glass substrate 1, that is, the thin film transistor part, which is a transparent insulating substrate. A thin film transistor (TFT) in which the etch stopper 5 of Si and the source / drain electrodes 6 are stacked in this order is formed, and at the same time, several pads 2a are formed in the pad portion.

Then, a protective film 7 of PVX is coated on the entire surface of the substrate 1 to cover the thin film transistor TFT and the pad 2a. Then, the resin film 10 having a low dielectric constant on the protective film 7 is applied. Apply thick).

Next, the first via hole Vh1 exposing a part of the thin film transistor TFT in the pixel portion by etching the resin film 10, the protective film 7, and the gate insulating film 3 locally, and in each of the pad portion. A second via hole Vh2 exposing the pad 2a is formed.

Subsequently, after ITO is deposited on the resin film 10, the ITO is patterned, and then patterned, through the pixel electrode 8a and the second via hole Vh2 contacting the thin film transistor TFT through the first via hole Vh1. By forming the ITO pattern 9b in contact with each of the pads 2a, the array substrate in the high aperture liquid crystal display device of the present invention is completed.

Here, the process for forming the first and second via holes Vh1 and Vh2 is performed in the following manner.

4 and 5 are schematic diagrams of a pad portion of an exposure mask used in the formation of a via hole according to the related art and the present invention, and a cross-sectional view of the pad portion in an array substrate formed therefrom.

First, as shown in FIG. 4, the conventional exposure mask is provided with several opening patterns 21 corresponding to each pad in the part corresponding to the pad part in the array substrate. Therefore, after the resin film 10 itself is exposed to light using such an exposure mask, it is developed, or after the photosensitive resin film is coated on the non-photosensitive resin film 10 and then exposed and developed, the photosensitive resin film pattern is formed. When the second via hole Vh2a exposing the pad 2a is formed by etching the used resin film 10, the second via hole Vh2a corresponds to the thickness of the resin film 10. As a result, the ITO pattern 9a formed to be in contact with the pad 2a also has a large step, so that the depression of the resin film 10 due to the pressurization of the probe pin during substrate testing occurs. Contact failure may be caused.

On the other hand, the exposure mask of the present invention, as shown in Figure 5, has a plurality of opening patterns (21) corresponding to each pad in the portion corresponding to the pad portion in the array substrate, and further, the area between the pads The slit patterns 22, which are opening patterns of a fine width, are provided between the mask portions corresponding to the opening patterns 21.

In this case, when the resin film 10 itself or the additionally coated photosensitive resin film is exposed using the above-described exposure mask of the present invention, the resin film portion on the pad 2a or the additionally coated photosensitive resin film portion In addition to the exposure, the resin film portion between the adjacent pads 2a or the additionally applied photosensitive resin film portion is half-tone-exposed, thereby remaining the resin film 10 remaining in the pad portion, more precisely, the adjacent pads 2a. The thickness of the resin film 10 remaining in the inter-region becomes significantly thin, thereby reducing the step of the second via hole Vh2 and the step of the ITO pattern 9b formed to contact the pad 2a. do.

Therefore, the depression of the resin film due to the pressurization of the probe pin at the time of the substrate test is hardly caused, so that the contact failure between the pad and the test pin is not caused.

As a result, when the first and second via holes exposing the thin film transistor and the pad are formed, a slit pattern is additionally designed in the mask area corresponding to the pad part so that the resin film portion between the pads is half-tone exposed. By using this, it is possible to prevent the occurrence of contact failure between the pad and the test pin due to the depression of the resin film during the array test, thereby ensuring the test reliability.

As described above, the present invention is to reduce the thickness of the resin film between the pads through the half-tone exposure process through the design change of the exposure mask used in the formation of the via hole so that the ITO pattern contacted with each pad is formed without a large step. In this way, it is possible to prevent the occurrence of contact failure caused by the depression of the resin film by the test pin during the array test, thereby improving the array test reliability.

In addition, by lowering the step height of each pad including the ITO pattern, defects that may occur when TCP is attached to the pad in the module process can be improved.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (2)

A process of applying a thick dielectric film of a low dielectric constant on a transparent insulating substrate having a pixel portion and a pad portion, and locally etching the resin film to expose the thin film transistor portion in the pixel portion and the pad in the pad portion, respectively. Forming a 2 via hole, depositing ITO on the resin film, pixel electrode contacting the thin film transistor through the first via hole by patterning the ITO, and an ITO pattern contacting the pad through the second via hole. In the manufacturing method of the high-aperture rate liquid crystal display device containing the process of forming, The process of forming the first and second via holes completely exposes the second via hole forming region while half-tone exposing a region between adjacent second via hole forming regions to pressurize the groove fin during substrate testing. The resin film of the pad portion in which the second via hole is formed so as to have a thickness such that the resin film is not recessed is formed to have a lower level than the resin film of the pixel portion in which the first via hole is formed. . The method of claim 1, wherein the halftone exposure is A high-aperture liquid crystal display device having an opening pattern in a mask area corresponding to each pad, and using an exposure mask having slit patterns of relatively fine width in a mask area corresponding to an area between adjacent pads. Manufacturing method.

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