KR100851455B1 - 챔버 조건에 대한 공정 민감도를 감소시키는 방법 - Google Patents
챔버 조건에 대한 공정 민감도를 감소시키는 방법 Download PDFInfo
- Publication number
- KR100851455B1 KR100851455B1 KR1020077030924A KR20077030924A KR100851455B1 KR 100851455 B1 KR100851455 B1 KR 100851455B1 KR 1020077030924 A KR1020077030924 A KR 1020077030924A KR 20077030924 A KR20077030924 A KR 20077030924A KR 100851455 B1 KR100851455 B1 KR 100851455B1
- Authority
- KR
- South Korea
- Prior art keywords
- chamber
- etching
- rate
- etch
- etchant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/02—Details
- H01J2237/022—Avoiding or removing foreign or contaminating particles, debris or deposits on sample or tube
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
| 변수 | 주 에칭 | 오버에칭 |
| 조성 | Cl2, HBr(1Cl:2Br), O2(<체적비로 5%) | HBr O2(<체적비로 3%) |
| 유동율 | 200sccm | 155-160sccm |
| 코일 전력 | 500W | 500-1000W |
| 바이어스 전력 | 80W | 100-150W |
| 압력 | 4mTorr | 50mTorr |
| 온도 | 50℃ | 50℃ |
| 변수 | 주 에칭 | 오버에칭 |
| 조성 | Cl, HBr(4Cl : 1Br), | HBr, |
| O2(<체적비로 5%) | O2(<체적비로 3%) | |
| 유동율 | 100-200 sccm | 100-200 sccm |
| 코일 전력 | 300-500W | 300-500W |
| 바이어스 전력 | 80 W | 100 W |
| 압력 | 4 mTorr | 50 mTorr |
| 온도 | 10-30℃ | 10-30℃ |
Claims (8)
- 내면을 갖춘 챔버 내부의 기판을 에칭하는 방법으로서,(a) 제 1 에칭제의 용적 유동이 제 2 에칭제의 용적 유동 보다 큰 적어도 제 1 에칭제와 제 2 에칭제를 상기 챔버 내측으로 유동시키는 단계,(b) 상기 제 1 및 제 2 에칭제가 분해되도록 상기 챔버 내에 플라즈마를 형성시키는 단계, 및(c) 상기 챔버 내측으로 산소를 유입시키는 단계를 포함하며,분해된 상기 제 1 에칭제가 상기 내면 상에 재료를 증착시키는 제 1 비율이 분해된 상기 제 2 에칭제가 상기 내면 상에 재료를 증착시키는 제 2 비율 보다 작은 에칭 방법.
- 제 1 항에 있어서, 상기 제 1 에칭제는 염소를 포함하는 에칭 방법.
- 제 1 항에 있어서, 상기 제 2 에칭제는 브롬을 포함하는 에칭 방법.
- 제 1 항에 있어서, 상기 제 1 에칭제는 염소를 포함하고 상기 제 2 에칭제는 브롬을 포함하는 에칭 방법.
- 제 1 항에 있어서,(d) 실리콘 층을 포함하는 하나 이상의 층을 상기 기판으로부터 에칭하는 단계를 더 포함하는 에칭 방법.
- 제 1 항에 있어서,상기 (a) 단계 이전에 상기 내면을 세정하는 단계를 더 포함하는 에칭 방법.
- 삭제
- 제 1 항에 있어서,상기 제 1 에칭제는 염소를 포함하고 상기 제 2 에칭제는 브롬을 포함하는 에칭 방법.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/352,008 US6808647B1 (en) | 1999-07-12 | 1999-07-12 | Methodologies to reduce process sensitivity to the chamber condition |
| US09/352,008 | 1999-07-12 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020027000438A Division KR100851454B1 (ko) | 1999-07-12 | 2000-07-12 | 챔버 조건에 대한 공정 민감도를 감소시키는 방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20080013004A KR20080013004A (ko) | 2008-02-12 |
| KR100851455B1 true KR100851455B1 (ko) | 2008-08-08 |
Family
ID=23383407
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020077030924A Expired - Fee Related KR100851455B1 (ko) | 1999-07-12 | 2000-07-12 | 챔버 조건에 대한 공정 민감도를 감소시키는 방법 |
| KR1020027000438A Expired - Fee Related KR100851454B1 (ko) | 1999-07-12 | 2000-07-12 | 챔버 조건에 대한 공정 민감도를 감소시키는 방법 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020027000438A Expired - Fee Related KR100851454B1 (ko) | 1999-07-12 | 2000-07-12 | 챔버 조건에 대한 공정 민감도를 감소시키는 방법 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6808647B1 (ko) |
| EP (1) | EP1198822B1 (ko) |
| JP (1) | JP2003504864A (ko) |
| KR (2) | KR100851455B1 (ko) |
| DE (1) | DE60036215T2 (ko) |
| WO (1) | WO2001004927A2 (ko) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070056930A1 (en) * | 2005-09-14 | 2007-03-15 | International Business Machines Corporation | Polysilicon etching methods |
| US9711365B2 (en) | 2014-05-02 | 2017-07-18 | International Business Machines Corporation | Etch rate enhancement for a silicon etch process through etch chamber pretreatment |
| US10950416B2 (en) | 2018-11-16 | 2021-03-16 | Mattson Technology, Inc. | Chamber seasoning to improve etch uniformity by reducing chemistry |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5332468A (en) | 1991-10-23 | 1994-07-26 | Siemens Aktiengesellschaft | Method for structuring a layer using a ring electrode and multiple RF power sources |
| KR970013027A (ko) * | 1995-08-18 | 1997-03-29 | 김주용 | 반도체 소자의 게이트 전극 형성 방법 |
| US5756400A (en) | 1995-12-08 | 1998-05-26 | Applied Materials, Inc. | Method and apparatus for cleaning by-products from plasma chamber surfaces |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5242536A (en) | 1990-12-20 | 1993-09-07 | Lsi Logic Corporation | Anisotropic polysilicon etching process |
| JP3298161B2 (ja) | 1991-10-29 | 2002-07-02 | ソニー株式会社 | ドライエッチング方法 |
| US5256245A (en) | 1992-08-11 | 1993-10-26 | Micron Semiconductor, Inc. | Use of a clean up step to form more vertical profiles of polycrystalline silicon sidewalls during the manufacture of a semiconductor device |
| JP3169759B2 (ja) * | 1993-12-28 | 2001-05-28 | 株式会社日立製作所 | プラズマエッチング方法 |
| US5453156A (en) | 1994-11-01 | 1995-09-26 | Taiwan Semiconductor Manufactoring Company Ltd. | Anisotropic polysilicon plasma etch using fluorine gases |
| US5880033A (en) | 1996-06-17 | 1999-03-09 | Applied Materials, Inc. | Method for etching metal silicide with high selectivity to polysilicon |
| US6136211A (en) * | 1997-11-12 | 2000-10-24 | Applied Materials, Inc. | Self-cleaning etch process |
-
1999
- 1999-07-12 US US09/352,008 patent/US6808647B1/en not_active Expired - Fee Related
-
2000
- 2000-07-12 KR KR1020077030924A patent/KR100851455B1/ko not_active Expired - Fee Related
- 2000-07-12 KR KR1020027000438A patent/KR100851454B1/ko not_active Expired - Fee Related
- 2000-07-12 DE DE60036215T patent/DE60036215T2/de not_active Expired - Fee Related
- 2000-07-12 JP JP2001509061A patent/JP2003504864A/ja not_active Withdrawn
- 2000-07-12 EP EP00947339A patent/EP1198822B1/en not_active Expired - Lifetime
- 2000-07-12 WO PCT/US2000/019152 patent/WO2001004927A2/en active IP Right Grant
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5332468A (en) | 1991-10-23 | 1994-07-26 | Siemens Aktiengesellschaft | Method for structuring a layer using a ring electrode and multiple RF power sources |
| KR970013027A (ko) * | 1995-08-18 | 1997-03-29 | 김주용 | 반도체 소자의 게이트 전극 형성 방법 |
| US5756400A (en) | 1995-12-08 | 1998-05-26 | Applied Materials, Inc. | Method and apparatus for cleaning by-products from plasma chamber surfaces |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020041405A (ko) | 2002-06-01 |
| WO2001004927A3 (en) | 2001-06-07 |
| DE60036215D1 (de) | 2007-10-11 |
| KR100851454B1 (ko) | 2008-08-08 |
| KR20080013004A (ko) | 2008-02-12 |
| JP2003504864A (ja) | 2003-02-04 |
| US6808647B1 (en) | 2004-10-26 |
| WO2001004927A2 (en) | 2001-01-18 |
| EP1198822B1 (en) | 2007-08-29 |
| EP1198822A2 (en) | 2002-04-24 |
| DE60036215T2 (de) | 2008-05-21 |
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