KR100866709B1 - Method for forming capacitor of semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a capacitor of a semiconductor device, in which a capping insulating film is deposited after forming a storage electrode in a capacitor forming process using a ferroelectric material, thereby preventing loss of the storage electrode in a CMP process performed in a subsequent process, To prevent the electrical characteristics of the capacitor from deteriorating and to improve the operating characteristics and reliability of the device.

Description

[0001] The present invention relates to a method of forming a capacitor of a semiconductor device,

1 is a cross-sectional view of a device formed by a method of forming a capacitor of a semiconductor device according to the prior art;

FIGS. 2A to 2E are process sectional views showing a method of forming a capacitor of a semiconductor device according to the present invention.

Description of the Related Art

11, 51: semiconductor substrate 13, 53: element isolation insulating film

15, 55: word line 17, 57: first interlayer insulating film

19, 59: bit line contact plug 21, 61: bit line

23, 63: second interlayer insulating film 25, 65: storage electrode contact plug

27, 67: adhesive layer 29, 69: storage electrode

31, 73: third interlayer insulating film 33, 75: dielectric film

35, 77: upper electrode 37, 79: fourth interlayer insulating film

39, 81: diffusion preventing film 41, 83: metal wiring

71: capping insulating film

The present invention relates to a method of forming a capacitor of a semiconductor device, and more particularly, to a method of forming a capacitor of a semiconductor device that prevents loss of a storage electrode in a capacitor forming process using a ferroelectric material.

The cell size is reduced in accordance with the trend of high integration of semiconductor devices, and it becomes difficult to form a capacitor having a sufficient capacitance. The capacitor is composed of a storage electrode, a dielectric film, and a plate electrode. In order to increase the capacitance, there is a method of using a dielectric film having a high dielectric constant or increasing the surface area of the storage electrode.

However, since the cell size is reduced to increase the surface area of the storage electrode, a method of applying a dielectric film having a high dielectric constant is mainly used.

Conventionally, the storage electrode and the plate electrode are formed of polycrystalline silicon, and an oxide film, a nitride film, or an oxide-nitride-oxide film, which is a laminated film thereof, is used as a dielectric.

In recent years, however, MOCVD (tantalum pentoxide) such as Ta ₂ O ₅ and BST ((Ba _1-x Sr _x ) TiO ₃ ), STO (SrTiO ₃ ) or PZT (PbZr _1-x Ti _x O ₃ ) metal organic chemical vapor deposition) film is mainly applied, and the Ta ₂ O ₅ film has already been used.

On the other hand, when the dielectric film having a large dielectric constant is used, the dielectric constant can be further improved by forming the storage electrode using a metal such as TiN, W, Ru, Pt, or Ir. Development is progressing actively.

Hereinafter, a method of forming a capacitor of a semiconductor device according to the related art will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a device formed by a conventional method for forming a capacitor of a semiconductor device.

First, an element isolation insulating film 13 and a word line 15 are formed on a semiconductor substrate 11.

Next, a first interlayer insulating film 17 is formed on the entire surface.

Next, the bit line contact hole is formed by etching the first interlayer insulating film 17 with the bit line contact mask as an etching mask.

Next, a bit line contact plug 19 connected to the active region of the semiconductor substrate 11 through the bit line contact hole is formed. At this time, the bit line contact plug 19 is formed of tungsten.

A bit line 21 is then formed which is connected to the bit line contact plug 19.

Next, a second interlayer insulating film 23 is formed on the entire surface.

Then, the second interlayer insulating film 23 and the first interlayer insulating film 17 are etched by a photolithography process using a storage electrode contact mask to form a storage electrode contact hole.

Then, a polycrystalline silicon layer is deposited on the entire surface, and then a storage electrode contact plug 25 for filling the storage electrode contact hole by a front etching process or a chemical mechanical polishing (CMP) .

Then, the storage electrode contact plug 25 is recessed by a predetermined thickness in a front etching process to partially expose the upper portion of the storage electrode contact hole.

Next, an adhesive layer 27 is formed to a predetermined thickness on the entire surface. At this time, the adhesive layer 27 is formed of a Ti film.

Then, the Ti film and the storage electrode contact plug 25 are reacted with each other by a heat treatment process to form a TiSi ₂ film. At this time, the TiSi ₂ film is formed to reduce the contact resistance.

Next, the Ti film which has not reacted in the heat treatment step is removed by the wet etching process.

Then, a conductive layer (not shown) for the storage electrode is formed on the entire surface. At this time, the storage electrode conductive layer is formed of an Ir film, an IrOx film, a Pt film, a Ru film, a Re film, an Rh film, or a laminated structure thereof.

Next, the storage electrode 29 is formed by etching the stacked structure by a photolithography process using a storage electrode mask.

Then, a third interlayer insulating film 31 is formed on the entire surface.

Next, the third interlayer insulating film 31 is removed by CMP to expose the storage electrode 29. At this time, the CMP process is performed using the Pt film as a polishing barrier.

Then, a dielectric film 33 is formed on the entire surface. At this time, the dielectric film 33 is formed of a ferroelectric material such as PZT ((Pb, Zr) TiO ₃ ), SBT (SrBi ₂ Ta ₂ O ₉ ), or BLT ((Bi, La) ₄ Ti ₃ O ₁₂ ).

Next, a conductive layer (not shown) for the plate electrode is formed on the entire surface. At this time, the conductive layer for the plate electrode is formed of an Ir film, an IrOx film, a Pt film, a Ru film, a Re film, an Rh film or a laminated structure thereof.

Then, the plate electrode 35 is formed by etching the conductive layer for the plate electrode by a photolithography process using a plate electrode mask.

Next, a fourth interlayer insulating film 37 is formed on the entire surface.

Then, the fourth interlayer insulating film 37 is etched by a photolithography process using a metal wiring contact mask to form a metal wiring contact hole exposing the plate electrode 35.

Next, a metal wiring 41 connected to the plate electrode 35 is formed. At this time, a diffusion preventing film 39 is formed between the metal wiring 41 and the plate electrode 35. The diffusion prevention film 39 is formed of a TiN film (see FIG. 1)

As described above, in the method of forming a capacitor of a semiconductor device according to the prior art, a storage electrode is used as a polishing barrier in the CMP process after the formation of the storage electrode, which deteriorates the characteristics of the capacitor due to loss or damage of the storage electrode .

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems of the prior art, and it is an object of the present invention to provide a capping insulator after forming a storage electrode, thereby preventing loss or damage of the storage electrode during a subsequent CMP process, And a method of forming a capacitor of a semiconductor device.

According to an aspect of the present invention, there is provided a method of forming a capacitor of a semiconductor device,

Forming a first interlayer insulating film having a storage electrode contact plug on a semiconductor substrate;

Forming a conductive layer for a storage electrode over the entire surface,

Forming a storage electrode by etching the conductive layer for the storage electrode by a photolithography process using a storage electrode mask;

Forming a capping insulating film on the entire surface with a predetermined thickness,

Forming a second interlayer insulating film on the capping insulating film,

Removing the second interlayer insulating film by a chemical mechanical polishing process using the capping insulating film as a polishing barrier;

Removing the capping insulating film by a front etching process to expose the storage electrode,

A step of forming a ferroelectric film on the entire surface,

Forming a conductive layer for a plate electrode on the ferroelectric film;

A step of etching the conductive layer for the plate electrode by a photo etching process using a plate electrode mask to form a plate electrode,

The capping insulating film may be formed to have a thickness of 100-200 Å by using an SiN film,

Wherein the storage electrode conductive layer is formed of one selected from the group consisting of an Ir film, an IrOx film, a Pt film, a Ru film, a Re film, an Rh film,

Wherein the conductive layer for a plate electrode is formed of one selected from the group consisting of an Ir film, an IrOx film, a Pt film, a Ru film, a Re film, an Rh film,

Wherein the chemical mechanical polishing process is carried out with a slurry containing one selected from the group consisting of SiO2, CeO2, ZrO2, Al2O3, and combinations thereof as an abrasive,

(Pb, Zr) TiO ₃ ), SBT (SrBi ₂ Ta ₂ O ₉ ) or BLT ((Bi, La) ₄ Ti ₃ O ₁₂ ) is used as the ferroelectric film,

And the storage electrode mask and the plate electrode mask use the same reticle.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to the present invention.

First, an element isolation insulating film 53 and a word line 55 are formed on a semiconductor substrate 51.

Next, a first interlayer insulating film 57 is formed on the entire surface.

Next, the bit line contact hole is formed by etching the first interlayer insulating film 57 with the bit line contact mask as an etching mask.                     

Next, a bit line contact plug 59 connected to the active region of the semiconductor substrate 51 through the bit line contact hole is formed. At this time, the bit line contact plug 59 is formed of tungsten.

Then, a bit line 61 connected to the bit line contact plug 59 is formed.

Next, a second interlayer insulating film 63 is formed on the entire surface.

Then, the second interlayer insulating film 63 and the first interlayer insulating film 57 are etched by a photolithography process using a storage electrode contact mask to form a storage electrode contact hole.

Then, a polycrystalline silicon layer is deposited on the entire surface, and then a front etching process or a CMP process is performed to form a storage electrode contact plug 65 for filling the storage electrode contact hole.

Then, the storage electrode contact plug 65 is recessed by a predetermined thickness in a front etching process to partially expose the upper portion of the storage electrode contact hole.

Next, an adhesive layer 67 is formed to a predetermined thickness on the entire surface. At this time, the adhesive layer 67 is formed of a Ti film.

Then, the Ti film and the storage electrode contact plug 65 are reacted with each other by a heat treatment process to form a TiSi ₂ film. At this time, the TiSi ₂ film is formed to reduce the contact resistance.

Next, the Ti film which has not reacted in the heat treatment step is removed by the wet etching process.

Then, a conductive layer (not shown) for the storage electrode is formed on the entire surface. At this time, the storage electrode conductive layer is formed of one selected from the group consisting of an Ir film, an IrOx film, a Pt film, a Ru film, a Re film, an Rh film, and a combination thereof.

Next, a storage electrode 69 is formed by etching the stacked structure by a photolithography process using a storage electrode mask. (See FIG. 2A)

Then, a capping insulating film 71 is formed to a predetermined thickness on the entire surface. At this time, the capping insulating film 71 is formed to a thickness of 100-200 Å by using a SiN film. (See FIG. 2B)

Next, a third interlayer insulating film 73 is formed on the entire surface. At this time, the third interlayer insulating film 73 is formed of an SiOx oxide such as TEOS, PSG, or BPSG.

Thereafter, the third interlayer insulating film 73 is removed by a CMP process. At this time, the CMP process is performed using the capping insulating film 71 as a polishing barrier.

The CMP process is performed using a slurry containing one selected from the group consisting of SiO2, CeO2, ZrO2, Al2O3, and combinations thereof as an abrasive. (See FIG. 2C)

Then, the capping insulating film 71 is removed by a front etching process to expose the storage electrode 69. (See Fig. 2d)

Then, a dielectric film 75 is formed on the entire surface. At this time, the dielectric film 75 is formed of a ferroelectric material such as PZT ((Pb, Zr) TiO ₃ ), SBT (SrBi ₂ Ta ₂ O ₉ ), or BLT ((Bi, La) ₄ Ti ₃ O ₁₂ ).

Next, a conductive layer (not shown) for the plate electrode is formed on the entire surface. At this time, the conductive layer for the plate electrode is formed of one selected from the group consisting of an Ir film, an IrOx film, a Pt film, a Ru film, a Re film, an Rh film, and a combination thereof.

Then, the plate electrode 77 is formed by etching the conductive layer for the plate electrode by a photo etching process using a plate electrode mask. At this time, the plate electrode mask may use the same reticle as the storage electrode mask.

Next, a fourth interlayer insulating film 79 is formed on the entire surface.

Next, the fourth interlayer insulating film 79 is etched by a photolithography process using a metal wiring contact mask to form a metal wiring contact hole exposing the plate electrode 77.

Next, a metal wiring 83 connected to the plate electrode 77 is formed. At this time, a diffusion preventing film 81 is formed between the metal wiring 83 and the plate electrode 77. The diffusion preventing film 81 is formed of a TiN film (see FIG.

As described above, the method of forming a capacitor of a semiconductor device according to the present invention includes depositing a capping insulating film after forming a storage electrode in a capacitor forming process using a ferroelectric material, thereby preventing the storage electrode from being lost in a subsequent CMP process Thereby securing the stability of the process, thereby preventing deterioration of the electrical characteristics of the capacitor and improving the operation characteristics and reliability of the device.

Claims (7)

Forming a first interlayer insulating film having a storage electrode contact plug on a semiconductor substrate; Forming a conductive layer for a storage electrode over the entire surface, Forming a storage electrode by etching the conductive layer for the storage electrode by a photolithography process using a storage electrode mask; Forming a capping insulating film on the entire surface, Forming a second interlayer insulating film on the capping insulating film, Removing the second interlayer insulating film by a chemical mechanical polishing process using the capping insulating film as a polishing barrier; Removing the capping insulating film by a front etching process to expose the storage electrode, A step of forming a ferroelectric film on the entire surface, Forming a conductive layer for a plate electrode on the ferroelectric film; And etching the conductive layer for the plate electrode by a photolithography process using a plate electrode mask to form a plate electrode. The method according to claim 1, Wherein the capping insulating layer is formed to a thickness of 100 to 200 占 using a SiN film. The method according to claim 1, Wherein the storage electrode conductive layer is formed of one selected from the group consisting of an Ir film, an IrOx film, a Pt film, a Ru film, a Re film, an Rh film, and a combination thereof. The method according to claim 1, Wherein the conductive layer for a plate electrode is formed of one selected from the group consisting of an Ir film, an IrOx film, a Pt film, a Ru film, a Re film, an Rh film, and a combination thereof. The method according to claim 1, Wherein the chemical mechanical polishing step is performed with a slurry containing one selected from the group consisting of SiO2, CeO2, ZrO2, Al2O3, and combinations thereof as an abrasive. The method according to claim 1, Wherein said ferroelectric film is made of PZT ((Pb, Zr) TiO ₃ ), SBT (SrBi ₂ Ta ₂ O ₉ ) or BLT ((Bi, La) ₄ Ti ₃ O ₁₂ ) . The method according to claim 1, Wherein the storage electrode mask and the plate electrode mask use the same reticle.

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