KR100878272B1 - Method of manufacturing polycrystalline silicon thin film transistor - Google Patents

Abstract

A semiconductor layer of polycrystalline silicon is formed on the insulating substrate, a gate insulating film is laminated, and a conductive film containing aluminum is laminated on the top. Subsequently, a conductive film of chromium is laminated, and a etch mask is formed by etching the chromium conductive film by a photolithography process. Then, the conductive film of aluminum is etched with the etching mask to form a gate wiring, and the mask for transient etching is removed. Low concentration doped regions are formed in the semiconductor layer using the gate wirings as doping masks, respectively. Subsequently, a spacer is formed on the side of the gate wiring, and the source region and the drain region are formed in the semiconductor layer using the spacer as a doping mask. Subsequently, a first interlayer insulating film covering the gate wiring is formed, and a contact hole exposing the source and drain regions is formed by etching the gate insulating film or the first interlayer insulating film. Subsequently, a data line including source and drain electrodes connected to the source and drain regions, respectively, is formed through the contact hole, and the second interlayer insulating layer is stacked and patterned to expose the drain electrode, and the drain electrode and the upper portion of the second interlayer insulating layer are formed. A pixel electrode to be connected is formed.

Low Doping Area, Polycrystalline Silicon, Undercut, Spacer

Description

A manufacturing method of a polycrystalline silicon thin film transistor {A METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR USING POLYSILICON}

1 is a cross-sectional view showing the structure of a polycrystalline silicon thin film transistor according to an embodiment of the present invention,

2A to 2G are cross-sectional views illustrating a method of manufacturing a polysilicon thin film transistor according to an embodiment of the present invention according to a process sequence thereof.

The present invention relates to a method for manufacturing a thin film transistor, and more particularly, to a method for manufacturing a polycrystalline silicon thin film transistor using polycrystalline silicon as a semiconductor layer.

As one of the flat panel display devices which are widely used at present, a liquid crystal display device has two substrates on which a plurality of electrodes for generating an electric field are formed, a liquid crystal layer injected between the two substrates, and is attached to the outer surface of each substrate to emit light. 2. A display device including two polarizing plates for polarizing and controlling the amount of light transmitted by rearranging liquid crystal molecules of a liquid crystal layer by applying a voltage to an electrode. This is because the arrangement of molecules changes when a voltage is applied among various properties of the liquid crystal. In a liquid crystal display device using light transmission or reflection, the liquid crystal does not emit light and thus requires a light source on its own or externally.

In this case, a thin firm transistor array panel is used as a circuit board for driving each pixel independently in a liquid crystal display. The thin film transistor array substrate includes a scan signal wiring or a gate wiring for transmitting a scan signal and an image signal line or data wiring for transmitting an image signal, and a thin film transistor and a thin film transistor connected to the gate wiring and the data wiring. It includes a pixel electrode connected to and used to display an image.

In this case, amorphous silicon or polycrystalline silicon is mainly used as a semiconductor layer of the thin film transistor. When polycrystalline silicon is used, the current mobility is approximately 20 ° C. It is about 150 cm 2 / Vsec, which is larger than that of using amorphous silicon, so that a better display image quality can be obtained, and the driving circuit can be integrated in the substrate at the same time as the thin film transistor is formed, so that the material cost of the integrated circuit (IC) In this regard, the cost of the process equipment can be reduced.

However, the semiconductor layer of polycrystalline silicon has a disadvantage of low leakage resistance and a large leakage current.A lightly doped domain (LDD) structure having a lightly doped region between the channel portion and the heavily doped source and drain regions is used to minimize this. It is adopted.

However, in order to form an LDD structure, a mask for low-concentration ion doping is additionally required, resulting in an increase in cost by adding a photolithography process using a mask. In order to solve this problem, a method of forming an ion doping mask as a double layer and patterning the undercut to generate one of the double layers as a mask for high concentration doping and the other as a low concentration doping mask has been developed. However, it is difficult to uniformly form the undercut structure within the tolerance range.

An object of the present invention is to provide a method for manufacturing a thin film transistor which can minimize the manufacturing cost and can form the LDD region uniformly.

In order to solve the above problems, in the present invention, the gate electrode is patterned to have a steep side by generating an undercut, and as a doping mask for forming a source and a drain region by forming a spacer on the side of the steep gate electrode. use.

In the method for manufacturing a thin film transistor according to the present invention, a semiconductor layer of polycrystalline silicon is formed on an insulating substrate, a gate insulating film covering the semiconductor layer is formed, and a conductive material for a gate wiring is laminated thereon. Subsequently, an etching mask is formed on the conductive material for the gate wiring, and the gate wiring including the gate electrode is formed by etching the conductive material for the gate wiring to be undercut using the etching mask. Subsequently, after the etching mask is removed, impurities are implanted at low concentration into the semiconductor layer using the gate wiring as a doping mask to form low concentration doped regions, respectively. Subsequently, spacers are formed on the side surfaces of the gate wirings, and the source and drain regions are formed by ion implanting impurities into the semiconductor layer at a high concentration using the spacers as a doping mask. Subsequently, a first interlayer insulating film covering the gate wiring is formed, and a contact hole exposing the source and drain regions is formed by etching the gate insulating film or the first interlayer insulating film. Subsequently, a data line including source and drain electrodes connected to the source and drain regions, respectively, is formed through the contact hole.

A pixel electrode connected to the drain electrode may be formed, and the pixel electrode may be formed of a transparent conductive material or a conductive material having a reflectance.

The spacer forming step is preferably formed by stacking silicon nitride or silicon oxide and etching by reactive ion etching, and the gate wiring preferably includes aluminum or an aluminum alloy.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, the structure of a thin film transistor according to an embodiment of the present invention will be described in detail with reference to FIG. 1.

1 is a cross-sectional view illustrating a structure of a polysilicon thin film transistor according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a source and a drain which are positioned on both sides of the channel region 151 and the channel region 151 on the insulating substrate 110, respectively, and are heavily doped with n-type or p-type impurities. A lightly doped region 152, 154 between the region 153, 155, the channel region 151, and the source and drain regions 153, 155 and doped with a low concentration of p-type or n-type impurities. A semiconductor layer 150 made of polycrystalline silicon is formed. Here, the source and drain regions 153 and 155 may include silicide layers.

A gate insulating layer 140 made of silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is formed on the substrate 110 to cover the semiconductor layer 150.

The gate insulating layer 140 is connected to a gate line (not shown), receives a scan signal or a gate signal from the gate line, and is a part of the gate wiring overlapping the channel region 151 of each semiconductor layer 150. The gate electrode 123 is formed. Meanwhile, a storage wiring for forming a storage capacitor may be formed on the same layer as the gate electrode 123 to overlap the pixel electrode formed later. Here, the gate electrode 123 has a steep inclination angle of the side surface of the gate electrode 123 to easily form a spacer used as a doping mask to form source and drain regions 153 and 155 which are highly doped regions in the manufacturing process. This will be described in detail in the manufacturing process. In this case, the gate wiring and the sustain wiring may include a conductive material having a low resistance, such as aluminum or an aluminum alloy, and may include a conductive material having excellent contact properties with other materials.

A first interlayer insulating layer 810 is formed on the gate line including the gate electrode 123, and the first interlayer insulating layer 810 together with the gate insulating layer 140 exposes the source and drain regions 153 and 155. It has contact holes 813 and 815. In this case, the first interlayer insulating film 810 may have an a-Si: C: O film or a-Si: O: F film (low dielectric constant CVD film) or low dielectric constant deposited by plasma enhanced chemical vapor deposition (PECVD). The branch may be made of an organic insulating material. Here, the a-Si: C: O film and the a-Si: O: F film (low dielectric constant CVD film) deposited by such a PECVD method have a dielectric constant of 4 or less (dielectric constant of 2 to 4). ), The dielectric constant is very low. Therefore, even a thin thickness does not cause a parasitic capacity problem. In addition, the a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by PECVD method have a 4 to 10 times faster process time than the silicon nitride film. It is also very advantageous in terms of.                     

The first interlayer insulating layer 810 is connected to a data line (not shown) that crosses a gate line and defines a pixel area, and is connected to a source region 153 of the semiconductor layer 150 through a contact hole 813. A source electrode 173 is formed, and a drain electrode 175 is formed on the opposite side of the source electrode 173 around the gate electrode 123, and the drain electrode 175 forms a contact hole 815. It is connected to the drain region 155 through.

A second interlayer insulating layer 820 is formed on the first interlayer insulating layer 810 on which data wirings including source and drain electrodes 173 and 175 are formed, and a drain electrode is formed on the second interlayer insulating layer 820. A waypoint 825 that reveals 175 is open.

A transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or the like is formed on the second interlayer insulating film 820 of the pixel area defined by the intersection of the data line (not shown) and the gate line (not shown), or A pixel electrode 191 made of a conductive material having reflectivity, such as silver or silver alloy or aluminum or aluminum alloy, is formed.

In the structure of the thin film transistor according to the exemplary embodiment of the present invention, the thin film transistor is illustrated as a structure in which the thin film transistor is connected to the pixel electrode.

Next, a method of manufacturing the thin film transistor according to the exemplary embodiment of the present invention will be described with reference to FIGS. 2A to 2G.

First, as shown in FIG. 2A, amorphous silicon is laminated on a transparent insulating substrate 110 and irradiated with laser to crystallize the amorphous silicon layer into the polycrystalline silicon layer 150, and then patterned by a photolithography process using a mask. . In this case, in order to increase the crystallinity of the polycrystalline silicon layer 150, heat treatment or laser annealing may be performed.

Next, as shown in FIG. 2B, a gate insulating layer 140 made of silicon nitride is deposited using chemical vapor deposition. Subsequently, a lower film of aluminum or an aluminum alloy, which is a conductive material for gate wiring having a low resistance, and an upper film made of chromium or the like are deposited by sputtering or the like, and then sequentially formed, and then the upper film is patterned to overetch. The mask 200 is formed. Subsequently, the gate layer 123 is formed by etching the lower layer for the gate wiring using the transient etching mask 200 as an etching mask. At this time, the etching is performed so that an under cut occurs in the lower portion of the transient etching mask 200 so that the side of the gate electrode 123 has a steep inclination angle, which facilitates spacers on the side of the gate electrode 123. To form. Here, the transient etching mask 200 is formed of a conductive material such as chromium, but may be formed using an organic material or an inorganic insulating material.

Subsequently, as shown in FIG. 2C, the N-type or P-type impurities are implanted at low concentration using the gate electrode 123 as a doping mask, and the ion is implanted at a low concentration using the gate electrode 123 as a doping mask. The lightly doped regions 152 and 154 are formed on both sides, and the channel region 151 is defined under the gate electrode 123.

Subsequently, as shown in FIG. 2D, an insulating film of silicon nitride or silicon oxide is stacked on the substrate, and the insulating film is etched through reactive ion etching to form spacers 300 on both sides of the gate electrode 123. At this time, since the side inclination angle of the gate electrode 123 is steep, the spacer 300 may be easily formed when the insulating film is stacked and etched, and may be uniformly formed on the substrate. Subsequently, using the spacer 300 as a high concentration doping mask, ion implantation of high concentrations of N-type or P-type impurities into the semiconductor layer 150 is performed to provide source and drain regions 153 and 155 on both sides of the semiconductor layer 150. Form. In the method of manufacturing the thin film transistor according to the present invention, the spacer 300 may be uniformly formed, and thus the widths of the lightly doped regions 152 and 154 disposed under the spacer 300 may be uniformly formed. Therefore, the characteristics of the thin film transistor can be secured uniformly over the entire substrate.

Next, as shown in FIG. 2E, a first interlayer insulating film 810 is formed thereon to form a gap between the gate wiring including the gate electrode 123 and the data wiring including a data line, a source electrode, and a drain electrode to be formed later. Insulate. In this case, the first interlayer insulating film 810 may be formed by growing an a-Si: C: O film or an a-Si: O: F film by chemical vapor deposition (CVD). It may be formed. For example, the first interlayer insulating layer 810 and the gate insulating layer 140 are patterned by a photolithography process using a mask to form contact holes 813 and 815 exposing source and drain regions 153 and 155 of the semiconductor layer.

Subsequently, as shown in FIG. 2F, a metal for data wiring such as chromium (Cr) or molybdenum (Mo) is deposited and patterned to form a data wiring including a source electrode 173 and a drain electrode 175. In this case, the source electrode 173 and the drain electrode 175 are connected to the source and drain regions 153 and 155 through the contact holes 813 and 815.

Subsequently, as shown in FIG. 2G, the second interlayer insulating layer 820 is coated on the upper portion thereof, and then, the upper portion of the drain electrode 175 is etched to form the gas passage 825. In this case, the second interlayer insulating film 820 may be formed by growing an a-Si: C: O film or an a-Si: O: F film by chemical vapor deposition (CVD). It may be formed.

Finally, as shown in FIG. 1, a transparent conductive material such as ITO or IZO or a conductive material having reflectivity is deposited and patterned to form the pixel electrode 191. In this step, the pixel electrode 191 is connected to the drain electrode 175 through the way hole 825, respectively.

In the method of manufacturing a thin film transistor for a display device according to an exemplary embodiment of the present invention, the gate wiring conductive layer is etched so that undercut is excessively formed to form a steep side of the gate electrode, and then an insulating film is stacked and etched to form both sides of the gate electrode. A spacer is formed in the film, which is used as a mask for forming a lightly doped region.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, in the method of manufacturing the thin film transistor according to the present invention, the spacer may be easily formed on the side of the gate electrode by excessively etching the gate electrode, thereby minimizing the manufacturing cost. In addition, the lightly doped region may be uniformly formed using a spacer, thereby uniformly securing the characteristics of the thin film transistor.

Claims (5)

Forming a semiconductor layer of polycrystalline silicon on top of the insulating substrate, Forming a gate insulating film covering the semiconductor layer; Stacking the conductive material for the gate wiring; Forming an etching mask on the conductive material for gate wiring; Forming a gate wiring including a gate electrode by etching the conductive material for the gate wiring to be undercut by using the etching mask; Removing the etching mask; Forming a lightly doped region by ion implanting impurities into the semiconductor layer at low concentration using the gate wiring as a doping mask; Forming a spacer on a side of the gate wiring; Forming a source region and a drain region by implanting impurities at a high concentration into the semiconductor layer using the spacer as a doping mask; Forming a first interlayer insulating film covering the gate wiring; Etching the gate insulating film or the first interlayer insulating film to form contact holes exposing the source and drain regions, respectively; Forming a data line including source and drain electrodes respectively connected to the source and drain regions through the contact hole; Method of manufacturing a thin film transistor comprising a. In claim 1, And forming a pixel electrode connected to the drain electrode. In claim 2, And the pixel electrode is made of a transparent conductive material or a conductive material having a reflectance. In claim 1, The forming of the spacer may include stacking silicon nitride or silicon oxide and etching the same by reactive ion etching. In claim 1, And the gate wiring is formed of aluminum or an aluminum alloy.

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