KR100870689B1 - Charge / discharge device, plasma display panel and charge / discharge method - Google Patents

Abstract

In the charge / discharge device 602 that charges the charge / discharge target capacitance Cp, one terminal is coupled to the first power source GND through the first switch means SW11, and the second power source is connected to the second power source Vs + Vo. One terminal is coupled to the connection point of the recovery capacitor Cr1 for recovery of electrical energy and the other terminal of the second power supply and recovery capacitor, and the other terminal is coupled to the charge / discharge target capacitance through the switch means SW12. The terminals are coupled to the first path forming means D11 for charging the charge / discharge target capacitance through the resonant inductor L1 when the first switch means is turned on, and at a connection point of one terminal of the first power supply and the recovery capacitor. One terminal is coupled, and the other terminal is coupled to the charge / discharge target capacitance, and when the second switch means is turned on, the charge / discharge target capacitance is discharged through the resonant inductor L1 to electrically recover the capacitor. Recovering the second comprises a path forming means (D12).

Charge / discharge device, power recovery circuit, clamp circuit, control signal generation circuit, recovery capacitor

Description

Charge / discharge device, plasma display panel and charging / discharging method {CHARGING / DISCHARGING DEVICE, PLASMA DISPLAY PANEL, AND CHARGING / DISCHARGING METHOD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the recovery of electrical energy accumulated in capacitance, and in particular, an apparatus for recovering charge accumulated by applying a pulsed voltage to a capacitance formed in a cell constituting a screen of a plasma panel display (PDP), a plasma. A display panel and a charging / discharging method are provided.

The technique of recovering the electrical energy of an applied pulse is collect | recovered by the electrical energy collection capacitor collect | recovering the electric charge accumulate | stored by application of the sustain pulse voltage to the capacitance formed in the some cell which comprises the screen of a PDP. The recovered charge is used for application of the next sustain pulse voltage. In the technique, the charge accumulated in the cell in the rise of one application pulse is recovered in the fall of the pulse.

Japanese Patent Laid-Open No. 10-105114 (A) published on April 24, 1998, describes a power recovery device of a PDP that enables charging and discharging of electric power even with respect to a negative voltage. The power recovery device is a constant voltage charging and discharging unit which charges a positive voltage and discharges a charging constant voltage to the discharge electrode at the next electrode discharge, and charges a negative voltage to discharge the charging negative voltage at the next electrode discharge. And a controller for controlling the charging and discharging of the negative voltage charging and discharging unit and the input of the external voltage.

Patent Document 1: Japanese Patent Application Laid-Open No. 10-105114

International publication WO 00/00956 (A), published January 6, 2000, discloses a method and apparatus for generating a control signal capable of variably determining the switching timing of a power recovery circuit of a plasma display panel television. The variable range pulse generator generates a variable range pulse that defines the maximum allowable variable range of the recovery power providing time, and the first counter is enabled by the variable range pulse to count the clock signal to periodically count the count value. Output The second counter and the third counter set the first reference value and the second reference value by counting the number of switching of the first switch and the second switch, respectively. The rising pulse generator periodically compares the count value with the first reference value and, when both become equal, inverts the logic level of the output signal from low to high. The falling pulse generator periodically compares the count value with the second reference value and inverts the logic level of the output signal from high to low when both become equal. The AND gate generates a control signal by logically outputting the output signals of the rising pulse generator and the falling pulse generator. The pulse duration of the control signal is determined by the first reference value and the second reference value, and these two reference values can be determined externally.

Patent Document 2: WO 00/00956

In the PDP, as a pulse waveform applied to an electrode for generating a discharge in a cell, an asymmetric waveform waveform may be used in some cases. In this case, in the ordinary power recovery circuit, the potential of the power recovery capacitor gradually shifts in one polarity direction, or the power applied to the display electrode capacitor cannot be sufficiently recovered.

The inventors have recognized that it is desirable to realize a circuit capable of sufficiently recovering the supplied electrical energy even when a periodic pulse-shaped voltage of any waveform including an asymmetric waveform is applied to the electrode for display.

An object of the present invention is to realize a circuit capable of sufficiently recovering electrical energy supplied to a capacitance by a periodic pulsed voltage of an arbitrary waveform.

According to a feature of the present invention, in a charge / discharge device for charging a charge / discharge target capacitance by applying a voltage, one terminal is coupled to a first power source through a first switch means and another terminal is connected to a second power source through a second switch means. Is coupled to the connection point of the recovery capacitor for recovery of electrical energy, the second power supply and the other terminal of the recovery capacitor, and the other terminal is coupled to the capacitance to be charged and discharged, One terminal is coupled to the first path forming means for charging the charge / discharge target capacitance through the resonant inductor when the switch means is turned on, and the connection point between the first power supply and the one terminal of the recovery capacitor, and the charge and discharge The other terminal is coupled to the target capacitance, and the charge / discharge target capacitance is passed through the resonant inductor when the second switch means is turned on. The discharges to a second-path forming means, and that the first and second switching means, a control means for controlling the first and the second path forming means for recovering the electric energy to the recovery capacitor.

The present invention also relates to a charge / discharge method for realizing the function of the above-described apparatus.

According to the present invention, the electrical energy supplied to the capacitance can be sufficiently recovered by applying a pulse shape voltage of an arbitrary waveform.

BRIEF DESCRIPTION OF THE DRAWINGS The figure which shows the structure of the display device of a typical example by embodiment of this invention.

2 is a diagram illustrating a cell structure of a typical example of the PDP 10.

3 illustrates a schematic driving sequence of output drive voltage waveforms of an X driver circuit, a Y driver circuit, and an A driver circuit according to an embodiment of the present invention;

Fig. 4A is a diagram useful in explaining an energy loss in resistance when charge is accumulated in a capacitance of a display device by a voltage source in a sustain circuit.

Fig. 4B is a diagram useful in explaining the energy loss in resistance when charge is accumulated in the capacitance of the display electrode through the resonant inductor by the voltage source in the conventional improved sustain circuit having the resonant inductor. .

Fig. 5A is a diagram showing a conventional pulse power supply and recovery circuit having an electrical energy recovery, that is, a power recovery function, used in a sustain circuit.

FIG. 5B is a diagram showing a change in voltage between the both ends of the display electrode capacitor when the pulse power supply and recovery circuit of FIG. 5A is used when a pulse is applied. FIG.

Fig. 6 shows a schematic waveform of a frequently used sustain pulse voltage.

7 illustrates a pulse voltage application circuit for applying a pulse voltage to a pair of display electrodes according to an embodiment of the present invention.

8A is a diagram showing waveforms of pulses applied to capacitances between display electrodes of a PDP according to an embodiment of the present invention.

FIG. 8B is a diagram showing on / off states of control signals of the control signal generation circuit of FIG. 7 according to an embodiment of the present invention. FIG.

9 (a) to 9 (f) are diagrams showing examples of waveforms of various pulses to which the present invention is applicable.

An embodiment of the present invention will be described with reference to the drawings. In the drawings, like reference numerals refer to like elements.

1 shows a configuration of a display device 60 of a typical example according to an embodiment of the present invention. The display device 60 includes a three-electrode surface discharge type PDP 10 having a display surface composed of an array of m × n cells, and a drive unit 50 for selectively emitting an array of cells. For example, it is used for a television receiver, a monitor of a computer system, and the like.

In the PDP 10, display electrodes X and Y constituting electrode pairs for generating display discharges are arranged in parallel, and address electrodes A are arranged so as to be orthogonal to these display electrodes X and Y. . The display electrode X is a sustain (hold) electrode, and the display electrode Y is a scan (scan) electrode. The display electrodes X and Y typically extend in the row direction or the horizontal direction of the screen, and the address electrodes A extend in the column direction or the vertical direction.

The drive unit 50 includes a driver control circuit 51, a data conversion circuit 52, a power supply circuit 53, an X electrode driver circuit or an X driver circuit 61, a Y electrode driver circuit or a Y driver circuit 64. And an address electrode driver circuit or an A driver circuit 68, and are mounted in the form of an integrated circuit which may optionally include a ROM. In the drive unit 50, field data Df indicating the light emission intensities of three primary colors R, G, and B are input together with various synchronization signals from an external device such as a TV tuner or a computer. The field data Df is temporarily stored in the field memory of the data conversion circuit 52. The data conversion circuit 52 converts the field data Df into subfield data Dsf for gray scale display and supplies it to the A driver circuit 68. The subfield data Dsf is a set of display data of 1 bit per cell, and the value of each bit indicates the necessity / unnecessity of light emission of each cell in the corresponding subfield SF.

The X driver circuit 61 includes a reset circuit 62 for applying a voltage for initialization to the display electrode X and the display discharge to the cells in order to equalize the wall voltages of a plurality of cells constituting the PDP display surface. And a sustain circuit 63 for applying a sustain pulse to the display electrode X for generation. The Y driver circuit 64 includes a reset circuit 65 for applying a voltage for initialization to the display electrode Y, a scan circuit 66 for applying a scan pulse to the display electrode Y in addressing, and a cell. And a sustain circuit 67 for applying a sustain pulse to the display electrode Y in order to generate display discharge. The A driver circuit 68 applies an address pulse to the address electrode A designated by the subfield data Dsf in accordance with the display data.

The driver control circuit 51 controls the application of the pulse voltage and the transfer of the subfield data Dsf. The power supply circuit 53 supplies driving power to the required portion in the unit. The driver control circuit 51 receives the information indicating the lit cell and the non-lighted cell by the subfield data Dsf from the data conversion circuit 52, and displays the display associated with the lit cell and the non-lighted cell. The electrodes X and Y may be determined, and the data regarding the display electrodes X and Y related to the non-lighting cell may be supplied to the sustain circuits 63 and 67.

2 shows a cell structure of a typical example of the PDP 10. The PDP 10 is composed of a pair of substrate spheres (structures in which cell components are provided on a glass substrate) 100 and 20. On the inner surface of the front side glass substrate 11, display electrodes X and Y are arrange | positioned one by one in each row of the display surface ES of n rows m columns. In this figure, the subscript j of the display electrodes X and Y represents the position of an arbitrary row, and the subscript i of the address electrode A represents the position of an arbitrary column. The display electrodes X and Y are made of a transparent conductive film 41 forming a surface discharge gap and a metal film 42 superimposed on the edge thereof, and the dielectric layer 17. And a protective film 18. The address electrodes A are arranged one by one in the inner surface of the back side glass substrate 21, and these address electrodes A are covered with the dielectric layer 24. A partition wall 29 is provided on the dielectric layer 24 to partition the discharge space for each column. Although the pattern of the partition of FIG. 2 is a stripe pattern, a grid | lattice form, a zigzag shape (meander), or a trapezoidal shape may be sufficient, and this invention is not limited by a partition shape. The color display phosphor layers 28R, 28G, and 28B covering the surface of the dielectric layer 24 and the side surface of the partition wall 29 are locally excited by the ultraviolet light emitted by the discharge gas and emit light. Italic letters R, G, and B in the figure indicate light emission colors of the phosphors. The color arrangement is a repeating pattern of R, G, and B in which the cells of each column are the same color.

One picture (picture) is typically composed of one frame period, one frame consists of two fields in interlace scanning, and one frame consists of one field in progressive scanning. It is. In the display by the PDP 10, in order to perform color reproduction by binary emission control, one field F of a time series of an input image of such one field period is typically a predetermined number. The data is divided into subfields SF of (q). Typically, each field F is replaced with a set of q subfields SF. Often, in order for the sub-fields (SF) 2 ^{0, 1} 2, 2 ^2, to give different weights, such as ... 2 ^q-1 and sets the number of times of display discharge in each subfield (SF). By the combination of light emission / non-emission in subfield units, luminance can be set in steps of N (= 1 + 2 ¹ +2 ² + ... + 2 ^q-1 ) for each color of R, G and B. In accordance with such a field configuration, the field period Tf, which is a field transfer period, is divided into q subfield periods Tsf, and one subfield period Tsf is assigned to each subfield SF. The subfield period Tsf is further divided into a reset period TR for initialization, an address period TA for addressing, and a display period TS for light emission. Typically, while the lengths of the reset period TR and the address period TA are constant regardless of the weight, the number of pulses in the display period TS increases as the weight increases, and the length of the display period TS The larger the weight, the longer. In this case, the length of the subfield period Tsf also increases as the weight of the corresponding subfield SF increases.

3 illustrates a schematic drive sequence of the output drive voltage waveforms of the X driver circuit 61, the Y driver circuit 64, and the A driver circuit 68 according to an embodiment of the present invention. In addition, the waveform shown is an example, and can change various amplitude, polarity, and timing.

The order of the reset period TR, the address period TA, and the sustain period TS are the same in q subfields SF, and the driving sequence is repeated for each subfield SF. In the reset period TR of each subfield SF, the negative polarity pulse Prx1 and the positive polarity pulse Prx2 are sequentially applied to all the display electrodes X, The positive pulse Pry1 and the negative pulse Pry2 are sequentially applied to all the display electrodes Y. The pulses Prx1, Pry1, and Pry2 are ramp waveforms or obtuse pulses whose amplitude increases at a rate of change at which small discharges occur. The pulses Prx1 and Pry1 initially applied are applied to all cells to generate an appropriate wall voltage of the same polarity regardless of light emission / non-light emission in the previous subfield SF. By applying the pulses Prx2 and Pry2 to the cells with proper wall charges, the wall voltage can be adjusted to a value corresponding to the difference between the discharge start voltage and the pulse amplitude. The driving voltage applied to the cell is a synthesized voltage indicating the difference in the amplitude of the pulses applied to the display electrodes X and Y.

In the address period TA, wall charges necessary for sustaining light emission are formed only in cells to emit light. Negative scan pulses are applied to the display electrodes Y corresponding to the selection rows for every row selection period (scan time for one row) while all the display electrodes X and all the display electrodes Y are biased to a predetermined potential. Apply (-Vy). Simultaneously with this row selection, the address pulse Va is applied only to the address electrode A corresponding to the selection cell which should generate the address discharge. That is, the potential of the address electrodes A ₁ to A _m is binary-controlled based on the sub-field data Dsf for m columns of the selection row j. In the selected cell, discharge between the display electrode Y and the address electrode A occurs. The address discharge triggers, and subsequent surface discharge occurs between the display electrodes XY.

In the sustain period TS, a sustain pulse Ps of a predetermined polarity (positive polarity in the example in the drawing) is first applied to all the display electrodes Y. FIG. Thereafter, the sustain pulse Ps is applied to the display electrode X and the display electrode Y alternately. The amplitude of the sustain pulse Ps is the sustain voltage Vs. By application of the sustain pulse Ps, surface discharge occurs in a cell in which a predetermined wall charge remains. The number of times of applying the sustain pulse Ps corresponds to the weight of the subfield SF as described above. In addition, in order to prevent unnecessary counter discharge throughout the sustain period TS, the address electrode A is biased with the voltage Vas of the same polarity as the sustain pulse Ps.

In FIG. 2, a capacitor formed of a pair of display electrodes Xj and Yj has a capacitor C. In FIG. The sustain circuits 63 and 67 of FIG. 1 apply the voltage Vs of the two series sustain pulses Ps of FIG. 3 between the pair of display electrodes Xj and Yj.

4A shows charge (q = CV) in the capacitor C of the display electrodes Xj and Yj by the voltage source V of the voltage Vs = V in the sustain circuits 63 and 67. It is helpful to explain the energy loss in the resistance R in one row (one line) when is accumulated. And the charge supplied from the voltage source (V) q = CV, the energy (E) supplied from the power source CV ^2, and the capacity of electric energy accumulated in the (C) is E = CV ^2/2, and the electrical energy supplied 1 / 2 is consumed by the resistor R and disappears.

4B shows the display electrode through the resonant inductor L by the voltage source V / 2 of the voltage Vs = V / 2 in the conventional improved sustain circuit having the resonant inductor L. FIG. It is helpful to explain the energy loss in the resistance R when the charge q = CV is accumulated in the capacitance C of (Xj and Yj). Resonant inductor (L) and a capacitor (C) forms a resonant circuit, and energy loss in the resistance (R) is sufficiently smaller than the CV ^2/2.

FIG. 5A shows a conventional pulse power supply and recovery circuit 10 having electrical energy recovery, that is, a power recovery function, used for the sustain circuits 63 and 67. FIG. 5B shows a voltage between both ends of the display electrode capacitor (capacitance) C when the pulse power supply and recovery circuit 10 of FIG. 5A is used when a pulse is applied. The change is shown.

In FIG. 5A, the pulse power supply and recovery circuit 12 includes a power recovery capacitor Cr having a large capacitance with one display electrode grounded, and one terminal thereof in series with the capacitor Cr. One terminal is coupled to the connection point of the diodes D1 and D2 coupled in parallel with the opposite polarity through the switches SW1 and SW2, respectively, and the other terminals of the capacitors C Switch at a connection point between a resonant inductor L coupled to one electrode of each pair of display electrodes of one pair or a plurality of pairs, the other terminal of the resonant inductor L, and one electrode of each pair of display electrodes thereof. A clamp circuit 14 is coupled to couple the positive voltage source V of the predetermined voltage V through SW4 and couple its connection point to the ground point GND via the switch SW5.

Referring to FIGS. 5A and 5B, charges of the voltage V / 2 are initially stored in the capacitor Cr, and charges are not accumulated in the display electrode capacitor C. FIG. Shall be. At the start of the rise period of the pulse P, when the switch SW1 is turned on, a supply current flows from the capacitor Cr to the display electrode capacitor C through the switch SW1 and the resonant inductor L, and the charge (q to CV) is accumulated in the capacitor C, the voltage of the capacitor C rises, and a rise of the pulse P is formed. When the voltage of the capacitor C has almost reached the peak voltage, the switch SW4 of the clamp circuit 14 is turned on. In addition, no current flows in the direction opposite to the supply current by the diode D1. Thus, the switch SW1 is turned off at any timing for a period from reaching the peak voltage until the turn-off timing of the switch SW4. In addition, the peak voltage is slightly lower than the voltage (V). In the clamp period, the voltage source of the clamp circuit 14 clamps the voltage of the capacitor C to the voltage V, and maintains the voltage of the display electrode capacitor C to the voltage V. FIG. After that, the switch SW4 is turned off.

At the start of the falling period of the pulse P, when the switch SW2 is turned on, a reflux current flows from the capacitor C to the recovery capacitor Cr through the switch SW2 and the resonant inductor L, and the charge ( q to CV are additionally accumulated in the capacitor Cr, so that the voltage of the capacitor C drops, and a drop of the pulse P is formed. When the voltage of the capacitor C has almost reached the peak voltage in the negative direction, the switch SW5 is turned on. Its peak voltage is slightly above ground potential (0V). In the falling period, the ground point GND of the clamp circuit 14 clamps the voltage of the capacitor C to the ground potential OV and maintains the voltage of the display capacitor C at the ground potential 0V. In addition, no current flows in the direction opposite to the reflux current by the diode D2. Therefore, the switch SW2 is turned off at any timing for a period from reaching the peak voltage until the turn-off timing of the switch SW5. After that, the switch SW5 is turned off.

In this way, most of the electric charge, that is, the electric power supplied from the capacitor Cr to the capacitor C is recovered. The clamp circuit 14 compensates the voltage of the capacitor C to be a predetermined voltage (V). In this way, when the waveform of the pulse P is symmetrical with respect to the rising and falling, the power supplied to the capacitor C is sufficiently recovered.

6 shows a schematic waveform of a sustain pulse voltage which is frequently used. In the waveform, when the pulse PR rises, the voltage between the display electrodes increases from the ground potential (0V) to almost the potential (Vs + Vo), and the potential (Vs + Vo) in the clamp period PCL1. Is maintained at, the potential is lowered from the potential (Vs + Vo) to the potential (Vs) in the discharge drop (PF1), maintained at the potential (Vs) in the clamp period (PCL2), and the potential at the drop (PF2) of the pulse. It falls to almost ground potential (0V) from (Vs), and is maintained at ground potential (0V) in clamp period PCL3. The voltage Vs may be a voltage Vo.

In the power recovery circuit 12 of FIG. 5A, when a pulse having a waveform as shown in FIG. 6 is used, at the falling of the pulse, rather than the charge supplied from the capacitor Cr to the capacitor C at the rising of the pulse. The charge collected from the capacitor C to the capacitor Cr is significantly small, and the voltage of the charge stored in the power recovery capacitor Cr gradually shifts from V / 2 toward the positive electrode. Therefore, the power recovery circuit 12 of FIG. 5 cannot be used for the pulse of the waveform of FIG. As an alternative arrangement, the circuit of Fig. 5A may be modified to recover only a portion of the power supplied to the display electrode capacitor C between the ground potential GND and the potential Vs. However, the recovery of power is not enough.

Most of the electric charge supplied from the capacitor Cr at the rise of the pulse is preferably recovered to the capacitor Cr.

FIG. 7 shows a pulse voltage application circuit 602 for applying a pulse voltage to a pair or a plurality of pairs of display electrodes X and Y having a capacitor Cp according to an embodiment of the present invention. The pulse voltage application circuit 602 includes a pulse power supply and recovery circuit 110 for supplying and recovering power when the pair of pulses P1 and P2 rises, and the last of the pair of pulses P1 and P2. A pulse power supply and recovery circuit 120 for supplying and recovering electric power in the fall of the circuit, a clamp circuit 140 for clamping the voltage between the display electrodes X and Y to a predetermined voltage, and a pulse power supply and recovery circuit. A control signal generation circuit 604 for generating a signal for controlling the on / off operation of the switches SW11 to SW45 in the 110 and 120 and the clamp circuit 140 is included. The pulse voltage application circuit 602 may further include the pulse power supply and recovery circuit 130 for supplying and recovering electric power in the initial drop of the pair of pulses P1 and P2. The switches SW11 to SW45 may be transistors.

FIG. 8A shows waveforms of a pair of pulses P1 and P2 among the periodic pulses applied to the capacitor Cp between the display electrodes of the PDP 10 according to the embodiment of the present invention. FIG. 8B shows on / off of the control signals C _{SW11 to} C _SW45 of the control signal generation circuit 604 of FIG. 7 for controlling the switches SW11 to SW45 according to the embodiment of the present invention. Indicates the state of.

In the pulsed power supply and recovery circuits 110 and 120 of FIG. 7, the recovery capacitor Cr1 is used to supply power at one rising portion of the pair of pulses P1 and P2 and to draw the power at the other rising portion. And recovers power at one falling portion of the pair of pulses and recovers the power at the other falling portion using the recovery capacitor Cr2.

The pulse power supply and recovery circuit 110 includes a power recovery capacitor having one terminal coupled to the ground point GND through the switch SW11 and the other terminal coupled to the constant voltage source Vs + Vo through the switch SW12. Cr1), diode D11 having an anode (anode) coupled via switch SW13 to one terminal of capacitor Cr1 and switch SW12, and another terminal and switch of capacitor Cr1. One terminal is coupled to a connection point of a diode D12 having an anode coupled to a connection point of SW11 through a switch SW14, and a cathode (cathode) of the diodes D11 and D12 and connected to 1 of the capacitance Cp. The resonant inductor L1 having the other terminal coupled to the display electrode of one (X or Y) of each pair of the pair or plural pairs of display electrodes X and Y is included.

The pulse power supply and recovery circuit 120 has a power recovery capacitor Cr2 having one terminal coupled to the constant voltage source Vs through the switch SW21 and the other terminal coupled to the ground point GND through the switch SW22. And a switch (D21) having a cathode coupled to the connection point of one terminal of the capacitor Cr2 and the switch SW22 via the switch SW23, and a connection point of the switch (SW21) to the other terminal of the capacitor Cr2. One terminal is coupled to the connection point of the diode D22 having the cathode coupled to the diode D21 and the anode of the diodes D21 and D22 via SW24, and each of the pair of display electrodes X and Y of the capacitor Cp is connected. One side of the pair includes a resonant inductor L2 having the other terminal coupled thereto.

The pulse power supply and recovery circuit 130 has a power recovery capacitor in which one terminal is coupled to the constant voltage source Vs + Vo through the switch SW31 and the other terminal is coupled to the constant voltage source Vs through the switch SW22. (Cr3), the diode D31 having a cathode coupled to the connection point of one terminal of the capacitor Cr3 and the switch SW32 through the switch SW33, and the connection point of the switch SW31 with the other terminal of the capacitor Cr3. A terminal is coupled to a junction point of a diode D32 having a cathode coupled thereto via a switch SW34, and an anode of diodes D31 and D32, and each pair of display electrodes X and Y of the capacity Cp is connected. It includes a resonant inductor (L3) coupled to the other terminal on one side.

The clamp circuit 140 includes a constant voltage source of a predetermined voltage (Vs + Vo) coupled through a switch SW41 to a connection point of the resonant inductors L1, L2, and L3 and one display electrode thereof, and the connection point thereof. And a constant voltage source of a predetermined voltage Vs coupled through the switch SW42, and a ground point GND coupled through the switch SW45 to its connection point.

Referring to the operation, in the pulse power supply and recovery circuit 12 of FIG. 6A, after the power of the display device 60 of FIG. 1 is turned on, the capacitors Cr1 and Cr2 repeat charging and discharging. In the normal operating state, the charge of the voltage (Vs + Vo) / 2 is accumulated in the capacitor Cr1, and the charge of the voltage Vs / 2 is stored in the capacitor Cr2. It is assumed that no charge is accumulated in (Cp). Capacitors Cr1 and Cr2 have a sufficiently large capacitance than capacitor Cp.

In the rising period PR of the pulse P1, when the switches SW11 and SW13 are turned on in accordance with the control signals C _SW11 and C _SW13 from the control signal generating circuit 604, the path 1 from the capacitor Cr1 is routed. A current flows through the display electrode capacitor Cp through the switch SW13, the diode D11, and the resonant inductor L1 forming a voltage, the voltage between both ends of the capacitor Cr1 decreases slightly, and the pulse P1 rises. Is formed. When the voltage of the capacitor Cp reaches the peak potential Vp1, the switch SW41 of the clamp circuit 140 is turned on in accordance with the control signal C _SW41 . In addition, no current flows in the direction opposite to the supply current by the diode D11. Thus, the switches SW11 and SW13 are turned off at any timing for a period from reaching the peak voltage until the turn-off timing of the switch SW41. The peak voltage Vp1 is slightly lower than Vs + Vo. In this rising period PR, charges q to Cr _r (Vs + Vo) / 2, that is, electric power, are supplied from the capacitor Cr1 to the capacitor Cp. In the clamp period PCL1, the voltage source Vs + Vo of the clamp circuit 140 clamps the voltage of the capacitor Cp to the voltage Vs + Vo, and the display electrode capacitor Cp to the potential Vs +. Vo). After that, the switch (SW41) is turned off in response to a control signal (C _SW41). In the first falling period (PF1) of the pulse (P1), switch (SW42) according to a control signal (C _SW42) is turned on, the voltage of the pulse (P1), i.e., the capacitor (Cp) is lowered to a voltage (Vs) . In the last falling period PF2 of the subsequent pulse P1, the voltage of the pulse P1, that is, the capacitor Cp, drops to the ground potential GND.

In the rising period PR of the pulse P2, when the switches SW12 and SW14 are turned on in accordance with the control signals C _SW12 and C _SW14 from the control signal generating circuit 604, the path from the capacitor Cr1 is routed. A current flows through the display electrode capacitor Cp through the switch SW14, the diode D12, and the resonant inductor L1 forming two, and the voltage between both ends of the capacitor Cr1 slightly increases, A rise is formed. When the voltage of the capacitor Cp reaches the peak potential Vp1, the switch SW41 of the clamp circuit 140 is turned on in accordance with the control signal C _SW41 . In addition, no current flows in the direction opposite to the supply current by the diode D12. Thus, the switches SW12 and SW14 are turned off at any timing for a period from reaching the peak voltage until the turn-off timing of the switch SW41. In this rising period PR, the charges q to Cr _r (Vs + Vo) / 2, that is, power, are recovered from the capacitor Cp to the capacitor Cr1. In the clamp period PCL1, the voltage source Vs + Vo of the clamp circuit 140 clamps the voltage of the capacitor Cp to the potential Vs + Vo, and the display electrode capacitor Cp is the potential Vs +. Vo). After that, the switch (SW41) is turned off in response to a control signal (C _SW41). In the initial falling period PF1 of the pulse P2, the switch SW42 is turned on in accordance with the control signal _CSW42 , and the voltage of the pulse P2, that is, the capacitor Cp, drops to the voltage Vs. . In the last falling period PF2 of the subsequent pulse P2, the voltage of the pulse P1, that is, the capacitor Cp, drops to the ground potential GND.

In the last falling period PF2 of the pulse P1 to the ground potential GND, when the switches SW21 and SW23 are turned on in accordance with the control signals C _SW21 and C _SW23 , from the display electrode capacitor Cp, A current flows in the capacitor Cr2 through the switch SW23, the diode D21, and the resonant inductor L2 forming the path 1, the voltage between both ends of the capacitor Cr2 decreases slightly, and the end of the pulse P1. Of descent is formed. When the voltage of the capacitor Cp reaches the peak potential Vp3, the switch SW45 of the clamp circuit 140 is turned on in accordance with the control signal C _SW45 . In addition, no current flows in the direction opposite to the supply current by the diode D21. Thus, the switches SW21 and SW23 are turned off at any timing for a period from reaching the peak voltage until the turn-off timing of the switch SW45. The peak voltage Vp3 is slightly higher than the potential GND. In this falling period PF2, the charge q-C _r2 Vs / 2, that is, electric power is supplied from the capacitor Cr2 to the capacitor Cp. In the clamp period PCL2, the ground potential GND of the clamp circuit 140 clamps the voltage of the capacitor Cp to the potential GND (0V), and the display electrode capacitor Cp to the ground potential GND. Keep). After that, the switch (SW45) is turned off in response to a control signal (C _SW45).

In the last falling period PF2 of the pulse P2 to the ground potential GND, when the switches SW22 and SW24 are turned on in accordance with the control signals C _SW22 and C _SW24 , from the display electrode capacitor Cp, A current flows in the capacitor Cr2 through the switch SW24, the diode D22, and the resonant inductor L2 forming the path 2, the voltage between both ends of the capacitor Cr rises slightly, and the end of the pulse P2. Of descent is formed. When the voltage of the capacitor Cp reaches the peak potential Vp3, the switch SW45 of the clamp circuit 140 is turned on in accordance with the control signal C _SW45 . In addition, no current flows in the direction opposite to the supply current by the diode D22. Thus, the switches SW22 and SW24 are turned off at any timing for a period from reaching the peak voltage until the turn-off timing of the switch SW45. This from the capacitor (Cp) in a falling period (PF2) in the capacitor (Cr2) charge _{(q ~ C r2 Vs / 2} ), i.e. the power is recovered. In the clamp period PCL2, the potential GND of the clamp circuit 140 clamps the voltage of the capacitor Cp to the ground potential GND, and the display electrode capacitor Cp to the ground potential GND. Keep it. After that, the switch (SW45) is turned off in response to a control signal (C _SW45).

As described above, the driver control circuit 51 supplies data concerning the display electrodes X and Y associated with the non-lighting cell to the sustain circuits 63 and 67, and the falling period of the initial discharge of the sustain pulse ( In PF1, electrical energy may be supplied to and recovered from the capacitance Cp between the display electrodes X and Y associated with the non-lighting cell. In this case, when the pulse power supply and recovery circuit 130 is provided, the control signal generation circuit 604 is in a sustain period during a low load, that is, a predetermined ratio of the total number of cells of the display electrode, for example, two. The control signals are supplied to the switches SW31 to SW42 so as to apply an applied voltage from the capacitor Cr3 only to the display electrodes of the rows in which more than a quarter of the cells do not emit light, that is, the address discharge is not performed. As a matter of course, the electrical energy may be collectively supplied and recovered from all the lines in the falling period PF1 of the initial discharge of the sustain pulse regardless of the display load. In this case, a pulse power supply and recovery circuit 130 is provided, and a control signal is supplied to the switches SW31 to SW42 so as to apply an applied voltage from the capacitor Cr3 to all the display electrodes. It is assumed that the charge of the voltage Vo / 2 is stored in the capacitor Cr3.

In the initial falling period PF1 of the pulse P1 to the potential Vs, when the switches SW31 and SW33 are turned on in accordance with the control signals C _SW31 and C _SW33 , the path from the display electrode capacitor Cp is increased. A current flows through the capacitor Cr3 through the switch SW33, the diode D31, and the resonant inductor L3 forming one, the voltage between both ends of the capacitor Cr3 decreases slightly, and the initial drop of the pulse P1 occurs. Is formed. When the voltage of the capacitor Cp reaches the peak potential Vp2, the switch SW42 of the clamp circuit 140 is turned on in accordance with the control signal C _SW42 . In addition, no current flows in the direction opposite to the supply current by the diode D31. Thus, the switches SW31 and SW33 are turned off at any timing for a period from reaching the peak voltage until the turn-off timing of the switch SW42. The peak voltage Vp2 is slightly higher than the potential Vs. In this falling period PF1, charges q to Cr _r Vo / 2, that is, electric power, are supplied from the capacitor Cr3 to the capacitor Cp. In the clamp period PCL2, the potential Vs of the clamp circuit 140 clamps the voltage of the capacitor Cp to the potential Vs and maintains the display electrode capacitor Cp at the potential Vs. After that, the switch (SW42) is turned off in response to a control signal (C _SW42).

In the first falling period (PF1) to pulse (P2) the potential (Vs) of, when the switches (SW32 and SW34) turned on in response to a control signal (C _SW32 and C _SW34), from the display electrode capacitor (Cp), the path 2 Current flows in the capacitor Cr3 through the switch SW34, the diode D32, and the resonant inductor L3 forming a voltage, the voltage between both ends of the capacitor Cr3 rises slightly, and the initial drop of the pulse P2 Is formed. When the voltage of the capacitor Cp reaches the peak potential Vp2, the switch SW42 of the clamp circuit 140 is turned on in accordance with the control signal C _SW42 . In addition, no current flows in the direction opposite to the supply current by the diode D32. Thus, the switches SW32 and SW34 are turned off at any timing for a period from reaching the peak voltage until the turn-off timing of the switch SW42. In this falling period PF1, since the capacitor Cp is not discharged, the charges q to Cr _r Vo / 2, that is, power, are recovered from the capacitor Cp to the capacitor Cr3. In the clamp period PCL2, the potential Vs of the clamp circuit 140 clamps the voltage of the capacitor Cp to the potential Vs and maintains the display electrode capacitor Cp at the potential Vs. After that, the switch (SW42) is turned off in response to a control signal (C _SW42).

In the pulse power supply and recovery circuit 110, the switch SW13 and the diode D11 may be realized by one transistor, and the switch SW14 and the diode D12 may be realized by one transistor. Similarly, in the pulse power supply and recovery circuit 120, the switch SW23 and the diode D21 may be realized by one transistor, and the switch SW24 and the diode D22 may be realized by one transistor. . The same applies to the pulse power supply and recovery circuit 130. The diodes D11, D12, D21, D22, D31, and D32 may be omitted. In that case, the turn-off timing of the switch connected to the anode of each diode needs to be the time which reached the peak voltage in the process of each path | route.

The resonant inductor L1 may be provided in series separately in each of the path 1 and the path 2 instead of being provided as a common element in the two paths 1 and 2. The resonant inductor L2 may be provided in series separately in each of the path 1 and the path 2 instead of being provided as a common element in the two paths 1 and 2. The same applies to the pulse power supply and recovery circuit 130. As an alternative configuration, in the pulse power supply and recovery circuits 110, 120, and 130, a part of the inductance of the same value among the inductances of the resonant inductors L1, L2, and L3 may be replaced with one common inductor. As an alternative configuration, instead of the resonant inductors L1, L2 and L3, one common inductor may be provided.

In the pulse power supply and recovery circuit 110, instead of the switches SW13 and SW14, a switching switch in which one terminal is coupled to the capacitor Cp and the other terminal is switched between the path 1 and the path 2 may be provided. The same applies to the pulse power supply and recovery circuits 120 and 130.

As described above, according to the above-described embodiment, power is supplied from the capacitors Cr1 and Cr2 to the capacitor Cp of the display electrode in a pair of pulses, and most of the power is supplied from the capacitors Cp to the capacitors Cr1 and Cr2. Can be recovered. Besides the power consumed in the sustain discharge, some of the power supplied to the display electrodes X and Y can be recovered to the capacitor Cr3. As a result, the power consumption of the display device 10 can be reduced.

In another embodiment, only one or two of the pulse power supply and recovery circuits 110, 120, and 130 may be provided in each of the sustain circuits 63 and 67.

It will be appreciated by those skilled in the art that the present invention can be applied not only to a pair of pulses of an asymmetric waveform but also to a pair of pulses of a normal symmetric waveform.

9 (a) to 9 (f) show examples of waveforms of various pulses to which the pulse power supply and recovery circuit according to the present invention is applicable. As for the pulse of FIG.9 (a), the inclination of a rise is abrupt and the inclination of a fall is gentle. As for the pulse of FIG.9 (b), the inclination of a rise is moderate and the inclination of a fall is urgent. As for the pulse of FIG.9 (c), a raise is a step type. As for the pulse of FIG.9 (d), descending is stepped. In the pulse of Fig. 9E, both the rising and falling steps are stepped. The pulse of Fig. 9F has a fall reaching the opposite polarity, and then rising to the ground potential.

The embodiment described above is merely a typical example of the PDP, the combination of the components of each embodiment, its modifications and variations are apparent to those skilled in the art, those skilled in the art and the principles and claims of the present invention It is apparent that various modifications of the above-described embodiments can be made without departing from the scope of the invention described in the following. For example, the present invention can be applied to electronic paper for displaying characters by accumulating electric charges by application of inorganic EL or voltage.

Claims (10)

A charging and discharging device for charging and discharging a capacitance to be charged and discharged by applying a voltage, A recovery capacitor for recovering electrical energy in which one terminal is coupled to the first power supply via the first switch means and the other terminal is coupled to the second power supply via the second switch means; A first terminal coupled to the other terminal of the recovery capacitor and another terminal coupled to the charge / discharge target capacitance to charge the charge / discharge target capacitance through a resonant inductor when the first switch means is turned on; Means for forming paths, One terminal is coupled to the one terminal of the recovery capacitor, and the other terminal is coupled to the charge / discharge target capacitance to discharge the charge / discharge target capacitance through a resonant inductor when the second switch means is turned on. Second path forming means for recovering electrical energy to the receiving capacitor; A control means for controlling the first and second switch means and the first and second path forming means, The control means changes the potential of the charge / discharge target capacitance from the first potential in the first pulse to the second potential by making the first path forming means active when the first switch means is turned on, Next, the first switch means is turned off, and when the second switch means is turned on, the second path forming means is made active and the potential of the charge / discharge target capacitance is changed to the first pulse and the subsequent waveform. The charging / discharging device, which is changed from the first potential to the second potential in the same second pulse. delete The method of claim 1, The recovery capacitor has a capacity larger than the capacitance to be charged and discharged, and is charged at a voltage equal to half the difference between the potential of the first power supply and the second power supply in a stable state after repeated charging and discharging. Charging and discharging device, characterized in that. The method of claim 1, One terminal of the charge / discharge target capacitance is coupled to the second power supply through a third switch means, and the one terminal of the charge / discharge target capacitance is coupled to the first power supply through a fourth switch means, The control means, after turning on the first switch, turns on the third switch means to clamp the charge / discharge target capacitance to the potential of the second power supply, and after turning on the second switch, the fourth switch means. Charging and discharging device to turn on to clamp the charging and discharging target capacitance to the potential of the second power supply. The method of claim 1, The first power source is a ground potential, and the first and second path forming means each includes rectifying means, and the polarity of the one terminal of the first path forming means and the one terminal of the second path forming means is different from each other. And a polarity of the other terminal of the first path forming means and the other terminal of the second path forming means is a second polarity opposite to the first polarity. A charge and discharge device for charging a charge and discharge target capacitance by applying a voltage, A first recovery capacitor for electrical energy recovery, wherein one terminal is coupled to a first power source via a first switch means and the other terminal is coupled to a second power source via a second switch means; One terminal is coupled to the connection point of the second power supply and the other terminal of the first recovery capacitor, and the other terminal is coupled to the capacitance to be charged and discharged, so that the first switch means is turned on through the resonant inductor. First path forming means for charging a charge / discharge target capacitance; One terminal is coupled to a connection point of the first power supply and the one terminal of the first recovery capacitor, and the other terminal is coupled to the capacitance to be charged and discharged, so that the second switch means is turned on through the resonant inductor. Second path forming means for discharging a charge / discharge target capacitance to recover electrical energy to the first recovery capacitor; A second recovery capacitor for electrical energy recovery, wherein one terminal is coupled to the third power source via the third switch means and the other terminal is coupled to the fourth power source via the fourth switch means; One terminal is coupled to the connection point of the third power supply and the one terminal of the second recovery capacitor, and the other terminal is coupled to the capacitance to be charged and discharged, so that the third switch means is turned on through the resonant inductor. Third path forming means for charging a charge / discharge target capacitance; One terminal is coupled to the connection point of the fourth power supply and the other terminal of the second recovery capacitor, and the other terminal is coupled to the capacitance to be charged and discharged, so that the fourth switch means is turned on through the resonant inductor when the fourth switch means is turned on. Fourth path forming means for discharging the capacitance to be charged and discharged to recover electrical energy to the second recovery capacitor; And said control means for controlling said first, second, third, and fourth switch means and said first, second, third, and fourth path forming means. The method of claim 6, Charge and discharge device, characterized in that the first power supply and the fourth power supply is the same potential. A display device comprising the charging / discharging device according to any one of claims 1 and 3 to 7, And the charge / discharge target capacitance comprises one or more cells constituting a display screen. A plasma display panel for performing charge charging to transfer charges to a cell constituting a screen from a recovery capacitor for recovery of electrical energy and power recovery to transfer charges from the cell to the recovery capacitor, The recovery capacitor having one terminal coupled to a first power source via a first switch means and another terminal coupled to a second power source through a second switch means; A first terminal coupled to the other terminal of the recovery capacitor and another terminal coupled to an electrode for applying a voltage to the cell to charge the cell through a resonant inductor when the first switch means is turned on Means for forming paths, One terminal is coupled to the one terminal of the recovery capacitor, and the other terminal is coupled to an electrode for applying a voltage to the cell, and discharges the cell through a resonant inductor when the second switch means is turned on. Second path forming means for recovering electrical energy to the receiving capacitor; When the first switch means is turned on, the first path forming means is brought into an active state to change from the first potential to the second potential in the first application pulse to the cell, and then the first switch means is changed. The first in a second application pulse that is turned off and that the first application pulse to the cell and the subsequent waveform are the same with the second path forming means active when the second switch means is turned on. The plasma display panel is changed from a potential to the second potential. As a charging / discharging method for charging / discharging cells constituting the screen of a plasma display panel, In the rising period of the first pulse applied to the cell, one terminal of the recovery capacitor is coupled to the first power supply, and the charge and discharge target capacitance is charged from the other terminal of the recovery capacitor through the resonant inductor, In a rising period of a second pulse having the same waveform as the first pulse applied to the cell, coupling the other terminal of the recovery capacitor to a second power source and removing a resonant inductor from the one terminal of the recovery capacitor. Discharge the charge-discharge target capacitance through the charge and discharge method, characterized in that to recover the electrical energy in the recovery capacitor.

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