KR100882834B1 - Thin Film Semiconductor Device and Manufacturing Method Thereof - Google Patents

Abstract

In particular, using the film thickness and the film formation temperature (environmental temperature in the sputter chamber) as the main parameters, the film thickness is adjusted to 100 nm to 500 nm (more preferably 100 nm to 300 nm), and the film formation temperature is adjusted within the range of 25 ° C to 300 ° C, The residual stress is controlled so as to be 300 MPa or more in the direction of increasing the lattice constant in the in-plane direction, and the Mo film 6 is formed on the SiO ₂ film 5, whereby another film for imparting distortion to the silicon thin film is obtained. It is possible to obtain a highly reliable CMOSTFT which realizes that the desired distortion is easily and reliably added to the polysilicon thin films 4a and 4b without adding a step, thereby improving mobility.

Film formation temperature, sputter chamber, residual stress, polysilicon thin film, mobility, CMOSTFT

Description

Thin film semiconductor device and its manufacturing method {THIN FILM SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device and a method of manufacturing the same, and is particularly applicable to a thin film transistor (TFT) used as a data driver, gate driver, and pixel switching element of an active matrix type liquid crystal display device or an EL panel display device. Is a suitable technique.

In recent years, the demand for further high performance of semiconductor devices is increasing, and even in thin film transistors (TFTs), higher mobility has been required for the realization of, for example, sheet computers. As a method of realizing this high mobility, expansion of the crystal grain size of a polysilicon thin film, improvement of crystallinity, improvement of a device structure, etc. are progressing. For improvement of the device structure, it is considered that it is effective to add distortion to the polysilicon thin film on which the channel region is formed, and to form a sidewall that stresses the polysilicon thin film (see Patent Document 1) or on the gate electrode. A method of depositing a film having a stress (see Patent Document 2) has already been proposed.

However, in the method disclosed in Patent Documents 1 and 2, it is necessary to add a step of forming a structure for distorting the polysilicon thin film in a conventional TFT manufacturing process, which makes the manufacturing process complicated and consequently increases the cost. There is a problem that causes.

Patent Document 1: Japanese Patent Application Laid-Open No. 2003-203925

Patent Document 2: Japanese Patent Application Laid-Open No. 2001-60691

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and it is possible to easily and reliably add a desired distortion to a semiconductor thin film without adding an additional step for imparting distortion to the semiconductor thin film, thereby achieving reliability. It is an object to provide this high thin film semiconductor device and its manufacturing method.

The thin film semiconductor device of the present invention includes an insulating substrate, a semiconductor thin film formed by patterning the insulating substrate, and a gate electrode formed by patterning a gate insulating film on the semiconductor thin film, wherein the gate electrode includes the film. The thickness is a value within the range of 100 nm to 500 nm, and has a residual stress of 300 MPa or more in the direction of increasing the lattice constant in the in-plane direction. At this time, the semiconductor thin film is subjected to tensile stress due to the residual stress of the gate electrode, and the lattice constant in the plane direction thereof is increased as compared with a state without the tensile stress.

Here, it is preferable that the said gate electrode becomes the value within the range whose film thickness is 100 nm-300 nm.

The manufacturing method of the thin film semiconductor device by this invention includes the process of pattern-forming a semiconductor thin film on an insulated substrate, and the process of pattern-forming a gate electrode on the said semiconductor thin film through a gate insulating film, The film thickness is adjusted to a value within the range of 100 nm to 500 nm, and the residual stress is formed so as to be 300 MPa or more in the direction of increasing the lattice constant in the in-plane direction, and the tensile stress caused by the residual stress in the semiconductor thin film. Is given, and the lattice constant in the plane direction is controlled to increase in comparison with the state without the tensile stress.

Here, it is preferable to form the said gate electrode so that the film thickness may be adjusted to the value within the range of 100 nm-300 nm, and that the residual stress becomes 300 Mpa or more in the direction which increases a lattice constant in an in-plane direction.

Moreover, the said gate electrode is adjusted to the value within the range of 100 nm-300 nm, and the environmental temperature at the time of film-forming is set to the value within the range of 25 degreeC-300 degreeC, respectively, and the residual stress is a lattice constant in an in-plane direction. It is more preferable to form so that it may become 300 Mpa or more in the direction which enlarges the.

Fig. 1 is a characteristic diagram showing a measurement result obtained by examining the relationship between the film thickness (nm) and the residual stress (MPa) of the formed Mo film.

Fig. 2 is a graph showing measurement results of the relationship between the film thickness (nm) and the Raman peak (/ cm) of a gate electrode made of Mo film in a state in which a gate electrode made of Mo is patterned on a polysilicon thin film. It is also.

Fig. 3 is a characteristic diagram showing a measurement result obtained by examining the relationship between the film thickness (nm) and the residual stress (MPa) of the Mo film formed at each film formation temperature.

Fig. 4A is a characteristic diagram showing a measurement result obtained by examining the relationship between the film thickness (nm) and the mobility (cm ² / V · s) of a gate electrode made of Mo in an n-channel TFT.

Fig. 4B is a characteristic diagram showing a measurement result obtained by examining the relationship between the film thickness (nm) and the mobility (cm ² / V · s) of a gate electrode made of Mo in a p-channel TFT.

5A is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the first embodiment in the order of steps.

FIG. 5B is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the first embodiment in the order of steps. FIG.

Fig. 5C is a schematic cross sectional view showing the CMOSTFT manufacturing method according to the first embodiment in the order of steps.

Fig. 5D is a schematic cross sectional view showing the CMOSTFT manufacturing method according to the first embodiment in the order of steps.

FIG. 5E is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the first embodiment in the order of steps. FIG.

Fig. 5F is a schematic cross sectional view showing the CMOSTFT manufacturing method according to the first embodiment in the order of steps.

Fig. 6A is a schematic cross sectional view showing a CMOSTFT manufacturing method according to a second embodiment in order of process.

6B is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the second embodiment in order of process.

6C is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the second embodiment in order of process.

6D is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the second embodiment in order of process.

6E is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the second embodiment in order of process.

6F is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the second embodiment in order of process.

6G is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the second embodiment in order of process.

Fig. 6H is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the second embodiment in the order of steps.

Fig. 6I is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the second embodiment in the order of steps.

Fig. 7A is a schematic cross sectional view showing a main process diagram of a modification of the method for manufacturing a CMOSTFT according to the second embodiment.

FIG. 7B is a schematic sectional view showing the main process diagram of a modification of the method of manufacturing a CMOSTFT according to the second embodiment. FIG.

8A is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the third embodiment in order of process.

8B is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the third embodiment in order of process.

8C is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the third embodiment in order of process.

8D is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the third embodiment in order of process.

Fig. 8E is a schematic cross sectional view showing the CMOSTFT manufacturing method according to the third embodiment in the order of steps.

8F is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the third embodiment in order of process.

8G is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the third embodiment in order of process.

8H is a schematic cross-sectional view showing the CMOSTFT manufacturing method according to the third embodiment in order of process.

Fig. 8I is a schematic cross sectional view showing the CMOSTFT manufacturing method according to the third embodiment in the order of steps.

9A is a schematic cross-sectional view showing the main steps of a modification of the method of manufacturing a CMOSTFT according to the third embodiment.

9B is a schematic cross-sectional view showing the main steps of a modification of the method of manufacturing a CMOSTFT according to the third embodiment.

Basic gist of the present invention

In manufacturing a TFT, the present inventors do not add a step for applying distortion (distortion for increasing lattice constant in the plane direction of a polysilicon thin film) to a semiconductor thin film, for example, a polysilicon thin film, and forming a gate electrode. It is conceivable to apply distortion to the polysilicon thin film by using only the residual stress of the gate electrode (ie, the residual stress in the direction of increasing the lattice constant in the in-plane direction) by forming the gate electrode. The method was polite.

In general, although the degree is slightly different depending on the film formation conditions, it is known that the high melting point metal film has a strong residual stress, and the degree increases as the film thickness decreases. In view of this, the present inventors use Mo, W, Ti, Nb, Re, and Ru, which are high melting point metals, as the material of the gate electrode, and use the film thickness as a main parameter to form different film forming conditions (film formation described later). Temperature), and the quantitative relationship between the film thickness and the tensile stress on the polysilicon thin film was discussed.

Here, Mo was taken as an example of the high melting point metal, and the relationship between the film thickness (nm) and the residual stress (MPa) of the formed Mo film was investigated. The measurement results are shown in FIG. Thus, it is judged that the film thickness and the residual stress of the Mo film have a substantially linear relationship in which the latter decreases as the former increases.

On the other hand, as a method of measuring the amount of distortion of the formed polysilicon thin film of the gate electrode, a TFT employs a Raman spectroscopy which can be measured from the back surface of the substrate by forming the polysilicon thin film on a transparent insulating substrate such as a glass substrate. did. Then, in the state where a polysilicon thin film is formed on the glass substrate and a gate electrode made of Mo is formed thereon through a gate insulating film, the film thickness (nm) and Raman peak (/ cm) of the gate electrode made of Mo film are formed. Investigate your relationship with The measurement results are shown in FIG. As described above, film forming conditions other than the film thickness (including the film forming temperature described later) are set in the same manner as in the experiment of FIG. Thus, it turns out that the film thickness of a gate electrode and a Raman peak have a relationship which the latter also increases as an electron increases.

Since the Raman peak with a large amount of distortion of the polysilicon thin film due to the residual stress of the gate electrode is shifted to the low wave side, the thinner the thickness of the gate electrode, the more the amount of distortion of the polysilicon thin film. As shown in Fig. 2, the relationship between the film thickness of the gate electrode and the Raman peak is not linear, and as the film thickness increases, the Raman peak approaches a value of about 517 / cm. This means that if the film thickness of the gate electrode is somewhat large, the Raman peak does not fluctuate from about 517 / cm even when the film thickness is changed. Judging from Fig. 2, it is reasonable to consider that the decrease in the Raman peak, that is, the increase in the amount of distortion of the polysilicon thin film is usually about 500 nm or less.

In order to obtain a larger amount of distortion of the polysilicon thin film, the thickness of the gate electrode may be, for example, about 300 nm or less. In addition, it is preferable to make a gate electrode 100 nm or more from a viewpoint of preventing the influence (concern of peeling etc.) by thinning of a gate electrode.

Therefore, it can be seen from FIG. 1 that the residual stress at which the film thickness of the gate electrode made of Mo is about 500 nm or less is about 300 MPa or more. This numerical relationship is considered to be the same also in the above-mentioned high melting metal other than Mo. That is, in order to give a large distortion to a polysilicon thin film by a gate electrode, considering the influence by thinning of the said gate electrode, the gate electrode has a value within the range of 100 nm-500 nm, Preferably it is 100 nm-300 nm. It is good to ensure a residual stress of 300 MPa or more.

By forming the gate electrode under such a film forming condition, a TFT can be realized by providing sufficient distortion to the polysilicon thin film without any other step, thereby obtaining a large mobility.

In addition, when a residual stress of 300 MPa or more caused by the gate electrode is applied to the polysilicon thin film, the wave number of the Raman peak by Raman spectroscopy of the polysilicon thin film is 0.2 to the low wave side with respect to the wave number before the gate electrode is formed. Shift more than / cm.

The main parameter for determining the amount of distortion imparted to the polysilicon thin film is the thickness of the gate electrode, but is a parameter having a particularly large influence on the amount of distortion in addition to the film thickness. The deposition temperature of the metal film of the gate electrode (here, the environmental temperature in the chamber) Is thought to be important. Therefore, in addition to the film thickness of the gate electrode, the film formation temperature was used as a parameter, and the relationship between the film thickness (nm) and the residual stress (MPa) of the Mo film formed at each film formation temperature was investigated. The measurement results are shown in FIG. Thus, it is judged that the lower the film forming temperature, the more the residual stress in the predetermined film thickness tends to be increased. However, even if the film formation temperature is changed, the film thickness and the residual stress of the Mo film maintain a substantially linear relationship in which the latter decreases as the former increases.

In view of the above, in order to obtain a large mobility of the TFT, as an index capable of imparting sufficient distortion to the polysilicon thin film, it is considered that the residual stress of the gate electrode is secured to 300 MPa or more. Therefore, the film forming temperature is added as a parameter of the residual stress, and each film forming temperature shown in Fig. 3 is experimentally proved, and the film forming temperature is in the range of 25 ° C or more and 300 ° C or less, the gate electrode having a film thickness of 100 nm or more and 500 nm or less, Preferably, it adjusts to the value within the range of 100 nm or more and 300 nm or less, and should just ensure the residual stress of 300 Mpa or more in a gate electrode.

In this way, by clarifying the parameters into two types of the film thickness and the deposition temperature of the gate electrode, and adjusting them appropriately within the above ranges, the gate electrode residual stress can be reliably controlled to a desired value of 300 MPa or more in accordance with various deposition environments in more detail. have.

In this case, in the region serving as the channel region of the polysilicon thin film, when the grain size is small, the grain boundary increases, and the residual stress from the gate electrode is alleviated. Therefore, by forming the crystal grain diameter of the site | part which becomes a channel region of a polysilicon thin film large, specifically about 400 nm or more, sufficient distortion of a polysilicon thin film is ensured.

Next, the inventors of the present invention provide the film thickness (nm) and the mobility of the gate electrode made of Mo for each of the n-channel TFT whose source / drain is n-type and the p-channel TFT whose source / drain is p-type. The relationship with (mobility: (cm ² / V · s)) was investigated. The measurement results are shown in Figs. 4A and 4B. As shown in Fig. 4A, in the n-channel TFT, as the film thickness of the gate electrode becomes thinner, specifically, the mobility is improved by being about 500 nm or less. On the other hand, as shown in Fig. 4B, the mobility in the p-channel TFT hardly depends on the film thickness of the gate electrode. In the p-channel TFT, for example, boron (B) used as a p-type impurity is lighter than phosphorus (p) used, for example, as an n-type impurity. If the gate electrode is thin, the gate electrode is ionized when B is ion-implanted. There exists a problem which may penetrate and reach a channel area | region.

Therefore, in view of the above circumstances, in applying the present invention to a CMOS type TFT comprising a p-channel TFT and an n-channel TFT, the gate electrode of the n-channel TFT whose mobility is improved as the thickness of the gate electrode is thinned Is formed to be thinner than that of the p-channel TFT. As a result, the performance can be particularly improved in the n-channel TFT without causing a significant problem in the p-channel TFT.

Specific embodiment to which this invention is applied

EMBODIMENT OF THE INVENTION Hereinafter, the specific embodiment which applied this invention to the structure and manufacturing method of a polysilicon TFT is described in detail, referring drawings. In addition, the structure of a polysilicon TFT is described with the manufacturing method for convenience of description.

(1st embodiment)

5A to 5F show a CMOS polysilicon TFT according to the first embodiment (hereinafter, simply

It is a schematic sectional drawing which shows the manufacturing method of CMOSTFT) in process order.

First, as shown in FIG. 5A, the amorphous silicon thin film 3 is formed by a plasma CVD method through a buffer layer 2 made of SiO ₂ having a thickness of about 400 nm on a transparent insulating substrate, for example, a glass substrate 1. For example, the film is formed to a thickness of about 65 nm. Here, boron (B) is doped in the amorphous silicon thin film 3 by mixing, for example, B ₂ H ₆ gas into the film formation chamber during film formation.

Subsequently, as shown in FIG. 5B, heat treatment is performed at about 550 ° C. for about 2 hours in a nitrogen atmosphere, and dehydrogenation of the amorphous silicon layer 3 is performed. Then, photolithography is performed on the amorphous silicon thin film 3. And dry etching, and are processed into a pair of amorphous silicon thin films 3a and 3b each having a predetermined ribbon pattern.

Next, as shown in Fig. 5C, amorphous silicon thin films 3a and 3b are crystallized by laser annealing. Specifically, for example, Nd: YVO _{4 which is} an energy beam that continuously outputs energy over time, here a solid state laser (DPSS laser) of semiconductor excitation (LD excitation). Using a laser, laser light is irradiated to the amorphous silicon thin films 3a and 3b under the condition of an output of 6.5 W and a scanning speed of 20 cm / sec, and the amorphous silicon layers 3a and 3b are crystallized to form the polysilicon thin films 4a and 4b. Convert to Then, photolithography and dry etching are performed on the polysilicon thin films 4a and 4b of the ribbon pattern and processed into predetermined island patterns, respectively.

Subsequently, as shown in Fig. 5D, a SiO ₂ film 5 is formed on the entire surface with a thickness of 30 nm so as to cover the polysilicon thin films 4a and 4b by plasma CVD. Then, a high melting point metal film serving as a gate electrode is formed on the SiO ₂ film 5 by the sputtering method, and here the Mo film 6 is formed. In particular, the film thickness and film formation temperature (environmental temperature in the sputter chamber) are controlled as main parameters so that the residual stress becomes a predetermined value of 300 MPa or more in the direction of increasing the lattice constant in the in-plane direction. Specifically, the pressure is 2 x 10 ^-3 Torr, the input power (RF power) 3.5 kW, the sputter gas is Ar gas, the flow rate is 20 sccm, the chamber temperature is 25 ° C to 300 ° C, here 175 ° C The Mo film 6 is formed into a film about 100 nm-500 nm (more preferably, 100 nm-300 nm), and about 100 nm here.

Subsequently, as the polysilicon thin film (4a, 4b) the processing by the Mo film 6 and the lithography and dry etching the SiO ₂ film 5 picture such that the respective electrode shape shown in Fig. 5E, SiO ₂ The gate electrodes 8a and 8b made of the Mo film 6 via the gate insulating film 7 made of the film 5 are patterned. As described above, the gate electrodes 8a and 8b are formed by controlling the film thickness and the film formation temperature as the main parameters, and have a residual stress of 300 MPa or more in the direction of increasing the lattice constant in the in-plane direction, here about 630 MPa. have. Due to this residual stress, tensile stress is applied to the polysilicon thin films 4a and 4b at least in the channel region of the polysilicon thin films 4a and 4b which are formation sites of these gate electrodes 8a and 8b. The lattice constant in the direction is increased in comparison with the state without the tensile stress.

Subsequently, as shown in FIG. 5F, a resist mask (not shown) is formed to cover the polysilicon thin film 4a side, and the gate electrode 8b is used as a mask to form the polysilicon thin film 4b. N-type impurities, here phosphorus (p), are ion-implanted on both sides of the gate electrode 8b to form an n-type source / drain 9b. Here, the n-channel TFT 10b in which the gate electrode 8b is formed on the polysilicon thin film 4b through the gate insulating film 7, and the source / drain 9b is formed on both sides of the gate electrode 8b. ) The main configuration is completed.

On the other hand, after removing the resist mask by an incineration process or the like, as shown in Fig. 5F, a resist mask (not shown) is formed so as to cover the polysilicon thin film 4b side, and the gate electrode 8a is formed. Using the mask as a mask, p-type impurities, in this case boron (B), are ion-implanted on both sides of the gate electrode 8a in the polysilicon thin film 4a to form the p-type source / drain 9a. Here, the p-channel TFT 10a in which the gate electrode 8a is formed on the polysilicon thin film 4a through the gate insulating film 7, and the source / drain 9a is formed on both sides of the gate electrode 8a. ) The main configuration is completed.

Thereafter, formation of an interlayer insulating film covering the p-channel TFT 10a and the n-channel TFT 10b, or the formation of contact holes and various wiring layers which are connected to the gate electrodes 8a and 8b and the source / drain 9a and 9b. After this, the CMOSTFT of the present embodiment is completed.

As described above, according to the present embodiment, a desired distortion is easily and reliably provided to the polysilicon thin films 4a and 4b without adding another step for imparting distortion to the polysilicon thin films 4a and 4b. Thus, the mobility can be improved, and a high performance CMOSTFT is realized.

(2nd embodiment)

In this embodiment, the structure and manufacturing method of the CMOSTFT which are almost the same as in the first embodiment are disclosed, but differ in that the film thickness of the gate electrode of the n-channel TFT is formed thinner than that of the p-channel TFT. 6A to 6G are schematic cross-sectional views showing a method for manufacturing a CMOS polysilicon TFT (hereinafter simply referred to as CMOSTFT) according to a second embodiment in the order of steps. In addition, about the structural member etc. which are common in 1st Embodiment, the same code | symbol is written together.

First, as shown in Fig. 6A, the amorphous silicon thin film 3 is formed by a plasma CVD method through a buffer layer 2 made of SiO ₂ having a film thickness of about 400 nm on a transparent insulating substrate, for example, a glass substrate 1. For example, the film is formed to a thickness of about 65 nm. Here, boron (B) is doped in the amorphous silicon thin film 3 by mixing, for example, B ₂ H ₆ gas into the film formation chamber during film formation.

Subsequently, as shown in Fig. 6B, heat treatment is performed at about 550 ° C. for about 2 hours in a nitrogen atmosphere, and dehydrogenation treatment of the amorphous silicon layer 3 is carried out. Lithography and dry etching are performed, and each is processed into a pair of amorphous silicon thin films 3a and 3b of a predetermined ribbon pattern.

Subsequently, as shown in Fig. 6C, amorphous silicon thin films 3a and 3b are crystallized by laser annealing. Specifically, for example, Nd: YVO _{4 which is} an energy beam that continuously outputs energy over time, here a solid state laser (DPSS laser) of semiconductor excitation (LD excitation). Using a laser, laser light is irradiated to the amorphous silicon thin films 3a and 3b under the condition of an output of 6.5 W and a scanning speed of 20 cm / sec, and the amorphous silicon layers 3a and 3b are crystallized to form the polysilicon thin films 4a and 4b. Convert to Then, photolithography and dry etching are performed on the polysilicon thin films 4a and 4b of the ribbon pattern and processed into predetermined island patterns, respectively.

Subsequently, as shown in Fig. 6D, the SiO ₂ film 5 is formed on the entire surface with a film thickness of about 30 nm so as to cover the polysilicon thin films 4a and 4b by the plasma CVD method. Then, a high melting point metal film serving as a gate electrode is formed on the SiO ₂ film 5 by the sputtering method, and here the Mo film 11 is formed. In particular, the film thickness and film formation temperature (environmental temperature in the sputter chamber) are controlled as main parameters so that the residual stress becomes a predetermined value of 300 MPa or more in the direction of increasing the lattice constant in the in-plane direction. Specifically, the pressure is 2 x 10 ^-3 Torr, the input power (RF power) 3.5 kW, the sputter gas is Ar gas, the flow rate is 20 sccm, the chamber temperature is 25 ° C to 300 ° C, here 175 ° C The Mo film 11 is formed into a film about 100 nm-500 nm (more preferably, 100 nm-300 nm), and about 300 nm here.

Subsequently, as shown in Fig. 6E, the Mo film 11 and the SiO ₂ film 5 are processed by photolithography and dry etching so as to have an electrode shape on the polysilicon thin films 4a and 4b, respectively.

Subsequently, as shown in Fig. 6F, a resist mask 13 covering only the polysilicon thin film 4a side on the left side in the drawing is formed, and only the Mo film 11 on the polysilicon thin film 4b is dry-etched, The Mo film 11 is thinned to a thickness of about 100 nm. In this state, the gate electrode 12a having a thickness of about 300 nm made of Mo via the gate insulating film 7 is formed on the polysilicon thin film 4a, and the Mo via the gate insulating film 7 is formed on the polysilicon thin film 4b. Gate electrodes 12b each having a film thickness of about 100 nm are formed.

As described above, the gate electrodes 12a and 12b are formed by controlling the film thickness and the film formation temperature as main parameters, and the residual stress of 300 MPa or more in the direction of increasing the lattice constant in the in-plane direction, in this case, the gate electrode. (12a) is about 470 MPa, and the gate electrode 12b is about 630 MPa with the effect by the said thinning being added. Due to this residual stress, tensile stress is applied to the polysilicon thin films 4a and 4b at least in the channel region of the polysilicon thin films 4a and 4b, which are the formation sites of the gate electrodes 12a and 12b. The lattice constant of is increased as compared with a state without tensile stress.

6G, the polysilicon thin film 4b using the resist mask 13 as an ion implantation mask as it is, and using the gate electrode 12b as a mask on the polysilicon thin film 4b side. N-type impurities, here phosphorus (p), are ion-implanted on both sides of the gate electrode 12b in to form an n-type source / drain 9b. Here, the gate electrode 12b is formed on the polysilicon thin film 4b through the gate insulating film 7, and the n-channel TFT 14b having the source / drain 9b formed on both sides of the gate electrode 12b. The main configuration is completed.

On the other hand, after the resist mask 13 is removed by a painting process or the like, as shown in Fig. 6H, the resist mask 15 is formed so as to cover the polysilicon thin film 4b side, and the polysilicon thin film 4a side Using the gate electrode 12a as a mask, p-type impurities, boron (B), are ion-implanted on both sides of the gate electrode 12a in the polysilicon thin film 4a, and the p-type source / drain 9a is implanted. ). Then, by removing the resist mask 15 by painting, etc., as shown in Fig. 6I, the gate electrode 12a is formed on the polysilicon thin film 4a through the gate insulating film 7, and the gate electrode 12a is formed. The main configuration of the p-channel TFT 14a in which the source / drain 9a is formed on both sides of is completed.

Thereafter, formation of an interlayer insulating film covering the p-channel TFT 14a and the n-channel TFT 14b, or the formation of contact holes and various wiring layers conducting to the gate electrodes 12a and 12b and the source / drain 9a and 9b. After this, the CMOSTFT of the present embodiment is completed.

As described above, according to the present embodiment, desired distortion can be easily and reliably added to the polysilicon thin films 4a and 4b without adding another step for imparting distortion to the polysilicon thin films 4a and 4b. In particular, the mobility of the n-channel TFT 14b can be improved, and a high-performance CMOSTFT is realized.

(Variation)

Here, the modification of 2nd Embodiment is demonstrated.

7A and 7B are schematic cross-sectional views showing main steps of the present modification.

First, the same process as that in Figs. 6A to 6E is performed.

Subsequently, as shown in Fig. 7A, a resist mask 13 covering only the polysilicon thin film 4a side on the left side in the drawing is formed, and the Mo film 11 is used as a mask on the polysilicon thin film 4b side. N-type impurities, here phosphorus (p), are ion-implanted on both sides of the Mo film 11 in the polysilicon thin film 4b to form an n-type source / drain 9b.

Subsequently, as shown in Fig. 7B, the resist mask 13 is used as an ion implantation mask as it is, and only the Mo film 11 on the polysilicon thin film 4b is dry-etched, and the Mo film 11 is film-thick. It is thinned down to about 100 nm. In this state, a gate electrode 12a having a thickness of about 300 nm made of Mo through the gate insulating film 7 is formed on the polysilicon thin film 4a, and Mo is formed through the gate insulating film 7 on the polysilicon thin film 4b. Gate electrodes 12b each having a film thickness of about 100 nm are formed.

Thereafter, after performing the same steps as in FIGS. 6H and 6I, an interlayer insulating film covering the p-channel TFT 14a and the n-channel TFT 14b is formed, or the gate electrodes 12a and 12b and the source / drain ( The CMOSTFT of this modification is completed by forming contact holes and various wiring layers which are in contact with 9a and 9b).

As described above, according to the present embodiment, a desired distortion is easily and reliably provided to the polysilicon thin films 4a and 4b without adding another step for imparting distortion to the polysilicon thin films 4a and 4b. In particular, the mobility of the n-channel TFT 14b can be improved, and a high-performance CMOSTFT is realized.

In this modification, on the n-channel TFT 14b side, before the Mo film 11 is still processed into the gate electrode 12b, a thick (here, about 300 nm) Mo film 11 is used as a mask. P is implanted. In the n-channel TFT, the problem of impurity protrusion at the time of ion implantation is not as serious as that of the p-channel TFT, but since the gate electrode 12b is as thin as about 100 nm, there is a concern that impurity protrusion may be a problem when the gate electrode 12b is called a mask. It cannot be denied. Thus, as in the present modification, by implanting ions as a mask while still in the state of the thick Mo film 11, the n-channel TFT 14b is not increased or complicated, and there is no fear of impurity protrusion. Can be formed.

(Third embodiment)

In the present embodiment, the structure and manufacturing method of the CMOSTFT which are almost the same as those of the second embodiment are disclosed, but the gate electrode of the p-channel TFT is formed by making the film thickness of the gate electrode of the n-channel TFT thinner than that of the p-channel TFT. It differs in the point of forming in a layer. 8A to 8G are schematic cross-sectional views showing a method for manufacturing a CMOS polysilicon TFT (hereinafter simply referred to as CMOSTFT) according to a third embodiment in the order of steps. In addition, the same code | symbol is attached | subjected about the structural member etc. which are common in 2nd Embodiment.

First, as shown in Fig. 8A, an amorphous silicon thin film 3 is formed on a transparent insulating substrate, for example, a glass substrate 1, by a plasma CVD method through a buffer layer 2 made of SiO ₂ having a film thickness of about 400 nm. ) Is formed, for example, at a thickness of about 65 nm. Here, boron (B) is doped in the amorphous silicon thin film 3 by mixing, for example, B ₂ H ₆ gas into the film formation chamber during film formation.

Subsequently, as shown in FIG. 8B, heat treatment is performed at about 550 ° C. for about 2 hours in a nitrogen atmosphere and dehydrogenation of the amorphous silicon layer 3 is carried out. Then, the amorphous silicon thin film 3 is subjected to photolithography and the like. Dry etching is performed and processed into a pair of amorphous silicon thin films 3a and 3b of predetermined ribbon patterns, respectively.

Subsequently, as shown in Fig. 8C, amorphous silicon thin films 3a and 3b are crystallized by laser annealing. Specifically, for example, Nd: YVO _{4 which is} an energy beam that continuously outputs energy over time, here a solid state laser (DPSS laser) of semiconductor excitation (LD excitation). Using a laser, laser light is irradiated to the amorphous silicon thin films 3a and 3b under the condition of an output of 6.5 W and a scanning speed of 20 cm / sec, and the amorphous silicon layers 3a and 3b are crystallized to form the polysilicon thin films 4a and 4b. Convert to Then, photolithography and dry etching are performed on the polysilicon thin films 4a and 4b of the ribbon pattern and processed into predetermined island patterns, respectively.

Subsequently, as shown in Fig. 8D, the SiO ₂ film 5 is formed on the entire surface with a thickness of about 30 nm so as to cover the polysilicon thin films 4a and 4b by plasma CVD. Then, a high melting point metal film serving as a gate electrode on the SiO ₂ film 5, in this case, a Mo film 21 and a Ti film 22, is laminated by a sputtering method. In particular, the film thickness and film formation temperature (environmental temperature in the sputter chamber) are controlled as main parameters so that the residual stress becomes a predetermined value of 300 MPa or more in the direction of increasing the lattice constant in the in-plane direction.

Specifically, for the Mo film 21, a pressure of 2 × 10 ⁻³ Torr, an input power (RF power) of 3.5 kW, a sputter gas as Ar gas, a flow rate of 20 sccm, a chamber temperature of 25 ° C. to 300 ° C., here Under the conditions of about 175 ° C, the Mo film 21 is formed here at about 100 nm so that the thickness of the laminated film of the Mo film 21 and the Ti film 22 is 100 nm to 500 nm (more preferably, 100 nm to 300 nm). do.

On the other hand, with respect to the Ti film 22, a pressure of 2 × 10 ⁻³ Torr, an input power (DC power) of 2.OkW, a sputter gas as Ar gas, a flow rate of 125 sccm, a chamber temperature of 25 ° C. to 300 ° C., here 125 The Ti film 22 is formed here about 200 nm so that the thickness of the laminated film of the Mo film 21 and the Ti film 22 will be 100 nm-500 nm (more preferably, 100 nm-300 nm) on condition of about degreeC.

Subsequently, as shown in Fig. 8E, the Ti film 22, Mo film 21 and SiO ₂ film 5 are subjected to photolithography and dry etching so as to have an electrode shape on the polysilicon thin films 4a and 4b, respectively. By processing.

Subsequently, as shown in Fig. 8F, a resist mask 13 covering only the side of the polysilicon thin film 4a on the left side of the figure is formed, and the Ti film using the Mo film 21 on the polysilicon thin film 4b as an etching stopper. Only (22) is dry-etched and only the said Mo film 21 is left. In this case, since the Mo film 21 is used as an etching stopper by using the difference between the etching rates of Mo and Ti, for example, compared to the case where the single layer high melting point metal film is dry-etched to control the film thickness, It is possible to achieve a desired film thickness (here, about 100 nm) leaving only the Mo film 21.

In this state, a gate electrode 23a having a thickness of about 300 nm formed by stacking Mo and Ti via the gate insulating film 7 on the polysilicon thin film 4a is formed on the polysilicon thin film 4b. ), Gate electrodes 23b each having a thickness of about 100 nm made of Mo are formed.

As described above, the gate electrodes 23a and 23b are formed by controlling the film thickness and the film formation temperature as main parameters, and the residual stress of 300 MPa or more in the direction of increasing the lattice constant in the in-plane direction, in particular the gate electrode The effect of the above thinning is added to 23b to be about 630 MPa. Due to this residual stress, tensile stress is applied to the polysilicon thin films 4a and 4b at least in the channel region of the polysilicon thin films 4a and 4b, which are the formation sites of the gate electrodes 23a and 23b. The lattice constant of is increased as compared with a state without tensile stress.

Subsequently, as shown in Fig. 8G, the resist mask 13 is used as an ion implantation mask as it is, and the polysilicon thin film 4b using the gate electrode 23b as a mask on the polysilicon thin film 4b side. N-type impurities, here phosphorus (p), are ion-implanted on both sides of the gate electrode 23b in to form an n-type source / drain 9b. Here, the gate electrode 12b is formed on the polysilicon thin film 4b through the gate insulating film 7, and the n-channel TFT 24b having the source / drain 9b formed on both sides of the gate electrode 12b. The main configuration is completed.

On the other hand, after removing the resist mask 13 by an incineration process or the like, as shown in Fig. 8H, a resist mask 15 is formed to cover the polysilicon thin film 4b side, and the polysilicon thin film 4a side is formed. By using the gate electrode 23a as a mask, p-type impurities, boron (B) are ion-implanted on both sides of the gate electrode 23a in the polysilicon thin film 4a, and the p-type source / drain 9a is implanted. ). Then, by removing the resist mask 15 by painting, etc., as shown in Fig. 8I, the gate electrode 23a is formed on the polysilicon thin film 4a through the gate insulating film 7, and the gate electrode 23a is formed. The main configuration of the p-channel TFT 24a in which the source / drain 9a is formed on both sides of is completed.

Thereafter, formation of an interlayer insulating film covering the p-channel TFT 24a and the n-channel TFT 24b, or the formation of contact holes and various wiring layers conducting to the gate electrodes 23a and 23b and the source / drain 9a and 9b. The CMOSTFT of the present embodiment is completed through the above.

As described above, according to the present embodiment, a desired distortion is easily and reliably provided to the polysilicon thin films 4a and 4b without adding another step for imparting distortion to the polysilicon thin films 4a and 4b. In particular, the mobility of the n-channel TFT 24b can be improved, and a high-performance CMOSTFT is realized.

(Variation)

Here, the modification of 3rd Embodiment is demonstrated.

9A and 9B are schematic cross-sectional views showing main steps of the present modification.

First, the manufacturing process as shown in Figs. 8A to 8E is performed.

Subsequently, as shown in Fig. 9A, a resist mask 13 covering only the polysilicon thin film 4a side on the left side of the figure is formed, and the Ti film 22 and the Mo film 21 on the polysilicon thin film 4b side. ) As a mask, n-type impurities, here phosphorus (P), are ion-implanted on both sides of the Mo film 11 in the polysilicon thin film 4b to form an n-type source / drain 9b.

Subsequently, as shown in FIG. 9B, the resist mask 13 is used as an ion implantation mask as it is, and only the Ti film 22 is dry-etched using the Mo film 21 on the polysilicon thin film 4b as an etching stopper. Only the Mo film 21 is left. In this case, since the Mo film 21 is used as an etching stopper by using the difference between the etching rates of Mo and Ti, for example, compared to the case where a single layer high-melting metal film is dry-etched to control the film thickness, It is possible to achieve the desired film thickness (here, about 100 nm) which left only the Mo film 21 easily.

In this state, a gate electrode 23a having a thickness of about 300 nm formed by laminating Mo and Ti via the gate insulating film 7 on the polysilicon thin film 4a is formed on the polysilicon thin film 4b. Gate electrodes 23b each having a film thickness of about 100 nm made of Mo via a thin film are formed.

Thereafter, after performing the same steps as in FIGS. 6H and 6I, an interlayer insulating film is formed to cover the p-channel TFT 24a and the n-channel TFT 24b, or the gate electrodes 23a and 23b and the source / drain ( The CMOSTFT of this modification is completed through the formation of contact holes and various wiring layers which are connected to 9a and 9b).

As described above, according to the present embodiment, a desired distortion is easily and reliably provided to the polysilicon thin films 4a and 4b without adding another step for imparting distortion to the polysilicon thin films 4a and 4b. In particular, the mobility of the n-channel TFT 24b can be improved, and a high-performance CMOSTFT is realized.

In the present modification, on the n-channel TFT 24b side, before the Ti film 22 is etched away yet to form the gate electrode 23b, the thick (here about 300 nm) Ti film 22 and P is ion implanted using the Mo film 21 as a mask. In the n-channel TFT, the problem of impurity protruding at the time of ion implantation to about the p-channel TFT is not serious. However, since the gate electrode 23b is as thin as about 100 nm, the impurity protruding may be a problem when the gate electrode 23b is used as a mask. Cannot be denied. Thus, as in the present modification, the ion implantation is carried out in the state of the thick Ti film 22 and the Mo film 21 as a mask to thereby increase or decrease the number of steps, without fear of impurity protrusion. The n-channel TFT 12b can be formed.

In addition, this invention is not limited to the said, 1st-3rd embodiment and various modified examples. For example, in the second and third embodiments and these modifications, the film thickness of the gate electrode of the p-channel TFT may be made thinner than that of the gate electrode of the n-channel TFT (that is, in this case) 6A to 6I, 7A, 7B, 8A to 8I, 9A, and 9B, the left and right illustrations are reversed). In particular, when the film thickness of the gate electrode of the p-channel TFT is made thinner than the film thickness of the gate electrode of the n-channel TFT, corresponding to the modification examples of FIGS. 7A, 7B, 9A, and 9B, the p-channel TFT The problem of impurity protrusion at the time of ion implantation is serious. In this case, by implanting ions in a state where a thick high melting point metal film (Mo film or Mo film and Ti film) is formed in the shape of an electrode, the p-channel TFT is formed without increasing or complicated the number of steps and fear of impurity protrusion. Can be formed.

According to the present invention, a highly reliable thin film semiconductor device is realized that realizes that the semiconductor thin film is easily and reliably provided with the desired distortion to improve the mobility without adding other steps for imparting distortion. .

Claims (19)

With insulation board, A semiconductor thin film formed by patterning on the insulating substrate; A gate electrode formed on the semiconductor thin film through a gate insulating film; The said gate electrode is the value in the range whose film thickness is 100 nm-500 nm, the film thickness of the gate electrode of the n-channel TFT is formed thinner than the film thickness of the gate electrode of the p-channel TFT, And a residual stress of 300 MPa or more and 630 MPa or less in the direction of increasing the lattice constant in the in-plane direction of the gate electrode. The CMOSTFT according to claim 1, wherein the gate electrode has a value within a range of 100 nm to 300 nm. The CMOSTFT according to claim 2, wherein the semiconductor thin film is formed of a silicon film having a crystal grain size of at least 400 nm in at least the channel region thereof. The said semiconductor thin film is a silicon film, The wave number of the Raman peak by the Raman scattering method in the channel area is 515 / cm or more and 517 / cm or less, The said semiconductor thin film of Claim 2 characterized by the above-mentioned. CMOSTFT. 3. The semiconductor thin film according to claim 2, wherein the semiconductor thin film is made of a silicon film, and the wave number of the Raman peak by Raman spectroscopy in at least the channel region is 0.2 / lower to the low wave side than the wave number before the gate electrode is formed. It is shifted more than cm / 2.0 or less, CMOSTFT characterized by the above-mentioned. 3. The gate electrode of claim 2, wherein the gate electrode is a metal selected from a metal group of Mo, W, Ti, Nb, Re, and Ru, an alloy of a plurality of metals selected from the metal group, or a plurality selected from the metal group. CMOSTFT comprising a laminated structure of a metal. The semiconductor device according to claim 2, further comprising a pair of said semiconductor thin films, each of said gate electrodes being formed on each of said semiconductor thin films via said gate insulating film, and said one of said gate electrodes being thinner than said other gate electrode. CMOSTFT which is made. 8. The CMOSTFT according to claim 7, wherein said other gate electrode is formed in a multilayer than said one said gate electrode. Pattern-forming a semiconductor thin film on an insulating substrate, Patterning a gate electrode on the semiconductor thin film through a gate insulating film, The gate electrode is adjusted to a value within the range of 100 nm to 500 nm, the film thickness of the gate electrode of the n-channel TFT is formed thinner than the film thickness of the gate electrode of the p-channel TFT, The residual stress is formed so as to be 300 MPa or more and 630 MPa or less in the direction of increasing the lattice constant in the in-plane direction, and the tensile stress caused by the residual stress is applied to the semiconductor thin film, and the lattice constant in the plane direction is the tensile stress. The manufacturing method of the CMOSTFT characterized by controlling in the state which increased compared with the absence. 10. The method according to claim 9, wherein the gate electrode is formed so as to have a thickness within a range of 100 nm to 300 nm so that the residual stress is 300 MPa or more and 630 MPa or less in the direction of increasing the lattice constant in the in-plane direction. The manufacturing method of the CMOSTFT characterized by the above-mentioned. The said gate electrode is each adjusted to the film thickness in the value of the range of 100 nm-300 nm, and the environmental temperature at the time of film formation is adjusted to the value in the range of 25 degreeC-300 degreeC, respectively, and the residual stress is in-plane direction. And forming a lattice constant so as to be 300 MPa or more and 630 MPa or less in the direction of increasing the lattice constant. 12. The method of claim 11, wherein after forming the semiconductor thin film in an amorphous state on the insulating substrate, the semiconductor thin film is irradiated with laser light to crystallize the semiconductor thin film. 12. The method for manufacturing a CMOSTFT according to claim 11, wherein the semiconductor thin film is a silicon film, and at least the crystal grain size in the channel region is 400 nm or more. The method of claim 11, wherein the gate electrode is a metal selected from the group of metals of Mo, W, Ti, Nb, Re, and Ru, an alloy of a plurality of metals selected from the metal group, or a plurality selected from the metal group. The manufacturing method of the CMOSTFT characterized by forming with the material containing the laminated structure of the metal. The semiconductor device of claim 11, wherein a pair of the semiconductor thin films are simultaneously formed on the insulating substrate, A method for manufacturing a CMOSTFT, wherein the gate electrodes are formed on the semiconductor thin films so that one gate electrode becomes thinner than the other gate electrode through a gate insulating film. The manufacturing method of the CMOSTFT according to claim 15, wherein the gate electrodes are simultaneously formed in the film thickness of the other gate electrode, and only the one gate electrode is etched to form a thin film. The said one gate electrode of Claim 15 after forming each said gate electrode simultaneously in the film thickness of the said other said gate electrode, and introduce | transducing an impurity into the said semiconductor thin film formed of the said one said gate electrode, A method of manufacturing a CMOS TFT comprising etching a bay and processing it thinly. The said gate electrode is laminated | stacked and simultaneously formed the several metal layer so that it may become the film thickness of the said other said gate electrode, and the said at least uppermost metal layer is etched only with respect to the said one gate electrode. And processing said one said gate electrode thinly. The semiconductor device according to claim 15, wherein a plurality of metal layers are laminated and formed simultaneously so as to have a thickness of the other gate electrode, and impurities are introduced into the semiconductor thin film formed of the one gate electrode. And etching the at least uppermost metal layer with respect to only the one gate electrode to process the one gate electrode thinly.

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