KR100882986B1 - Image sensor and manufacturing method - Google Patents

Abstract

An image sensor and a manufacturing method thereof are provided to remove a carrier inside a photodiode in a reset operation by applying a strong reverse bias to an upper surface of the photo diode. A wiring(150) and a readout circuit(120) are formed in a first substrate(100). An image sensor(210) is formed in the upper side of the readout circuit. The image sensor is formed inside a crystalline semiconductor layer. A reverse bias is applied to the upper side of the image sensor in a reset operation. The reverse bias is -3V or -5V. The readout circuit includes a first conductive connection region(147) and an electric junction region(140).

Description

Image sensor and method for manufacturing

Embodiments relate to an image sensor and a manufacturing method thereof.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is classified into a charge coupled device (CCD) and a CMOS image sensor (CIS).

In the prior art, a photodiode is formed on a substrate by ion implantation. However, as the size of the photodiode gradually decreases for the purpose of increasing the number of pixels without increasing the chip size, the image quality decreases due to the reduction of the area of the light receiver.

In addition, since the stack height is not reduced as much as the area of the light receiving unit is reduced, the number of photons incident on the light receiving unit is also decreased due to diffraction of light called an airy disk.

One alternative to overcome this is to deposit photodiodes with amorphous Si, or read-out circuitry using wafer-to-wafer bonding such as silicon substrates. And photodiodes are formed on the lead-out circuit (hereinafter referred to as "three-dimensional image sensor"). The photodiode and lead-out circuit are connected via a metal line.

However, according to the related art, the ground electrode is simply grounded to the upper electrode connected to the photodiode. The ground current does not effectively reset the excess electrons or the excess holes generated in the photodiode. Dark Current) or Reset Noise is occurring.

Meanwhile, according to the related art, when the surface voltage of the photodiode is lowered by light, the surface voltage of the voltage sensing unit is also lowered at the same time. After the transfer transistor Tx is opened and closed, the source and drain voltages of the transfer transistor become equal and the voltage difference between the drains is amplified through the drive transistor. However, according to the related art, since both the source and the drain of both ends of the transfer transistor are doped with a high concentration N type, there is a problem in that charge sharing occurs. When charge sharing occurs, the sensitivity of the output image is lowered and image errors may occur.

In addition, according to the related art, a dark current is generated between the photodiode and the lead-out circuit and the photocharge is not smoothly moved, and saturation and sensitivity are decreased.

Embodiments provide an image sensor capable of preventing reset noise or dark current while increasing a fill factor and a method of manufacturing the same.

In addition, the embodiment is to provide an image sensor and a method of manufacturing the same that can increase the charge factor (Charge Sharing) does not occur.

In addition, the embodiment of the present invention provides an image sensor capable of minimizing dark current sources and preventing saturation and degradation of sensitivity by creating a smooth movement path of photo charge between the photodiode and the lead-out circuit. To provide a manufacturing method.

An image sensor according to an embodiment includes a first substrate on which wiring and a readout circuitry are formed; And an image sensing unit formed on an upper side of the readout circuit, wherein a reverse bias is applied to the upper side of the photodiode.

In addition, the manufacturing method of the image sensor according to the embodiment comprises the steps of forming a wiring and a lead out circuit on the first substrate; And forming an image sensing unit on the wiring, wherein forming the lead-out circuit of the first substrate includes forming an electrical junction region on the first substrate. Forming an electrical junction region may include forming a first conductivity type ion implantation region in the first substrate; And forming a second conductivity type ion implantation region on the first conductivity type ion implantation region.

In addition, the image sensor according to the embodiment includes a first substrate having a wiring and a lead-out circuit; And an image sensing unit formed on the first substrate while being electrically connected to the wiring, wherein the first substrate is electrically conductive in a second conductivity type, and the readout circuit includes: a transistor formed on the first substrate; And an electrical junction region formed at one side of the transistor.

According to the image sensor and the method of manufacturing the same according to the embodiment, unlike the conventional technology applying a ground (ground) on the upper surface of the photodiode by applying a strong reverse bias (carrier) in the photodiode region during the reset operation of the image sensor By removing the carriers more effectively, it is possible to prevent reset noise or dark current.

In addition, according to the embodiment, the device may be designed such that there is a potential difference between the source / drain across the transistor Tx, thereby enabling full dumping of the photo charge. Accordingly, as the photo charge generated in the photodiode is dumped into the floating diffusion region, sensitivity to the output image may be increased.

In addition, according to the embodiment, the charge connection region is formed between the photodiode and the lead-out circuit to create a smooth movement path of the photo charge, thereby minimizing the dark current source, and reducing saturation and sensitivity. You can prevent it.

Hereinafter, an image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.

The present invention is not limited to the CMOS image sensor, and can be applied to all image sensors requiring a photodiode.

(First embodiment)

1 is a cross-sectional view of an image sensor according to a first embodiment.

The image sensor according to the first embodiment may include a first substrate 100 having a wiring 150 and a readout circuit 120 formed thereon; And an image sensing unit 210 formed above the readout circuit 120. The image sensing unit 210 may be a photodiode 210, but is not limited thereto and may be a photogate, a combination of a photodiode and a photogate, and the like.

In some embodiments, the photodiode 210 is formed on the crystalline semiconductor layer, but is not limited thereto.

The lead-out circuit 120 of the first substrate 100 may include an electrical junction region 140 formed on the first substrate 100; And a first conductivity type connection region 147 formed on the electrical junction region to be connected to the wiring 150.

In the first embodiment, the photodiode 210 is formed on a crystalline semiconductor layer 210a (see FIG. 3). Thus, according to the first embodiment, the image sensing unit adopts a three-dimensional image sensor positioned above the readout circuit to increase the fill factor while forming the image sensing unit in the crystalline semiconductor layer to prevent defects in the image sensing unit. Can be.

In addition, according to the image sensor and the method of manufacturing the same according to the embodiment, unlike the prior art simply applying a ground (ground) to the upper surface of the photodiode, by applying a strong reverse bias to the upper surface of the photodiode of the image sensor The reset noise and dark current may be prevented by more effectively removing carriers in the photodiode region during the reset operation.

That is, according to the embodiment, a reverse bias is applied to the top surface of the photodiode to strongly induce an electric field applied to the reset transistor when the photodiode is reset, thereby facilitating the reset of the surplus electrons or the surplus holes, and thus the reset noise. Nose) or dark current can be prevented.

V _GND [V] Distance of depletion @ edge of PD [um] 0.0 0.21 -0.3 0.158 -0.5 0.147

Table 1 is a table showing the effect of applying a reverse bias (reverse bias) to the photodiode.

That is, when ground is simply applied to the upper surface of the photodiode as in the prior art (0 V), the distance from the photodiode lower edge to the depleted portion is about 0.21 mu m.

However, as in the embodiment, when 0.3 V is applied to the photodiode, the distance from the bottom edge of the photodiode to the depleted position is about 0.158 μm, and when 0.5 V is applied to the photodiode, the distance from the lower edge of the photodiode is decreased. It can be seen that the distance to the plunged area is about 0.147 μm, thereby making the depleted area wider.

When applying a strong reverse bias to the ground of the photodiode image side, as a result, an embodiment, a reset (Reset) operation when (Tx = on, Rx = on ), the voltage (voltage) difference between the photodiode V _GND + Vdd Since it can be enlarged, an electric field is formed large. This electric field causes a strong attraction of the carrier.

Accordingly, when a strong reverse bias is applied to the ground above the photodiode as in the embodiment, a strong reset of the electric field applied to the reset transistor when the photodiode is reset causes easy reset of the surplus electrons or the excess hole, thereby resetting the reset noise. Nose) and dark current can be prevented, and the effect of increasing the width of depletion in the photodiode region can also be obtained.

Next, according to the embodiment, the device may be designed such that there is a potential difference between the source and the drain across the transistor Tx, thereby enabling full dumping of the photo charge. Accordingly, as the photo charge generated in the photodiode is dumped into the floating diffusion region, the output image sensitivity may be increased.

That is, in the first exemplary embodiment, as shown in FIG. 1, an electrical junction region 140 is formed in the first substrate 100 on which the readout circuit 120 is formed, so that the source / drain between the both ends of the transistor Tx 121 is formed. The voltage difference allows the complete dumping of the photocharge. The readout circuit 120 may include a transfer transistor (Tx) 121, a reset transistor (Rx) 123, a drive transistor (Dx) 125, and a select transistor (Sx) 127.

Hereinafter, the dumping structure of the photocharge of the first embodiment will be described in detail.

In the first embodiment, the electrical bonding region 140 may include a first conductivity type ion implantation layer 143 formed on the second conductivity type well 141 or the second conductivity type epitaxial layer (not shown), and the first conductivity type. A second conductivity type ion implantation layer 145 formed on the ion implantation layer 143 may be included. For example, the electrical junction region 140 may be a PN junction or a PNP junction, but is not limited thereto.

Unlike the floating diffusion (FD) 131 node, which is an N + function, the P / N / P section 140, which is an electrical junction region 140, does not transmit all of the applied voltages and pinches off at a predetermined voltage. -off) This voltage is called a pinning voltage and the pinning voltage depends on the P0 145 and N- (143) doping concentrations.

Specifically, the electrons generated by the photodiode 210 are moved to the PNP caption 140 and are transferred to the FD 131 node when the transfer transistor (Tx) 121 is turned on to be converted into a voltage.

Since the maximum voltage value of the P0 / N- / P- caption 140 becomes pinning voltage and the maximum voltage value of the node of the FD 131 becomes Vdd-Rx Vth (threshold voltage), it is charged due to the potential difference between both ends of the Tx (131). Electrons generated from the photodiode 210 on the chip without charge sharing may be fully dumped to the FD 131 node.

That is, according to the embodiment, the reason why the P0 / N- / Pwell junction, rather than the N + / Pwell junction, is formed in the silicon sub (Si-Sub), which is the first substrate 100, is P0 / N− during the 4-Tr APS Reset operation. In the / Pwell junction, + voltage is applied to N- (143) and ground voltage is applied to P0 (145) and Pwell 141. Therefore, P0 / N- / Pwell double junction is equal to Pinch- as in BJT structure. Off occurs. This is called pinning voltage. Therefore, a voltage difference is generated in the source / drain at both ends of the Tx 121, thereby preventing the charge sharing phenomenon during the Tx On / Off operation.

Therefore, unlike the case where the photodiode is connected by N + junction as in the prior art, the first embodiment can avoid problems such as degradation of saturation and degradation of sensitivity.

Next, according to the first embodiment, the first conductive connection region 147 is formed between the photodiode and the lead-out circuit to make a smooth moving path of the photo charge, thereby minimizing the dark current source, Deterioration of saturation and degradation of sensitivity can be prevented.

To this end, the first embodiment may form a first conductivity type connection region 147 for ohmic contact on the surface of the P0 / N- / P- cushion 140. Meanwhile, the width of the first conductive connection region 147 may be minimized in order to minimize the first conductive connection region 147 from becoming a leakage source. This can contribute to reducing the dark current of the three-dimensional image sensor.

That is, as in the first embodiment, the reason for locally N + doping only to the contact forming part is to facilitate the formation of ohmic contact while minimizing the dark signal. When N + Doping the entire Tx Source part, the dark signal may increase due to the substrate surface dangling bond.

Unexplained reference numerals among the reference numerals of FIG. 1 will be described in the following manufacturing method.

Hereinafter, a method of manufacturing the image sensor according to the first embodiment will be described with reference to FIGS. 2 to 6.

First, as shown in FIG. 2, the first substrate 100 having the wiring 150 and the readout circuit 120 is prepared. For example, the isolation layer 110 is formed on the second conductive first substrate 100 to define an active region, and a readout circuit 120 including a transistor is formed in the active region. For example, the readout circuit 120 may include a transfer transistor (Tx) 121, a reset transistor (Rx) 123, a drive transistor (Dx) 125, and a select transistor (Sx) 127. can do. Thereafter, an ion implantation region 130 including a floating diffusion region (FD) 131 and source / drain regions 133, 135, and 137 for each transistor may be formed.

The forming of the lead-out circuit 120 on the first substrate 100 may include forming an electrical junction region 140 on the first substrate 100 and forming an interconnection on the electrical junction region 140. And forming a first conductivity type connection region 147 connected to 150.

For example, the electrical junction region 140 may be a PN junction 140, but is not limited thereto. For example, the electrical junction region 140 may include a first conductive ion implantation layer 143 and a first conductive ion implantation layer (143) formed on the second conductive well 141 or the second conductive epitaxial layer. 143 may include a second conductivity type ion implantation layer 145. For example, the PN junction 140 may be a P0 145 / N- 143 / P-141 junction as shown in FIG. 2, but is not limited thereto. The first substrate 100 may be conductive in a second conductivity type, but is not limited thereto.

In the first embodiment, as shown in FIG. 2, the voltage difference between the source and the drain across the transistor Tx 121 is formed by forming the electrical junction region 140 on the first substrate 100 on which the readout circuit 120 is formed. This allows full dumping of the photocharge.

That is, according to the embodiment, the device may be designed such that there is a potential difference between the source and the drain across the transistor Tx, thereby enabling full dumping of the photo charge. For example, a device may be designed such that there is a voltage difference between sources / drains across the transistor Tx by lowering the doping concentration of the N- 143 region to a lower doping concentration of the FD 131.

Next, the first embodiment may form the first conductivity type connection region 147 for ohmic contact on the surface of the P0 / N− / P− junction 140. For example, an N + region 147 for ohmic contact may be formed on the surface of the P0 / N− / P− junction 140. The N + region 147 may be formed to contact the N− 143 through the P0 145.

Meanwhile, the width of the first conductive connection region 147 may be minimized in order to minimize the first conductive connection region 147 from becoming a leakage source.

To this end, the embodiment may proceed with a plug implant after etching the first metal contact 151a, but is not limited thereto. For example, the first conductive connection region 147 may be formed by forming an ion implantation pattern (not shown) and using the ion implantation mask as an ion implantation mask.

According to the first embodiment, the first conductive connection region 147 is formed between the photodiode and the lead-out circuit to create a smooth movement path for the photo charge, thereby minimizing dark current sources and saturation. ) Can be prevented from deterioration and deterioration of sensitivity.

Next, the interlayer insulating layer 160 may be formed on the first substrate 100, and the wiring 150 may be formed. The wiring 150 may include a first metal contact 151a, a first metal 151, a second metal 152, a third metal 153, and a fourth metal contact 154a, but is not limited thereto. It is not.

Next, as shown in FIG. 3, a crystalline semiconductor layer 210a is formed on the second substrate 200. By forming a photodiode in the crystalline semiconductor layer 210a, it is possible to prevent defects in the photodiode.

For example, the crystalline semiconductor layer 210a is formed on the second substrate 200 by epitaxial. Thereafter, hydrogen ions are implanted at the boundary between the second substrate 200 and the crystalline semiconductor layer 210a to form the hydrogen ion implanted layer 207a. The implantation of hydrogen ions may be performed after ion implantation to form the photodiode 210.

Next, as shown in FIG. 4, the photodiode 210 is formed by ion implantation into the crystalline semiconductor layer 210a. For example, a second conductivity type conductive layer 216 is formed under the crystalline semiconductor layer 210a. For example, a high concentration P-type conductive layer 216 may be formed by implanting ions into the entire surface of the second substrate 200 with a blanket under the crystalline semiconductor layer 210a without a mask.

Thereafter, a first conductivity type conductive layer 214 is formed on the second conductivity type conductive layer 216. For example, the low concentration N-type conductive layer 214 may be formed by implanting ions onto the entire surface of the second substrate 200 without a mask on the second conductive conductive layer 216.

Thereafter, the first embodiment may further include forming a high concentration of the first conductivity type conductive layer 212 on the first conductivity type conductive layer 214. For example, an ion implantation may be performed on the entire surface of the second substrate 200 without a mask on the first conductive type conductive layer 214 to form a high concentration N + type conductive layer 212, thereby contributing to ohmic contact.

Next, as shown in FIG. 5, the first substrate 100 and the second substrate 200 are bonded to each other so that the photodiode 210 and the wiring 150 correspond to each other. In this case, the bonding may be performed by increasing the surface energy of the surface bonded by activation by plasma before bonding the first substrate 100 and the second substrate 200. Meanwhile, in order to improve the bonding force, bonding may be performed through an insulating layer, a metal layer, or the like on the bonding interface.

Thereafter, the hydrogen ion implantation layer 207a may be changed into a hydrogen gas layer (not shown) through heat treatment on the second substrate 200.

Next, as shown in FIG. 6, the photodiode 210 may be exposed by leaving a photodiode 210 based on the hydrogen gas layer and removing a portion of the second substrate 200 using a blade or the like.

Subsequently, the photodiode 210 may be etched by pixel, and the etched portion may be filled with an inter-cell insulation layer (not shown). Alternatively, a P-type ion implantation layer may be formed for pixel separation.

Thereafter, a process such as the upper electrode 240 and a color filter (not shown) may be performed.

(2nd Example)

7 is a sectional view of an image sensor according to a second embodiment.

The image sensor according to the second embodiment may include a first substrate 100 having a wiring 150 and a readout circuit 120 formed thereon; And an image sensing unit 210 formed above the readout circuit 120. The lead-out circuit 120 of the first substrate 100 may include an electrical junction region 140 formed on the first substrate 100; And a first conductivity type connection region 148 formed on one side of the electrical junction region to be connected to the wiring 150.

The second embodiment can employ the technical features of the first embodiment.

For example, the second embodiment applies a strong reverse bias to the photodiode top surface to more effectively remove carriers in the photodiode area during the reset operation of the image sensor, thereby resetting the reset noise or the dark current. (Dark Current) can be prevented.

In addition, according to the embodiment, the device may be designed such that there is a potential difference between the source / drain across the transistor Tx, thereby enabling full dumping of the photo charge. Accordingly, as the photo charge generated in the photodiode is dumped into the floating diffusion region, sensitivity to the output image may be increased.

In addition, according to the embodiment, the charge connection region is formed between the photodiode and the lead-out circuit to create a smooth movement path of the photo charge, thereby minimizing the dark current source, and reducing saturation and sensitivity. It can prevent.

Meanwhile, unlike the first embodiment, the second embodiment is an example in which the first conductive connection region 148 is formed on one side of the electrical bonding region 140.

According to an embodiment, an N + connection region 148 for ohmic contacts may be formed in the P0 / N− / P− junction 140, in which the process of forming the N + connection region 148 and the M1C contact 151a may be performed. It can be a Leakage Source. This is because the electric field EF may be generated on the Si surface of the substrate because the reverse bias is applied to the P0 / N− / P− junction 140. The crystal defects generated during the contact forming process in the electric field become a liquid source.

In addition, according to the embodiment, when the N + connection region 148 is formed on the surface of the P0 / N- / P- junction 140, an E-Field by the N + / P0 junction 148/145 is added. Becomes

Accordingly, the embodiment provides a layout for forming a first contact plug 151a in an active region formed of an N + connection region 148 without being doped with a P0 layer and connecting the N-junction 143 with the N-junction 143. .

According to the second embodiment, the E-Field of the Si surface does not occur, which may contribute to the reduction of dark current of the 3-D integrated CIS.

The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.

1 is a sectional view of an image sensor according to a first embodiment;

2 to 6 are process cross-sectional views of a method of manufacturing the image sensor according to the first embodiment.

7 is a sectional view of an image sensor according to a second embodiment;

Claims (20)

A first substrate on which wiring and readout circuitry are formed; And And an image sensing unit formed on the readout circuit. And a reverse bias is applied to an upper side of the image sensing unit at reset. delete According to claim 1, The reverse bias is Image sensor, characterized in that -3V to -5V is applied. According to claim 1, The lead out circuit is An electrical junction region formed in the first substrate, The electrical junction region is A first conductivity type ion implantation region formed on the first substrate; And And a second conductivity type ion implantation region formed on the first conductivity type ion implantation region. The method of claim 4, wherein And a first conductive connection region formed on the electrical junction region and electrically connected to the wiring. The method of claim 4, wherein The electrical junction region is Image sensor characterized in that the PNP junction (junction). According to claim 1, The readout circuit includes a transistor, And a potential difference between the source and the drain of the transistor. The method of claim 7, wherein The transistor is a transfer transistor, And an ion implantation concentration of the transistor source is lower than an ion implantation concentration of the floating diffusion region which is the drain of the transistor. The method of claim 4, wherein And a first conductivity type connection region formed on one side of the electrical junction region to be electrically connected to the wiring. The method of claim 9, The first conductivity type connection region And an electrical junction region in contact with the device isolation region. delete delete delete delete delete A first substrate on which wiring and lead-out circuits are formed; And an image sensing unit electrically connected to the wiring and formed on the first substrate. The first substrate is conductive in a second conductivity type, The readout circuit, A transistor formed on the first substrate; And An electrical junction region formed at one side of the transistor; And a reverse bias is applied to an upper side of the image sensing unit at reset. The method of claim 16, The electrical junction region is A first conductivity type ion implantation region formed on the first substrate; And And a second conductivity type ion implantation region formed on the first conductivity type ion implantation region. The method of claim 16, And a first conductivity type connection region connected to the wire and formed to contact the electrical junction region. delete The method of claim 16, And a potential difference between a source and a drain of the transistor of the readout circuit.

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