KR100905153B1 - Filters, Interpolation Filters, and Decimation Filters for Digital Up-Down Converters - Google Patents

Abstract

An interpolation filter according to an embodiment of the present invention capable of processing an IQ signal having a baseband frequency or an IF frequency is an M-tap interpolation filter that performs N-up up-sampling on an I signal and a Q signal input at a first sampling frequency. A delay unit configured to continuously delay the I signal and the Q signal by the period for each period corresponding to the first sampling frequency; A delay signal selection unit for selecting the delayed I or Q signals by M / (2 × N) for each clock corresponding to 2N times the first sampling frequency; A filter coefficient selector for selecting a filter coefficient corresponding to the selected I or Q signal for each of the clocks; And an accumulator for calculating a partial sum through a product of the selected I signal or Q signal and the selected filter coefficient, and calculating a filtering result value through the total sum of the partial sums.

Description

Filter For Digital Up-down Converter, Interpolation Filter, and Decimation Filter

The present invention relates to filters for digital up-down converters, interpolation filters, and decimation filters, and more particularly, filters for digital up-down converters, interpolation filters, and decimations capable of processing IQ signals having baseband or IF frequencies. It is about a filter.

In general, to implement a circuit that provides the function of raising or lowering the sampling frequency between a signal of a digital baseband frequency and a signal of a digital intermediate frequency, an up-down sampling technique, There is a need for filters and frequency conversion techniques for digital signals.

The digital upconverter, which supports upsampling required for frequency conversion of digital signals, converts the baseband digital IQ signal into an intermediate band (IF) digital IQ signal. Convert the signal to a baseband digital IQ signal.

In order to increase the sampling frequency in the digital up-converter or the digital down-converter, the baseband input signal is upsampled through an interpolator, and a low-pass filter is passed to remove the image spectrum. In addition, to reduce the sampling frequency, eliminating aliasing through a low pass filter in the IF input signal and down sampling through a decimator.

However, in the digital frequency conversion process, the baseband IQ signal must be separated and transmitted by I and Q, and thus, two ADC (Analog to Digital Converter) or DAC (Digital to Analog Converter) for analog and digital conversion are transmitted and received. There is a problem that the time difference between the two signals is large due to the transmission and reception delay of the I signal and the Q signal.

In addition, since the I and Q signals must be filtered through the digital filter in the digital up-down conversion process, the number of digital filters or the internal logic of the digital filter increases.

In addition, in order to implement TDD (Time Division Duplexing) technology, a digital up-down converter that supports both upsampling and downsampling should be used. In this case, it is necessary to filter not only a transmission signal but also a reception signal. Internal logic has had a problem that increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and it is a technical problem to provide a filter, an interpolation filter, and a decimation filter of a digital up-down converter supporting up-down sampling.

Another object of the present invention is to provide a digital up-down converter filter, an interpolation filter, and a decimation filter that can filter a signal separated into an I signal Q signal through one digital filter.

In addition, the present invention provides a digital up-down converter that supports up-down sampling to implement TDD, and includes a digital up-down converter filter, an interpolation filter, and a decimation filter that can filter a transmission and a reception signal through one digital filter. It is another technical problem to provide.

An interpolation filter according to an aspect of the present invention for achieving the above object is, in the M-tap interpolation filter for performing N-fold up-sampling on the I and Q signals input at the first sampling frequency, the first sampling frequency. A delay unit for continuously delaying the I signal and the Q signal by the period at each corresponding period; A delay signal selection unit for selecting the delayed I or Q signals by M / (2 × N) for each clock corresponding to 2N times the first sampling frequency; A filter coefficient selector for selecting a filter coefficient corresponding to the selected I or Q signal for each of the clocks; And an accumulator that calculates a partial sum through the product of the selected I signal or Q signal and the selected filter coefficient, and calculates a filtering result value through the total sum of the partial sums.

In order to achieve the above object, an interpolation filter according to another aspect of the present invention is an M-tap interpolation filter that performs N-up up-sampling on an I signal and a Q signal input at a first sampling frequency. A delay unit for continuously delaying the I signal and the Q signal by the period at each corresponding period; A delay signal selector for selecting the delayed I or Q signals by M / (K × N) for each clock corresponding to K × N times the first sampling frequency; A filter coefficient selector for selecting a filter coefficient corresponding to the selected I or Q signal for each of the clocks; And an accumulator configured to calculate a partial sum through a product of the selected I signal or Q signal and the selected filter coefficient, and calculate a FIR filtering result through the total sum of the partial sums.

A decimation filter according to an aspect of the present invention for achieving the above object, in the M tap decimation filter for performing 1 / N times down sampling of the I signal and the Q signal input at the first sampling frequency, A delay unit for continuously delaying the I signal and the Q signal at intervals corresponding to 1/2 times the first sampling frequency; A delay signal selector for selecting the delayed I or Q signals by M / (2N) for each clock corresponding to twice the first sampling frequency; A filter coefficient selector for selecting a filter coefficient corresponding to the selected I or Q signal for each of the clocks; And an accumulator for calculating a partial sum through a product of the selected I signal or Q signal and the selected filter coefficient, and calculating a filtering result value through the total sum of the partial sums.

A decimation filter according to another aspect of the present invention for achieving the above object is a M-tap decimation filter for performing 1 / N times down sampling on an I signal and a Q signal input at a first sampling frequency. A delay unit for continuously delaying the I and Q signals by the period every cycle corresponding to one-half times the first sampling frequency; A delay signal selector for selecting the delayed I or Q signals by M / (K × N) for each clock corresponding to 2K times the first sampling frequency; A filter coefficient selector for selecting a filter coefficient corresponding to the selected I or Q signal for each of the clocks; And an accumulator configured to calculate a partial sum through a product of the selected I signal or Q signal and the selected filter coefficient, and calculate a FIR filtering result through the total sum of the partial sums.

According to an aspect of the present invention, a filter for a digital up-down converter according to an aspect of the present invention performs N-ups up sampling on a first signal input at a first sampling frequency or a second signal input at a second sampling frequency. A filter for an M-tap digital up-down converter that performs 1 / N times down sampling with respect to a first filter, wherein the first signal is continuously delayed by the first period at every first period corresponding to the first sampling frequency, and the second signal is performed. A delay unit for continuously delaying the signal every cycle corresponding to 1/2 times the second sampling frequency; The delayed first and second signals include an I signal and a Q signal, respectively, and a delay signal for selecting the I signal or the Q signal by M / (2N) for each clock corresponding to 2N times the first sampling frequency. A selection unit; A filter coefficient selector for selecting a filter coefficient corresponding to the selected I or Q signal for each of the clocks; And an accumulator for calculating a partial sum through a product of the selected I signal or Q signal and the selected filter coefficient, and calculating a filtering result value through the total sum of the partial sums.

As described above, according to the present invention, signal processing is performed by using a digital filter that provides one up-down sampling of the I signal and the Q signal, so that an imbalance between the I signal and the Q signal can be overcome.

In addition, according to the present invention, by filtering the separated I and Q signals through one digital filter, there is another effect of reducing the number or internal logic of the digital filter for the digital up-down converter.

Further, according to the present invention, the signal processing of the transmission IQ signal and the reception IQ signal using one digital filter can reduce the number or internal area of the digital filter for the digital up-down converter.

1 is an overall block diagram of a digital up-down converter supporting up-down sampling according to an embodiment of the present invention.

As shown, a digital up-down converter supporting up-down sampling according to an embodiment of the present invention includes a digital up converter 102 supporting up sampling and a digital down converter 112 supporting down sampling.

Digital up converter 102 that supports upsampling includes an SP converter 104, an interpolator 106, a digital lowpass filter 108, and a digital upconverter 110.

The SP converter 104 separates the baseband I / Q signal into baseband I and Q signals through a serial to parallel converting technique. Then, the interpolator 106 upsamples to increase the sampling frequency of the separated I and Q signals.

The up-sampled signal is removed from the image spectrum through the digital low pass filter 108 and then becomes a real signal of the intermediate band IF through the digital up converter 110.

The digital up converter 112 supporting down sampling includes a digital down converter 114, a digital low pass filter 116, a decimator 118, and a PS converter 120.

The real signal is separated into I and Q signals at the IF frequency via the digital down converter 114 and then through the digital low pass filter 116 to prevent aliasing. After down-sampling by the decimator 118, it is converted into a series baseband I / Q signal by the PS converter 120.

2A and 2B illustrate a process of converting a real or IQ signal between a baseband and an IF frequency through a digital up converter and a digital down converter according to an embodiment of the present invention.

Referring to FIG. 2A, when the baseband signal BB is converted to the IF signal IF through the digital up converter 202a, only one real signal may be transmitted instead of the I and Q signals. Only real signals need to be received. In order to convert the baseband signal BB to the IF signal IF, a carrier 204a having an IF frequency needs to be multiplied.

In order to convert the IF signal IF into the baseband signal BB through the digital down converter 206a, the carrier 208a having the IF frequency needs to be multiplied.

For example, if the frequency of the carrier 204a is set to 1/4 of the sampling frequency of the baseband signal BB, the frequency conversion is implemented in a very simple process, and may be represented by Equation 1 below.

In Equation 1, τ is a phase offset and n is a sample index. Assuming τ is 0, the carrier 204a used for up-conversion has four complex samples: {(1,0), (0,1), (-1,0), (0, -1)}. The carrier 208a used for down conversion may be expressed as {(1,0), (0, -1), (-1,0), (0,1)}.

Referring to FIG. 2B, a digital up-down converted result can be simply expressed by a carrier conceptually set to one quarter of the sampling frequency of the baseband signal BB.

The digital up converter 202b converts the input I and Q signal strings in series so that the I and Q signals alternate. At this time, the output symbol string is also changed alternately.

 The digital down converter 204b converts the serial real symbol string into I and Q signals which are alternately outputted with the real signal. At this time, the input real symbols are alternately used for conversion.

As a result, the digital up-down conversion through the IF carrier corresponding to 1/4 of the input sampling frequency is made possible by an easy operation of selecting a predetermined signal among the input signals or inverting a sign.

Referring back to FIG. 1, in one embodiment of the present invention, the interpolator 106, the decimator 118, and all the digital low pass filters required for the digital up-down conversion are implemented as one filter 122 for the digital up-down converter. do. Hereinafter, the filter for the digital up-down converter 122 will be described in detail with reference to FIG. 3.

3 is a block diagram of a filter for a digital up-down converter supporting up-down sampling according to an embodiment of the present invention.

As illustrated, the digital up-down converter filter 302 supporting up-down sampling according to an embodiment of the present invention includes a delay unit 304, a delay signal selector 310, a filter coefficient storage unit 312a, and a filter. A coefficient selector 312b, an accumulator 314, a primary storage 322, and an effective number of bits setter 324 are included.

The digital up-down converter filter 302 according to an embodiment of the present invention performs interpolation and decimation for performing 6 times (N = 6) or 1/6 times down sampling on the input I and Q signals. Filter, a 192 Tab FIR digital filter. Here, the clock frequency of the filter is 12 times (= 2 × N times) of the input sampling frequency when operating as an interpolation filter, and 1/12 of the sampling frequency of the output of the filter 302 when operating as a decimation filter. It is a ship.

The input I signal or Q signal of the digital up-down converter filter 302 is separated and input in parallel, and the filtering results are output in series.

The frequency of the clock may be a general formula such as (K × N) times the input sampling frequency. Hereinafter, assuming that N is the up-sampling ratio, M is the number of taps, and K is the ratio of the clock frequency to the frequency corresponding to N times the input sampling frequency.

The delay unit 304 includes 96 shift registers 306 and 308 for the I and Q signals, respectively. The shift registers 306 and 308 differ in the number required when the filter 302 operates as an interpolation filter and when it operates as a decimation filter.

When the filter 302 operates as an interpolation filter, the delay unit 304 delays the input I signal or Q signal for each period corresponding to the input sampling frequency by using M / N shift registers 306 and 308, respectively. .

The delay unit 304 delays the input I signal or Q signal using M / 2 shift registers 306 and 308, respectively, when the filter 302 operates as a decimation filter.

When the filter 302 operates as an interpolation filter, the shift registers 306 and 308 delay the inputted I and Q signals successively every cycle corresponding to the input sampling frequency, i.e., 12 clock cycles.

As an example, when the tap delayed I signal is described, according to an input / output equation of a general FIR filter, the 192 tap FIR filter requires 192 sequentially delayed I signals for one filter output, but according to an embodiment of the present invention. Since the filter 302 is an interpolation filter that performs 6 times upsampling, if there are 192 sequentially delayed I signals, 5/6 of them will be interpolated to 0, and will be 0 anyway during the operation for filtering. Value is unnecessary information. Thus, in one embodiment of the present invention, 32 sequentially delayed I signals are required for one filter output, and only 32 shift registers 306 are required.

In the meantime, when the filter 302 operates as a decimation filter, the Q signal will be described as an example. The shift register 308 is continuously provided with a period corresponding to 1/2 times the input sampling frequency, that is, every four clocks. Delay the input Q signal. Here, the reason for delaying at every cycle corresponding to 1/2 times the input sampling frequency will be explained with reference to FIG. 2B. This is the input to the filter. However, the output of the digital down converter 204b alternates between 0 and a non-zero signal value in the case of the Q signal.

Therefore, half of the input Q signals are not necessary to be zero in the calculation, and only 96 Q signals are required in the filtering operation and sequentially delayed by the shift register 308.

When the filter 302 operates as an interpolation filter, the delay signal selector 310 selects M / (2 × N) signals for each clock, which are sequentially delayed by the shift registers 306 and 308. In one embodiment of the invention, M is 192, the number of taps, and N is 6, the upsampling rate. Therefore, there will be 16 sequentially delayed I or Q signals to be selected. Here, the number of the selected signal can be expressed by M / (K × N).

4 is a diagram for describing an operation of the delay signal selector 310 when the filter 302 operates as an interpolation filter.

First, the delay signal selector 310 selects 16 402 from the I signals having the largest delay time among the 32 delayed I signals through the multiplexer D_SEL. The 16 delayed I signals 402 are distributed and output through 16 multiplexers D-MUX0 to 15. The output I signals 402 are then multiplied by the corresponding filter coefficients for the FIR filtering operation in the accumulator 314.

Next, 16 delayed I signals 404 are selected and output through the multiplexers D-MUX0 to 15.

Next, similarly to the Q signal, 16 406 are selected from the Q signal having the largest delay time and output through the multiplexers D-MUX0 to DMUX15. Then, the remaining 16 Q signals are selected and output.

Therefore, all 32 delayed I signals are output through two selection processes, and then all 32 delayed Q signals are also output. Here, the reason for performing two selection processes for the I signal or the Q signal, respectively, is to reduce the multipliers to 16. The accumulator 314 must multiply 32 times in order to generate one writing force output, but it is possible to perform all necessary multiplications twice using the 16 multipliers through the above-described selection process.

In addition, even if the multiplication is performed twice, since the clock frequency is 2N times the input sampling frequency, the calculation result of the accumulator 314 may be output at a predetermined time without delay.

In addition, when one I signal and a Q signal are input to the filter 302, the delay signal selector 310 undergoes a total of 12 selection processes in order to calculate a six-fold upsampled corresponding filtering result. That is, 16 delayed I signals are selected 6 times (= 2 × 3), and 16 Q signals are selected six times (= 2 × 3).

As described above, the delay signal selecting unit 310 may be regarded as repeatedly performing the process of selecting the delayed Q signal K times after selecting the delayed I signal K times.

Referring back to FIG. 3, when the filter 302 operates as a decimation filter, the delay signal selector 310 may sequentially change the I signal or Q signal delayed by the shift registers 306 and 308 for each clock M / ( 2 x N) In this case, the number of I signals to be selected may be expressed as M / (K × N).

FIG. 5 is a diagram for describing an operation of the delay signal selector 310 when the filter 302 operates as a decimation filter.

First, the delay signal selector 310 selects 16 502 from the 96 delayed I signals having the largest delay time through the multiplexer D_SEL. The 16 delayed I signals 502 are output through 16 multiplexers D-MUX0 to 15. The output I signals 502 are later multiplied by the corresponding filter coefficients for FIR filtering in the accumulator 314.

Next, 16 pieces of the remaining unselected I signals are repeatedly selected and distributed through the multiplexers D-MUX0 to 15 to output.

Next, similarly to the Q signal, 16 504 are selected from the Q signal having the largest delay time and output through the multiplexers D-MUX0 to 15.

Then, 16 pieces are repeatedly selected for the remaining unselected Q signals. Therefore, all 96 delayed I signals are output through 6 selection processes, and all 96 delayed Q signals are output through 6 subsequent selection processes. Here, the reason why the six or six selection processes are selected for the I signal or the Q signal instead of three is to reduce the multipliers used to calculate the FIR filtering result of the accumulator 314 to 16.

Referring back to FIG. 3, the filter coefficient storage unit 312a stores 192 filter coefficients h0 to h191 for input / output operations of the 192 tap FIR filter. The filter coefficients may be stored in any suitable manner and stored in the memory device.

The filter coefficient selector 312b selects and outputs a filter coefficient corresponding to the I signal or the Q signal selected by the delay signal selector 310 for each clock.

6 is a view for explaining the operation of the filter coefficient selection unit 312b when the filter 302 operates as an interpolation filter.

First, the filter coefficient selector 312b selects 16 filter coefficients 602 mapped to an I signal or a Q signal output from the delay signal selector 310. The sixteen filter coefficients 602 obtained through the multiplexer H_SEL from the filter coefficient storage unit 312a are again output through the sixteen multiplexers H-MUX0 to 15. The output filter coefficient 602 is multiplied by the corresponding I or Q signal for FIR filtering in the accumulator 314.

Next, the next 16 filter coefficients 604 are selected, distributed through the multiplexers H-MUX0 to 15, and output. Hereinafter, a set of h arranged up to h (186) in the order of h (96), h (102), and h (108) will be referred to as h (96: 6: 18).

The control signal of the filter coefficient selector 312b selects 16 filter coefficients 602, which may be represented by h (96: 6: 18), and 16, which may be represented by h (97: 6: 187). Filter coefficients 604 are selected. In the same way, a total of 192 filter coefficients are output through a total of 12 selection processes.

FIG. 7 is a diagram for explaining the operation of the filter coefficient selector 312b when the filter 302 operates as a decimation filter.

First, the filter coefficient selector 312b selects 16 filter coefficients 702 mapped to an I signal or a Q signal output from the delay signal selector 310. The sixteen filter coefficients 702 obtained from the filter coefficient storage unit 312a are output through sixteen multiplexers H-MUX0 to 15. The output filter coefficient 702 is multiplied by the corresponding I or Q signal for FIR filtering in the accumulator 314.

Accordingly, the filter coefficient selector 312b outputs all 192 filter coefficients through a total of 12 selection processes.

Referring again to FIG. 3, the accumulator 314 includes a multiplier 316, an adder 318, a shift register 320, and a primary storage 322.

The accumulator 314 includes 16 multipliers 316 that multiply the I or Q signal selected by the delay signal selector 310 and the filter coefficient selected by the filter coefficient selector 312b. And add all of the outputs of the multiplier through adders 318.

Here, the number of multipliers 316 used by the accumulator 314 may be expressed by Equation 2 below.

Number of multipliers = M / (K × N)

In one embodiment of the present invention, the 192-tap interpolation filter 302 which performs 6 times upsampling and the decimation filter 302 which performs downsampling 1/6 times sequentially 32 delayed I or Q signals and corresponding filter coefficients. The FIR filtering operation should be performed by multiplying, but by determining the clock of the filter 302 to be twice the upsampling rate, only 16 multipliers 316 are required. Instead, by multiplying the multiplier twice with 16 multipliers 316, the multiplication value of the 32 I or Q signals and the corresponding filter coefficient can be calculated.

The primary storage unit 322 stores a partial sum of 16 multiplication values of 16 I signals or Q signals output from the delay signal selecting unit 310 and 16 corresponding filter coefficients output from the filter coefficient selecting unit 312b. do. Subsequently, the total sum is calculated by adding up the subtotals generated in the same manner. The FIR filtering result for the corresponding input is obtained through the total sum.

When the filter 302 operates as an interpolation filter, the first storage unit 322 may accumulate the I signals or Q signals that are consecutively selected K times by the delay signal selection unit 310. The unit may calculate the total sum by storing a partial sum of the first selected I signal or the Q signal and accumulating and storing the partial sums up to the Kth selected I signal or the Q signal in the same manner.

When the filter 302 operates as a decimation filter, the first storage unit 322 is configured such that the accumulating unit is first selected in the I signal or the Q signal that is selected six times consecutively by the delay signal selecting unit. The total sum can be calculated by storing a partial sum for an I signal or a Q signal and accumulating and storing the partial sums up to the sixth selected I or Q signal in the same manner.

In addition, the accumulator 314 shifts the shift register 320 as a delay element to perform a more stable FIR filtering operation on a signal processing delay time that occurs during a plurality of operations such as multiplexing, multiplying, and adding a plurality of signals. ). The signals that have passed through the shift register 320 are synchronized with respect to the clock so that no timing malfunction occurs.

When the filter 302 operates as an interpolation filter, the accumulator 314 alternately outputs the filtered I signal and the Q signal in series in an interval corresponding to upsampling.

When the filter 302 operates as an interpolation filter, the accumulator 314 alternately outputs the filtered I and Q signals in series in a cycle corresponding to the downsampling.

The effective bit number setting unit 324 leaves the output of the accumulator 314 by the significant digit bit and removes the remaining bits. In one embodiment, the effective bit number setting unit 324 matches the number of bits of the input / output signal when the output of the accumulation unit 314 is larger than the number of bits of the I signal or the Q signal input to the filter 302. The effective number of bits in the output I or Q signal can be adjusted.

When the filter 302 operates as an interpolation filter, the filter 302 generates a first real symbol at a period corresponding to the upsampling by using the I and Q signals output from the accumulator 314. It may further include a converting unit (not shown).

By further including a first converting unit (not shown), referring to FIG. 2B, the digital up-down conversion is simply performed by the carrier 204a set to 1/4 of the sampling frequency of the baseband signal BB. Since the filter 304 may alternately output the I and Q signals in series, the filter 304 may alternately output the sign of the output signal alternately using the first converting unit. The effect of the up converter can be achieved.

When the filter 302 operates as a decimation filter, the filter 302 uses a real symbol input in series to generate a second converting signal having an I and Q signal having an input sampling frequency of the filter 302. It may further include a portion (not shown).

By further including a second converting unit (not shown), referring to FIG. 2B, the filter 302 requires parallel I and Q signals as inputs, and uses the second converting unit to generate a serial real symbol string. By converting the I and Q signals, which are alternately output between the real signal and 0, and alternating the codes, the digital down converter can be easily produced at the input side of the filter 302.

When the filter 302 operates as an interpolation filter, the filter 302 may further include a serial / parallel unit (not shown) for separating and outputting the I and Q signals in parallel from input symbols input in series. have.

8 is a timing diagram illustrating a signal flow when a digital up-down converter filter operates as an interpolation filter according to an embodiment of the present invention.

Referring to the timing diagram of FIG. 8 with reference to the block diagrams of FIGS. 1 and 3, first, the frequency of the clock CLK_12x 802 is a frequency obtained by up-sampling the sampling frequency of the input serial IQ signal DIN_IQ 804 by six times. 2 times larger than

The input I signal S / P_I 806 is an I component output of the SP converter 104, and the input Q signal S / P_Q 808 is a Q component output of the SP converter 104. For example, “i ₃₂ ” refers to the 32nd input I signal of the interpolation filter.

The delayed I signal (REG_I: 810) of the shift register and the delayed Q signal (REG_Q: 812) of the shift register have a predetermined period (=) between the input I signal 806 and the input Q signal 808, which are interpolation filter inputs, by the shift register. 12 clock cycles).

For example, I [32: 1] means that 32 I signals of i ₁ to i ₃₂ are sequentially delayed in ₃₂ shift registers.

The delayed filter input signal FIN_D 814 is an I signal or a Q signal which is selected from the delay signal selector 310 and inputs to the accumulator 314.

The filter coefficient FIN_H 816 is a filter coefficient multiplied by the delayed filter input signal 814 and the accumulator 314.

If i ₃₂ is delayed and stored in the shift register for input delay, an I [32: 1] signal is generated and the interpolation FIR filtering operation for i ₃₂ is started.

First, in I [32: 1], D0 815a is selected and the corresponding filter coefficient H0 is selected. The mapping relationship between the delayed filter input signal D0 815a and the filter coefficient H0 is shown in table 822. In addition, "H0 = H [96: 6: 186]" means filter coefficients arranged at intervals of 6 from h ₉₆ to h ₁₈₆ .

The delay signal selector 310 sequentially selects D0 815a to D11 815b for each clock, and the accumulator 314 sequentially multiplies and adds the signals. At this time, D0 815a and D1 are I signals, and D2 and D3 are Q signals. The I and Q signals are alternately calculated by the accumulator 314.

The filter output (F_OUT: 818) is an FIR filtered value, and the I and Q signals are alternated. For example, the accumulator 314 calculates a partial value by adding the multiplication values of D0 815a and H0 and stores the partial value in the primary storage unit 322. Then, the multiplication value of D1 and H1 is added to calculate the partial value, and the sum is added to the value stored in the primary storage unit 322 to calculate a final value of I _{32 , 0} .

As described above, the filter outputs F_OUT 818 are obtained through two multiplication processes by selecting 16 I signals or Q signals, and thus the multipliers 316 can be reduced from 32 to 16.

The digital up-converter output (DU_OUT: 820) is an output value of the digital up-converter 110, and alternately outputs the signals of the I and Q signals alternately using the values of the filter output (F_OUT: 818) output in series. . This is the same as described with respect to FIG. 2B and will be omitted.

FIG. 9 is a timing diagram illustrating a signal flow when the digital up-down converter filter operates as a decimation filter according to an embodiment of the present invention.

Referring to the timing diagram of FIG. 9 with reference to the block diagrams of FIGS. 1 and 3, first, the clock CLK_12x: 902 is twice as large as the frequency of up-sampling the sampling frequency of the filter output FOUT 918 by six times.

The input signal DD_IN 904 of the digital down converter 114 is a real signal transmitted in series. The output I signal (DDO_I) 906 and the Q signal (DDO_Q) 908 of the digital down converter 114 alternately take a real value of the input including 0, and alternately take a minus sign. Since this has been described with reference to FIG. 2B, a detailed description thereof will be omitted.

The delayed I signal (REG_I: 910) of the shift register and the delayed Q signal (REG_Q: 912) of the shift register have a predetermined period of time between the input I signal 906 and the input Q signal 908, which are the decimation filter inputs, by the shift register. = 4 clock cycles).

The delayed filter input signal FIN_D 914 is an I signal or a Q signal which is selected from the delay signal selector 310 and inputs to the accumulator 314.

The filter coefficient FIN_H 916 is a filter coefficient multiplied by the delayed filter input signal 914 and the accumulator 14.

Hereinafter, the output process of I _{192 .0} 915c will be described. When r ₁₉₂ is stored in the shift register for input delay, an I [192: 2: 2] signal is generated. However, the decimation FIR filtering operation for the output of I _{192 .0} 915c has already begun at the point where D0 915a is selected.

When r ₁₉₂ is input, stored in the shift register, and D5 is selected and operated, the filtering operation for the output of I _{192 .0} (915c) is completed. The mapping relationship between the delayed filter input signal D0 915a and the filter coefficient H0 is shown in the table 920.

For the outputs of I _{192 .0} (915c) and I _{191 .1} , the signals from D0 915a to D11 915b are sequential among the signals of I [192: 2: 2] and Q [191: 2: 1]. It is selected as, the accumulator 314 is to multiply and add sequentially.

The filter output (FOUT) 918 is a FIR filtered value, and the I and Q signals are alternated. For example, the accumulator 314 adds the multiplication values of D0 915a and H0 to calculate a partial value and stores the partial value in the primary storage unit 322. Then, the multiplication values of D1 and H1 are added together to calculate a partial value and then summed with the values stored in the primary storage unit 322.

This, by repeating the process until D5, it is possible to perform a multiplication process over by 16 6 times for 96 delayed I signal, it can eventually be obtained by the output value of the FIR I _{192 .0} (915c).

As described above, the multiplier 316 can be reduced from 32 to 16 by selecting and calculating sixteen delayed I or Q signals six times and calculating the filter output FOUT 818.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features.

Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

1 is an overall block diagram of a digital up-down converter that supports up-down sampling in accordance with one embodiment of the present invention.

2A and 2B illustrate a process of converting a real or IQ signal between a baseband and an IF frequency through a digital up converter and a digital down converter according to an embodiment of the present invention.

3 is a block diagram of a filter for a digital up-down converter that supports up-down sampling in accordance with one embodiment of the present invention.

4 is a diagram for explaining an operation of a delay signal selector when a filter operates as an interpolation filter.

5 is a view for explaining the operation of the delay signal selection unit when the filter operates as a decimation filter.

6 is a view for explaining the operation of the filter coefficient selector when the filter operates as an interpolation filter.

7 is a view for explaining the operation of the filter coefficient selector when the filter operates as a decimation filter.

8 is a timing diagram illustrating a signal flow when a filter for a digital up-down converter operates as an interpolation filter according to an embodiment of the present invention.

9 is a timing diagram illustrating a signal flow when the digital up-down converter filter operates as a decimation filter according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

302: filter for the digital up-down converter 304: delay

306 and 308: shift register 310: delay signal selector

312a: filter coefficient storage unit 312b: filter coefficient selection unit

314: accumulator 316: multiplier

318: adder 320: shift register

322: primary storage unit 324: effective bit number setting unit

Claims (32)

An M-tap interpolation filter which performs N-fold up-sampling on an I signal and a Q signal input at a first sampling frequency, A delay unit for continuously delaying the I signal and the Q signal by the period for each period corresponding to the first sampling frequency; A delay signal selection unit for selecting the delayed I or Q signals by M / (2 × N) for each clock corresponding to 2N times the first sampling frequency; A filter coefficient selector for selecting a filter coefficient corresponding to the selected I or Q signal for each of the clocks; And An accumulator for calculating a partial sum through a product of the selected I signal or Q signal and the selected filter coefficient, and calculating a filtering result value through the total of the partial sums; Interpolation filter, characterized in that it comprises a. The method of claim 1, And the delay signal selecting unit repeatedly selects the delayed I signal twice and then selects the delayed Q signal twice. The method of claim 1, In the I signal or the Q signal selected two times in succession by the delay signal selecting section, the accumulating section stores a partial sum of the first selected I signal or the Q signal, and then stores the sub sum of the first selected I signal or the Q signal. And calculating the subtotal to add the stored subtotal to the subtotal to calculate the total sum. The method of claim 1, And the accumulator calculates the filtering result using M / (2 × N) multipliers. The method of claim 1, And the accumulator outputs the I and Q signals, which are the filtering result values, in series and in series according to a period corresponding to the upsampling. The method of claim 1, And a serial / parallel unit configured to generate the input I and Q signals by separating and outputting the I and Q signals of an input symbol in parallel. The method of claim 6, And a first converting unit generating a real symbol at a period corresponding to the upsampling with respect to the input symbol by using the I signal and the Q signal output from the accumulator. The method of claim 1, And an effective bit number setting unit for receiving an I signal or a Q signal output from the accumulator and outputting an I signal and a Q signal having a specific number of bits. The method of claim 1, And the filtering result is an FIR filtering value. The method of claim 1, And the delay unit delays the input I signal or the Q signal by using M / N shift registers, respectively. The method of claim 1, And the accumulator delays an input of the delay signal selector through a shift register using the clock. An M-tap interpolation filter which performs N-fold up-sampling on an I signal and a Q signal input at a first sampling frequency, A delay unit for continuously delaying the I signal and the Q signal by the period for each period corresponding to the first sampling frequency; A delay signal selector for selecting the delayed I or Q signals by M / (K × N) for each clock corresponding to K × N times the first sampling frequency; A filter coefficient selector for selecting a filter coefficient corresponding to the selected I or Q signal for each of the clocks; And An accumulator for calculating a partial sum through a product of the selected I signal or Q signal and the selected filter coefficient, and calculating an FIR filtering result value based on the total sum of the partial sums; Interpolation filter, characterized in that it comprises a. The method of claim 12, And the delay signal selecting unit repeatedly selects the delayed Q signal K times after selecting the delayed I signal K times. The method of claim 12, In the I signal or the Q signal sequentially selected K times by the delay signal selector, the accumulator accumulates from a partial sum of the first selected I signal or the Q signal to a partial sum of the K selected I or Q signals. And calculating the total sum by storing the interpolation filter. The method of claim 12, And the accumulator calculates the filtering result using M / (K × N) multipliers. In the M-tap decimation filter for down sampling 1 / N times the I and Q signals input at the first sampling frequency, A delay unit for continuously delaying the I signal and the Q signal at intervals corresponding to 1/2 times the first sampling frequency; A delay signal selector for selecting the delayed I or Q signals by M / (2N) for each clock corresponding to twice the first sampling frequency; A filter coefficient selector for selecting a filter coefficient corresponding to the selected I or Q signal for each of the clocks; And An accumulator for calculating a partial sum through a product of the selected I signal or Q signal and the selected filter coefficient, and calculating a filtering result value through the total of the partial sums; A decimation filter comprising a. The method of claim 16, And the delay signal selector repeatedly selects the delayed I signal six times and then selects the delayed Q signal six times. The method of claim 16, In the I signal or the Q signal continuously selected M / (2N) times by the delay signal selector, Here, M / (2N) is 6, and the accumulator calculates the total sum by accumulating and storing the partial sums from the partial sum of the first selected I signal or the Q signal to the sixth selected I signal or the Q signal. A decimation filter characterized by the above. The method of claim 16, And the accumulating unit calculates the filtering result value using M / (2N) multipliers. The method of claim 16, And the accumulator outputs the filtered I and Q signals alternately in series according to the period corresponding to the down sampling. The method of claim 16, And a second converting unit configured to generate an I signal and a Q signal input at the first sampling frequency using real symbols input in series. The method of claim 16, And a valid bit number setting unit for receiving an I signal or a Q signal output from the accumulator and outputting an I signal and a Q signal having a specific number of bits. The method of claim 16, The filtering result is a decimation filter, characterized in that the FIR filtering value. The method of claim 16, And the delay unit delays the input I signal or the Q signal by using a shift register of M / 2, respectively. In the M-tap decimation filter for down sampling 1 / N times the I and Q signals input at the first sampling frequency, A delay unit for continuously delaying the I signal and the Q signal by the period every cycle corresponding to 1/2 times the first sampling frequency; A delay signal selector for selecting the delayed I or Q signals by M / (K × N) for each clock corresponding to 2K times the first sampling frequency; A filter coefficient selector for selecting a filter coefficient corresponding to the selected I or Q signal for each of the clocks; And An accumulator for calculating a partial sum through a product of the selected I signal or Q signal and the selected filter coefficient, and calculating an FIR filtering result value based on the total sum of the partial sums; A decimation filter comprising a. A filter for an M-tap digital up-down converter that performs N-up up-sampling on a first signal input at a first sampling frequency or 1 / N-down down-sampling on a second signal input at a second sampling frequency. A delay for continuously delaying the first signal by the first period at every first period corresponding to the first sampling frequency and continuously delaying the second signal at a period corresponding to 1/2 times the second sampling frequency part; The delayed first and second signals include an I signal and a Q signal, respectively, and a delay signal for selecting the I signal or the Q signal by M / (2N) for each clock corresponding to 2N times the first sampling frequency. A selection unit; A filter coefficient selector for selecting a filter coefficient corresponding to the selected I or Q signal for each of the clocks; And An accumulator for calculating a partial sum through a product of the selected I signal or Q signal and the selected filter coefficient, and calculating a filtering result value through the total of the partial sums; Digital up-down converter filter comprising a. The method of claim 26, In the I signal or the Q signal of the first signal selected two times in succession by the delay signal selection unit, the accumulating unit stores a partial sum of the I signal or the Q signal of the first signal selected first, And calculating the subtotal of the second selected I signal or the Q signal and adding the subtotal to the stored subtotal to calculate the total sum. The method of claim 26, In the I signal or the Q signal of the first signal selected six times in succession by the delay signal selector, the accumulator is selected sixth from a partial sum of the I or Q signal of the first signal selected first. And accumulating and storing up to a partial sum of an I signal or a Q signal of the first signal to calculate the total sum. The method of claim 26, And said accumulator calculates the filtering result using M / (2N) multipliers. The method of claim 26, And the accumulator outputs the I and Q signals of the filtering result alternately in series according to a period corresponding to the upsampling or downsampling. The method of claim 26, And a valid bit number setting unit for receiving an I signal or a Q signal output from the accumulator and outputting an I signal and a Q signal having a specific number of bits. The method of claim 26, The filtering result value is a filter for a digital up-down converter, characterized in that the FIR filtering value.

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