KR100914985B1 - Semiconductor package - Google Patents

Abstract

A semiconductor package is disclosed. The semiconductor package is a substrate including a first region having a first pad and a connection pad and a second region adjacent to the first region and having a second and third pads, disposed in the second region, and having a step shape. A chip select block including first and second steps having a first chip and first and second conductive members connected to the second and third pads through the first and second steps, respectively. A first semiconductor chip disposed in the structure and (i) the first region and having a first bonding pad connected to the first pad and a second bonding pad connected to the connection pad, (ii) the first semiconductor chip and the A second semiconductor chip disposed on a first step portion and having a third bonding pad connected to the first bonding pad and a fourth bonding pad connected to the first conductive member; and (iii) the second semiconductor chip and the second bonding pad. The third bonding is disposed on the step portion It includes a semiconductor chip structure having a third semiconductor chip having a bonding pad connected to the sixth and the fifth bonding pad and the second conductive member connected to the node.

Description

Semiconductor Package {SEMICONDUCTOR PACKAGE}

The present invention relates to a semiconductor package.

Recently, with the development of semiconductor chip manufacturing technology, various kinds of semiconductor packages having semiconductor chips and semiconductor chips suitable for storing massive data and processing more data in a short time have been developed.

Recently, in order to further improve the amount of data stored in a semiconductor package and the processing speed of data from the semiconductor package, a multilayer semiconductor package in which a plurality of semiconductor chips are stacked and electrically connected to a plurality of stacked semiconductor chips has been developed.

To implement a multilayer semiconductor package, a technology of selectively applying a control signal, a data signal, a power signal, and an address signal to a specific semiconductor chip among a plurality of stacked semiconductor chips is required, but a specific semiconductor chip among a plurality of stacked semiconductor chips is required. In order to select the semiconductor chip, the through electrodes may be formed in different patterns or at different positions in the semiconductor chips constituting the multilayer semiconductor package.

The present invention provides a semiconductor package suitable for input / output of data by selecting a plurality of stacked semiconductor chips having the same structure and stacked semiconductor chips.

A semiconductor package according to the present invention includes a substrate including a first region having a first pad and a connection pad, and a second region disposed adjacent to the first region and having second and third pads, the second region being disposed in the second region. And a chip select block including first and second stepped portions having a step shape and first and second conductive members connected to the second and third pads through the first and second stepped portions, respectively. And a chip select structure including (i) a first semiconductor chip disposed in the first region and having a first bonding pad connected to the first pad and a second bonding pad connected to the connection pad, and (ii) the first semiconductor chip. A second semiconductor chip having a semiconductor chip and a third bonding pad disposed on the first stepped portion and connected to the first bonding pad and a fourth bonding pad connected to the first conductive member; and (iii) the second semiconductor chip. And on the second staircase And a third semiconductor chip having a fifth bonding pad connected to the third bonding pad and a sixth bonding pad connected to the second conductive member.

The first semiconductor chip of the semiconductor package may include a first through electrode connecting the first pad and the first bonding pad, a second through electrode connecting the second bonding pad and the connection pad, and the first bonding pad. It further comprises a connected first redistribution.

The second semiconductor chip of the semiconductor package may include a third through electrode connecting the first bonding pad and the third bonding pad, a fourth through electrode connecting the first conductive member and the fourth bonding pad, and the third bonding chip. The apparatus may further include a second redistribution connected to the bonding pad.

The third semiconductor chip of the semiconductor package may include a fifth through electrode connecting the third bonding pad and the fifth bonding pad, a sixth through electrode connecting the second conductive member and the sixth bonding pad and the fifth bonding pad. The apparatus may further include a third redistribution line connected to the bonding pads.

The chip select block of the semiconductor package includes a ceramic.

The first to third pads of the semiconductor package are chip select pads to which a chip select signal is applied.

The semiconductor package further includes an underfill member interposed between the substrate, the first semiconductor chip, the first semiconductor chip, and the second semiconductor chip.

According to the present invention, it is possible to select one of the semiconductor chips having the same structure in which a plurality of layers are stacked using a chip select structure and to input / output data from the selected semiconductor chip.

1 is a perspective view illustrating a semiconductor package according to an embodiment of the present invention.

FIG. 2 is a plan view of the substrate shown in FIG. 1.

3 is a perspective view illustrating the chip select structure illustrated in FIG. 1.

4 is a cross-sectional view taken along the line II ′ of FIG. 1.

FIG. 5 is a plan view illustrating each semiconductor chip of the semiconductor chip structure illustrated in FIG. 1.

6 is a cross-sectional view taken along the line II-II 'of FIG. 1.

Hereinafter, a semiconductor package according to embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and those skilled in the art will appreciate The present invention may be embodied in various other forms without departing from the spirit of the invention.

1 is a perspective view illustrating a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor package 500 includes a substrate 100, a chip select structure 200, and a semiconductor chip structure 300.

FIG. 2 is a plan view of the substrate shown in FIG. 1.

The substrate 100 has a plate shape. The substrate 100 may be, for example, a printed circuit board.

The substrate 100 has a first region FR and a second region SR. The first region FR and the second region SR are disposed adjacent to the substrate 100.

The semiconductor chip structure 300, which will be described later, is disposed in the first region FR. The first pad 110 and the connection pad 120 are disposed in the first region FR.

The chip selection structure 200 to be described later is disposed in the second region SR. For example, the second pad 130 and the third pad 140 are disposed in the second region SR.

In the present embodiment, the second pad 130 and the third pad 140 are spaced at a specified interval, and the second pad 130 and the third pad 140 are in the first direction FD defined in FIG. 2. Is arranged in a direction parallel to the.

On the other hand, the first pad 120 disposed in the first region FR is disposed adjacent to the second pad 130 disposed in the second region SR, for example, and the first to third pads. For example, all of the 110, 130, and 140 are disposed in a direction parallel to the first direction FD.

In the present exemplary embodiment, the first to third pads 110, 130, and 140 are chip select pads for selecting one of the semiconductor chips included in the semiconductor chip structure 300, which will be described later. Each chip select signal is applied. In this embodiment, the chip select signals applied to the first to third pads 110, 130, and 140 may be the same or different.

3 is a perspective view illustrating the chip select structure illustrated in FIG. 1. 4 is a cross-sectional view taken along the line II ′ of FIG. 1.

3 and 4, the chip select structure 200 may include, for example, a chip select block 210, a first conductive member 220, and a second conductive member 230. In the present embodiment, the chip select structure 200 is disposed on the second region SR of the substrate 100.

The chip select block 210 disposed in the second region SR has, for example, a rectangular parallelepiped shape, and the chip select block 210 has at least one stepped portion 206 having a step shape. do.

In the present embodiment, the chip select block 210 includes two step portions 206, for example. Hereinafter, the two steps 206 will be defined as the first step 202 and the second step 204. The second step portion 204 is disposed above the first step portion 202.

In this embodiment, the chip select block 210 may include an insulating material. An example of an insulating material that can be used as the chip select block 210 is ceramic. Alternatively, the chip select block 210 may include various insulating materials in addition to the ceramic.

In addition, in order to reduce the planar area of the semiconductor package 500 illustrated in FIG. 1, the width W of the chip select block 210 illustrated in FIG. 3 may be as narrow as possible.

Referring to FIG. 4, the first conductive member 220 is disposed at a position corresponding to the first step portion 202. The first conductive member 220 has a conductive bar shape, and one end of the first conductive member 220 penetrates the chip select block 210 and is disposed on the second region SR of the substrate 100. It is electrically connected with the two pads 130. In the present embodiment, the first conductive member 220 has a first length.

The second conductive member 220 is disposed at a position corresponding to the second step portion 204. The second conductive member 230 has a conductive bar shape, and one end of the second conductive member 230 penetrates the chip select block 210 and is disposed on the second region SR of the substrate 100. It is electrically connected with the three pads 140. In the present embodiment, the second conductive member 230 has a second length longer than the first length.

In the present exemplary embodiment, the bottom surface of the chip select block 210 facing the substrate 100 and the substrate 100 may be bonded by an adhesive member (not shown).

FIG. 5 is a plan view illustrating each semiconductor chip of the semiconductor chip structure illustrated in FIG. 1. 6 is a cross-sectional view taken along the line II-II 'of FIG. 1.

4 to 6, the semiconductor chip structure 300 includes a first semiconductor chip 310, a second semiconductor chip 320, and a third semiconductor chip 330.

The first semiconductor chip 310 is disposed on the first region FR of the substrate 100. The first semiconductor chip 310 includes a first bonding pad 317, a first through electrode 319, a second bonding pad 311, a second through electrode 313, and a first redistribution 315. .

The first bonding pads 317 are disposed on the top surface of the first semiconductor chip 310. In the present embodiment, the first bonding pads 317 are disposed at positions corresponding to the first pads 110 of the substrate 100.

The first through electrode 319 penetrates through the top surface of the first semiconductor chip 310 and the bottom surface opposite to the top surface. Accordingly, the first through electrode 319 is disposed at a position corresponding to the first pad 110 of the substrate 100, and the first through electrode 319 is electrically connected to the first pad 110. Copper may be used as an example of the metal that may be used as the first through electrode 319.

For example, the second bonding pads 311 are disposed on the top surface of the first semiconductor chip 310. In the present embodiment, the plurality of second bonding pads 311 are disposed along the edge of the first semiconductor chip 310. For example, the second bonding pads 311 are disposed along the second direction SD that is substantially perpendicular to the first direction FD illustrated in FIG. 5.

The second through electrode 313 is spaced apart from each second bonding pad 311 by a predetermined interval. The second through electrode 313 penetrates the upper and lower surfaces of the first semiconductor chip 310, and each second through electrode 313 is connected to each connection pad of the substrate 100 as illustrated in FIG. 6. 120 is electrically connected.

The first redistribution 315 is disposed on the top surface of the first semiconductor chip 310. The first redistribution 315 electrically connects the second bonding pad 311 and the second through electrode 313.

The second semiconductor chip 320 is disposed on the first stepped portion 202 of the first semiconductor chip 310 and the chip select structure 200, and thus, the first semiconductor chip 310 and the second semiconductor chip ( 320 is arranged in a step shape.

The second semiconductor chip 320 includes a third bonding pad 327, a third through electrode 329, a fourth bonding pad 321, a fourth through electrode 323, and a second redistribution 325. .

The third bonding pads 327 are disposed on the top surface of the second semiconductor chip 320. In the present embodiment, the third bonding pad 327 is disposed at a position corresponding to the first conductive member 220 of the chip select structure 200.

The third through electrode 329 penetrates the upper surface of the second semiconductor chip 320 and the lower surface of the second semiconductor chip 320 that faces the upper surface. Thus, the third through electrode 329 is electrically connected to the first conductive member 220 of the chip select structure 200. Copper may be used as an example of the metal that may be used as the third through electrode 329.

The fourth bonding pads 321 are disposed on, for example, the upper surface of the second semiconductor chip 320. In the present embodiment, the plurality of fourth bonding pads 321 are disposed along the edge of the second semiconductor chip 320. For example, the fourth bonding pads 321 are disposed along the second direction SD that is substantially perpendicular to the first direction FD illustrated in FIG. 5.

The fourth through electrode 323 is spaced apart from each of the fourth bonding pads 321 by a predetermined interval. The fourth through electrode 323 penetrates the upper surface and the lower surface of the second semiconductor chip 320, and each of the fourth through electrodes 323 is connected to the first rewiring 315 of the first semiconductor chip 310. Electrically connected.

The second redistribution 325 is disposed on the top surface of the second semiconductor chip 320. The second redistribution 325 electrically connects the fourth bonding pad 321 and the fourth through electrode 323.

The third semiconductor chip 330 is disposed on the second stepped portion 204 of the second semiconductor chip 320 and the chip select structure 200, so that the first to third semiconductor chips 310, 320, and 330 are stepped. Is placed.

 The third semiconductor chip 330 includes a fifth bonding pad 337, a fifth through electrode 339, a sixth bonding pad 331, a sixth through electrode 333, and a third rewiring 335. .

The fifth bonding pads 337 are disposed on the top surface of the third semiconductor chip 330. In the present exemplary embodiment, the fifth bonding pad 337 is disposed at a position corresponding to the third conductive member 230 of the chip select structure 200.

The fifth through electrode 339 penetrates through the upper surface of the third semiconductor chip 330 and the lower surface of the third semiconductor chip 330. Thus, the fifth through electrode 339 is electrically connected to the second conductive member 230 of the chip select structure 200. Copper may be used as an example of the metal that can be used as the fifth through electrode 339.

The sixth bonding pad 331 is disposed on, for example, an upper surface of the third semiconductor chip 330. In the present embodiment, the plurality of sixth bonding pads 331 are disposed along the edge of the third semiconductor chip 330. For example, the sixth bonding pads 331 are disposed along the second direction SD that is substantially perpendicular to the first direction FD illustrated in FIG. 5.

The sixth through electrodes 333 are spaced apart from the sixth bonding pads 331 by a predetermined interval. The sixth through electrode 333 penetrates the upper and lower surfaces of the third semiconductor chip 330, and each sixth through electrode 333 is connected to the second redistribution 325 of the second semiconductor chip 320. Electrically connected.

The third redistribution 325 is disposed on the upper surface of the third semiconductor chip 330. The third redistribution 335 electrically connects the sixth bonding pad 331 and the sixth through electrode 333.

In the present embodiment, a gap is formed between the substrate 100 and the first semiconductor chip 310, the first semiconductor chip 310, and the second semiconductor chip 320, and the substrate 100 and the first semiconductor chip ( An under-fill member 350 may be interposed between the 310, the first semiconductor chip 310, and the second semiconductor chip 320.

As described above in detail, when the first chip select signal is applied through the first pad 110 of the substrate 100, the first chip select signal may be a first through electrode of the first semiconductor chip 310. The first semiconductor chip 310 is applied to the first semiconductor chip 310 through 319, and thus data is input and output from the first semiconductor chip 310.

In addition, when the second chip select signal is applied through the second pad 130 of the substrate 100, the second chip select signal may be applied to the first conductive member 220 and the second semiconductor chip of the chip select structure 200. The second semiconductor chip 320 is applied to the second semiconductor chip 320 through the third through electrode 329 of the 320, and thus data is input and output from the second semiconductor chip 320.

In addition, when the third chip select signal is applied through the third pad 140 of the substrate 100, the third chip select signal is the second conductive member 230 and the third semiconductor chip of the chip select structure 200. The third semiconductor chip 330 is applied to the third semiconductor chip 330 through the fifth through electrode 339 of 330. Accordingly, the third semiconductor chip 330 is selected to input and output data from the third semiconductor chip 330.

Meanwhile, in FIGS. 1 to 6, a technique of selecting any one of the semiconductor chips of the semiconductor chip module using the chip selection structure is disclosed. The chip select bonding pads may be electrically connected to each other, and the chip select bonding pads of the third semiconductor chip may be electrically connected using the conductive pins.

As described above in detail, it is possible to select one of the semiconductor chips having the same structure in which a plurality of layers are stacked and to input / output data from the selected semiconductor chip using the chip selection structure.

In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

Claims (7)

A substrate comprising a first region having a first pad and a connection pad and a second region disposed adjacent to the first region and having second and third pads; A chip selection block disposed in the second area and including first and second stepped portions having a stepped shape, and through the first and second stepped portions, respectively, to connect the first stepped portion and the second pad. A chip select structure comprising a first conductive member to form a second conductive member connecting the second stepped portion to the third pad; And (i) a first semiconductor chip disposed in the first region and having a first bonding pad connected to the first pad and a second bonding pad connected to the connection pad, (ii) the first semiconductor chip and the first A second semiconductor chip disposed on the stepped portion and having a third bonding pad connected to the first bonding pad and a fourth bonding pad connected to the first conductive member; and (iii) the second semiconductor chip and the second stepped portion. And a semiconductor chip structure having a third semiconductor chip disposed on and having a fifth bonding pad connected to the third bonding pad and a sixth bonding pad connected to the second conductive member. The method of claim 1, The first semiconductor chip may include a first through electrode connecting the first pad and the first bonding pad, a second through electrode connecting the second bonding pad and the connection pad, and a first connection pad connected to the first bonding pad. The semiconductor package further comprises a rewiring. The method of claim 1, The second semiconductor chip may include a third through electrode connecting the first bonding pad and the third bonding pad, a fourth through electrode connecting the first conductive member and the fourth bonding pad, and the third bonding pad. And a second redistribution connected to the semiconductor package. The method of claim 1, The third semiconductor chip may include a fifth through electrode connecting the third bonding pad and the fifth bonding pad, a sixth through electrode connecting the second conductive member and the sixth bonding pad, and the fifth bonding pad. And a third redistribution connected to the semiconductor package. The method of claim 1, The chip selection block comprises a ceramic package. The method of claim 1, And the first to third pads are chip select pads to which a chip select signal is applied. The method of claim 1, And a underfill member interposed between the substrate, the first semiconductor chip, the first semiconductor chip, and the second semiconductor chip.