KR100924750B1 - LCD and its manufacturing method - Google Patents

Abstract

According to the COT liquid crystal display including the top gate type thin film transistor according to the present invention and a method of manufacturing the same, by minimizing the bonding margin by the COT structure can increase the aperture ratio, and using a polysilicon thin film transistor to separate the upper substrate The black matrix pattern can be omitted, and since the black matrix is formed as a protective layer, a high opening ratio structure can be easily applied through the process simplification, thereby increasing the production yield.

Description

Liquid Crystal Display Device and Method for Fabricating the same             

1 is a view schematically showing a general liquid crystal display device.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1. FIG.

3 is a cross-sectional view of an array substrate for a liquid crystal display device including a conventional top gate type thin film transistor.

4 is a cross-sectional view of a substrate for a COT liquid crystal display device in a first embodiment of the present invention.

FIG. 5 is a process flowchart showing step by step a manufacturing process for a COT liquid crystal display according to a second embodiment of the present invention; FIG.

<Brief description of the main parts of the drawing>

110 substrate 112 buffer layer

114: semiconductor layer 116: first capacitor electrode

118 gate insulating film 120 gate electrode

122: second capacitor electrode 124: interlayer insulating film

126a, 126b, 126c: 1st, 2nd, 3rd contact hole                 

128: source electrode 130: drain electrode

132: auxiliary capacitor electrode 134: data wiring

136: black matrix 137: open

138: first transparent conductive layer 140: color filter layer

142: second transparent conductive layer 144: pixel electrode

Va, Vb, Vc: active region, source region, drain region

VIa, VIb: 1st, 2nd region

VII: Data Wiring and Black Matrix Overlap Area

C _ST : Storage capacitance P: Pixel area

T: thin film transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display (COT) structure liquid crystal display device having a structure of simultaneously forming a color filter layer on a substrate on which a thin film transistor is formed, and a manufacturing method thereof.

In general, a liquid crystal display device displays an image by using optical anisotropy and birefringence characteristics of liquid crystal molecules. When an electric field is applied, the alignment of liquid crystals is changed, and the characteristics of light transmission vary according to the arrangement direction of the changed liquid crystals.

In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying a voltage to the two electrodes. By moving the liquid crystal molecules by the electric field is a device that represents the image by the transmittance of light that varies accordingly.

1 is a view schematically showing a general liquid crystal display device.

As shown, a general color liquid crystal display device 11 includes a color filter 7 and a color filter 8 including a black matrix 6 formed between a sub color filter 8 and each sub color filter 8. The upper substrate 5 having the common electrode 18 deposited thereon, the pixel region P, and the pixel electrode 17 and the switching element T formed in the pixel region, and the pixel region P The liquid crystal 14 is filled between the lower substrate 22 and the upper substrate 5 and the lower substrate 22 on which array wiring is formed.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 crosses the plurality of thin film transistors TFT. ) And data wirings 15 are formed.

In this case, the pixel area P is an area defined by the gate wiring 13 and the data wiring 15 intersecting. A transparent pixel electrode 17 is formed on the pixel area P as described above.                         

The pixel electrode 17 uses a transparent conductive metal having relatively high light transmittance such as indium-tin-oxide (ITO).

A storage capacitor C _ST connected in parallel with the pixel electrode 17 is formed on the gate wiring 13, and a part of the gate wiring 13 is used as the first electrode of the storage capacitor C _ST . As the second electrode, an island-shaped source / drain metal layer 30 formed of the same material as the source and drain electrodes is used.

In this case, the source / drain metal layer 30 is configured to be in contact with the pixel electrode 17 to receive a signal of the pixel electrode.

As described above, when the upper color filter substrate 5 and the lower array substrate 22 are bonded to each other to produce a liquid crystal panel, light leakage defects due to the bonding error between the color filter substrate 5 and the array substrate 22 may be reduced. It is very likely to occur.

A description with reference to FIG. 2 is as follows.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1.

As described above, the first substrate 22, which is an array substrate, and the second substrate 5, which is a color filter substrate, are spaced apart from each other, and the liquid crystal layer 14 is disposed between the first and second substrates 22, 5. This is located.

A thin film transistor T including a gate electrode 32, an active layer 34, a source electrode 36, and a drain electrode 38 is disposed on the first substrate 22, and an upper portion of the thin film transistor T. The protective film 40 is configured to protect it.

In the pixel region P, a transparent pixel electrode 17 is formed in contact with the drain electrode 38 of the thin film transistor T, and a storage capacitor C _ST connected in parallel with the pixel electrode 17 includes a gate wiring ( 13) is configured on the top.

A black matrix 6 is formed on the second substrate 5 to correspond to the gate wiring 13, the data wiring 15, and the thin film transistor T. The pixel region P of the first substrate 22 is formed. Correspondingly, the color filter 8 is configured.

In this case, the general first substrate 22 is configured such that the data line 15 and the pixel electrode 17 are spaced at a predetermined interval IIIa to prevent vertical cross talk, and the gate line 13 is disposed. ) And the pixel electrode are also configured to be spaced apart at a predetermined interval (IIIb).

Since the spaces A and B spaced apart between the data line 15 and the gate line 13 and the pixel electrode 17 are areas where light leakage occurs, a black matrix formed on the second substrate 5 is formed. (6) will cover this part.

In addition, the black matrix 6 formed on the thin film transistor T serves to block the light so that the light radiated from the outside does not affect the active layer 34 through the passivation layer 40. .

However, a misalignment may occur during the process of bonding the first substrate 5 and the second substrate 22. In consideration of this, a margin of a constant value is designed when designing the black matrix 6. Since the design is based on the margin, the aperture ratio decreases by that amount.

In addition, when the bonding error beyond the margin occurs, there is often a case of light leakage defects in which the light leakage regions IIIa and IIIb are not covered by the black matrix 6.

In this case, since the light leakage appears outside, there is a problem that the image quality is deteriorated.

In order to solve the above problems, it is an object of the present invention to provide a liquid crystal display device having a structure that can minimize the bonding margin to increase the transmittance.

To this end, the present invention is to provide a COT liquid crystal display device of a method of forming a color filter element on a substrate on which a thin film transistor is formed.

Another object of the present invention is to provide a COT liquid crystal display device having a process simplification structure.

To this end, in the present invention, a gate electrode is formed on a semiconductor layer made of polysilicon (p-Si), an impurity treatment is performed on both exposed sides of the semiconductor layer using the gate electrode as a mask, and the impurity treatment of the semiconductor layer is performed. A top gate type thin film transistor structure array element formed by a manufacturing process of forming a source electrode and a drain electrode in contact with a region, and in particular, the black layer of the color filter element without separately forming a protective layer for the top gate type thin film transistor. It is intended to simplify the process by forming the matrix as a protective layer combined with a light blocking pattern.

3 is a cross-sectional view of an array substrate for a liquid crystal display device including a conventional top gate type thin film transistor.

As illustrated, a buffer layer 52 is formed on the substrate 50, and the semiconductor layer 54 and the first capacitor electrode 56 are disposed to be spaced apart from each other, and the semiconductor layer 54 is disposed on the buffer layer 52. ) Is composed of an active region IIIa, a source region IIIb and a drain region IIIc positioned at the periphery of the active region IIIa. The first capacitor electrode 56 has a first region IVa and a first region IVa. The second region IVb is defined at both sides of the first region IVa, and the first region IVa substantially corresponds to the active region.

The material constituting the semiconductor layer 54 is selected from a polysilicon material, and the source region IIIb, the drain region IIIc, and the second region IVb correspond to an impurity treated region.

A gate insulating layer 58 is formed in a region covering the semiconductor layer 54 and the first capacitor electrode 56, and the gate electrode 60 is positioned at a position covering the active region IIIa on the gate insulating layer 58. The second capacitor electrode 62 is formed at a position covering the first region IVa above the gate insulating layer 58.

An interlayer insulating film 64 is formed at a position covering the gate electrode 60 and the second capacitor electrode 62, and the source region IIIb of the semiconductor layer 54 is formed in the interlayer insulating film 64 and the gate insulating film 58. ) And drain region IIIa and contact holes exposing any one second region IVb of first capacitor electrode 56 are formed.

For convenience of description, exposing the first contact hole 66a and the drain region IIIc to the contact hole exposing the source region IIIb of the semiconductor layer 54 is the second contact hole 66b and the second region. Exposing (IVb) is referred to as third contact hole 66c.

The source electrode 68 and the second contact connected to the source region IIIb through the first contact hole 66a on the interlayer insulating layer 64 including the first to third contact holes 66a, 66b, and 66c. A drain electrode 70 is formed to be connected to the drain region IIIc through the hole 66b, and an auxiliary capacitor electrode 72 is formed to be connected to the second region IVb through the third contact hole 66c. It is.

The data line 69 is formed in connection with the source electrode 68.

The drain contact hole 74 is formed at a position covering the source electrode 68, the drain electrode 70, and the auxiliary capacitor electrode 72, and exposes the drain electrode 70 and the auxiliary capacitor electrode 72. And a protective layer 78 having a capacitor contact hole 76. The drain electrode 70 and the auxiliary capacitor electrode are formed on the protective layer 78 through the drain contact hole 74 and the capacitor contact hole 76. A pixel electrode 80 connected to the 72 is formed.

The semiconductor layer 54, the gate electrode 60, the source electrode 68, and the drain electrode 70 form a thin film transistor T and become conductive as a voltage is applied through the auxiliary capacitor electrode 72. The region where the first capacitor electrode 56 and the second capacitor electrode 62 overlap each other forms a storage capacitance C _ST in a state where the gate insulating layer 58 is interposed therebetween.

In the present invention, to simplify the process by forming a liquid crystal display array substrate including a conventional top-gate thin film transistor in a COT structure.

In more detail, a top gate type thin film transistor structure is applied to a COT liquid crystal display, and at this time, by using a black matrix instead of an organic insulating layer used for improving the aperture ratio and a protective layer, the bonding margin of the COT structure is minimized and In addition to increasing the aperture ratio, it is possible to have an additional process simplification effect.

In order to achieve the above object, in a first aspect of the present invention, there is provided a semiconductor layer comprising polysilicon (p-Si) formed on a substrate; A gate electrode formed in a region covering a central portion of the semiconductor layer and a gate wiring connected to the gate electrode; A source electrode and a drain electrode connected to both sides of the semiconductor layer on the gate electrode, and a data line connected to the source electrode and intersecting the gate line; A first capacitor electrode formed of the same material as the semiconductor layer and spaced apart from each other; A second capacitor electrode made of the same material as the gate electrode so as to overlap with a central portion of the first capacitor electrode; A region where the gate line and the data line cross each other forms a pixel region, and the semiconductor layer, the gate electrode, the source electrode, and the drain electrode form a thin film transistor, and are formed at positions covering the boundary portion and the thin film transistor for each pixel region. A black matrix having an open portion at a position corresponding to the pixel region; A first transparent conductive layer formed in an area covering the black matrix and connected to the drain electrode; A color filter layer formed over the first transparent conductive layer and formed on the open part using the black matrix as a color boundary part; A pixel electrode formed on each of the pixel regions on the color filter layer, the pixel electrode including a first transparent conductive layer and a second transparent conductive layer connected to the first transparent conductive layer, and connected to the first transparent conductive layer Provided is a substrate for a COT liquid crystal display device including a capacitor electrode.
The pixel electrode is formed to overlap a neighboring data line at a predetermined interval, and the black matrix is formed to include a region covering the data line, and the material forming the black matrix is selected from the black resin.
In addition, the semiconductor layer region connected to the source electrode and the drain electrode corresponds to an impurity treated region, a gate insulating layer is interposed between the semiconductor layer and the gate electrode, and an interlayer is interposed between the gate electrode and the source electrode and the drain electrode. An insulating film is interposed, and contact holes exposing both sides of the semiconductor layer are formed in the interlayer insulating film and the gate insulating film.
In this case, the first capacitor electrode is made of the same material as the semiconductor layer, the second capacitor electrode is made of the same material as the gate electrode on the gate insulating film, the auxiliary capacitor electrode is the source electrode and the drain electrode The same material as is connected to one side of the first capacitor electrode, the overlapping region of the first and second capacitor electrode forms a storage capacitance.
In addition, a second aspect of the invention provides a method for forming a buffer layer on a substrate; Forming a semiconductor layer made of a polysilicon material on the buffer layer; Forming a first capacitor electrode spaced apart from the semiconductor layer; Forming a gate insulating film on the semiconductor layer; Forming a gate electrode overlapping the center portion of the semiconductor layer on the gate insulating layer and a gate wiring connected to the gate electrode; Forming a second capacitor electrode positioned at a central portion of the first capacitor electrode; Forming an interlayer insulating film in a region covering the gate electrode and the gate wiring; Forming first and second contact holes in the gate insulating film and the interlayer insulating film to partially expose both sides of the semiconductor layer; Forming a source electrode and a drain electrode connected to the semiconductor layer through the first and second contact holes, and a data line connected to the source electrode and intersecting the gate line on the interlayer insulating layer; Forming an auxiliary capacitor electrode connected to one side of the first capacitor electrode; A region where the gate line and the data line cross each other is defined as a pixel area, and the semiconductor layer, the gate electrode, the source electrode, and the drain electrode form a thin film transistor, and are located in an area covering the boundary portion and the thin film transistor for each pixel area. Forming a black matrix having a pixel area as an open part; Forming a first transparent conductive layer connected to the drain electrode in a region covering the black matrix; Forming a color filter layer on the open portion, using the black matrix as a color-specific boundary portion on the first transparent conductive layer; Forming a second transparent conductive layer connected to the first transparent conductive layer on the color filter layer, and patterning the first and second transparent conductive layers for each pixel region to form a pixel electrode And the first transparent conductive layer is connected to the auxiliary capacitor electrode, and wherein overlapping regions of the first and second capacitor electrodes form a storage capacitance. To provide.
In this case, the polysilicon material constituting the semiconductor layer is formed through a crystallization process using an amorphous silicon material, and the pixel electrode is formed to overlap with a neighboring data line at a predetermined interval, and the black matrix covers an area covering the data line. It is formed to include.
In the forming of the gate electrode, impurity treatment may be performed on both sides of the exposed semiconductor layer using the gate electrode as a mask.

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BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a COT structure liquid crystal display device and a method of manufacturing the same, which together form a color filter on an array substrate.

In addition, the present invention is characterized in that the color filter is formed on the array substrate having a top gate type thin film transistor, wherein the black matrix is used as a protective layer for the thin film transistor, so that the black matrix is light on the non-pixel region. In addition to the light blocking role of blocking the function of the organic insulating film used for the aperture ratio improving structure, the aperture ratio improving structure can be provided.

First Embodiment

4 is a cross-sectional view of a substrate for a COT liquid crystal display device according to a first embodiment of the present invention.

As illustrated, a buffer layer 112 is formed on the substrate 110, and the semiconductor layer 114 and the first capacitor electrode 116 are disposed on the buffer layer 112 so as to be spaced apart from each other, and the semiconductor layer 114. ) Is composed of an active region Va, a source region Vb and a drain region Vc positioned at the periphery of the active region Va. The first capacitor electrode 116 has a first region VIa and a first region. Second regions VIb are defined at both sides of the first region VIa, and the first region VIa substantially corresponds to the active region.

The material constituting the semiconductor layer 114 is selected from a polysilicon material, and the source region Vb and the drain region Vc and the second region VIb correspond to an impurity treated region.

A gate insulating layer 118 is formed in a region covering the semiconductor layer 114 and the first capacitor electrode 116, and the gate electrode 120 is positioned at a position covering the active region Va above the gate insulating layer 118. The second capacitor electrode 122 is formed at a position covering the first region VIa above the gate insulating layer 118.

Although not shown in the drawings, a gate wiring is formed in connection with the gate electrode 120.

An interlayer insulating layer 124 is formed at a position covering the gate electrode 120 and the second capacitor electrode 122, and the source region Vb of the semiconductor layer 114 is formed in the interlayer insulating layer 124 and the gate insulating layer 118. ) And the drain region Vc and contact holes exposing any one of the second regions VIb of the first capacitor electrode 116 are formed.

For convenience of description, exposing the first contact hole 126a and the drain region Vc to expose the contact hole exposing the source region Vb of the semiconductor layer 114 includes the second contact hole 126b and the second region. The contact hole exposing VIb is referred to as a third contact hole 126c.

The source electrode 128 and the second contact connected to the source region Vb through the first contact hole 126a on the interlayer insulating layer 124 including the first to third contact holes 126a, 126b, and 126c. A drain electrode 130 connected to the drain region Vc is formed through the hole 126b, and an auxiliary capacitor electrode 132 connected to the second region VIb is formed through the third contact hole 126c. It is.

The data line 134 is connected to the source electrode 128, and although not shown in the drawing, the data line 134 is formed to cross the gate line to define the pixel area P. Referring to FIG.

The semiconductor layer 114, the gate electrode 120, the source electrode 128, and the drain electrode 130 form a thin film transistor T. An upper portion of the thin film transistor T is disposed in an area covering the data line 134. The black matrix 136 is formed.

Although not shown in the drawing, the black matrix 136 is formed in an integrated pattern having an open portion 137 at a position surrounding the boundary portion of each pixel region P. Referring to FIG.

The first transparent conductive layer 138 is formed on the entire surface of the substrate covering the black matrix 136, and the color filter 140 is formed in the open part 137 using the black matrix 136 as a color-specific boundary. It is.

Although not shown in the drawings, the color filter 140 is formed by sequentially forming red, green, and blue color filters.

The first capacitor electrode 116, the second capacitor electrode 122, and the gate insulating layer 118 electrically connected to the first transparent conductive layer 138 through the auxiliary capacitor electrode 132 are interposed. The capacitance (C _ST ) is achieved.

In the drawing, it can be seen that the storage capacitor C _ST is provided in the first region VIa of the first capacitor electrode 116.

The second transparent conductive layer 142 is formed in an area covering the color filter 140, and the first and second transparent conductive layers 138 and 142 patterned for each pixel area P form the pixel electrode 144. Achieve.

In the COT liquid crystal display device including the top gate thin film transistor according to the present invention, since the polysilicon thin film transistor is used, unlike the amorphous silicon thin film transistor having an inverse staggered structure, the characteristic degradation due to light leakage current due to light inflow is reduced. Because of the relatively low, the additional black matrix process can be omitted.

However, the black matrix 136 according to the present invention is positioned in the region VII covering the data line 134, thereby minimizing the occurrence of parasitic capacitance between the pixel electrode 144 and the data line 134. It is important to do so.

Second Embodiment

5 is a process flowchart showing step by step a manufacturing process for a COT liquid crystal display according to a second embodiment of the present invention.                     

ST1 is a step of forming a buffer layer on a substrate and forming a semiconductor layer and a first capacitor electrode by using a polysilicon material on the buffer layer.

The semiconductor layer includes an active region in the center portion, source and drain regions on both sides, and a first capacitor electrode includes a first region in the center portion and a second region on both sides of the first region.

For example, the buffer layer and the amorphous silicon material may be continuously deposited, and then may be formed of polysilicon through laser crystallization and thermal crystallization through a dehydrogenation process.

Since the polysilicon has a high mobility characteristic, it is possible to minimize the deterioration of switching characteristics due to the light leakage current, so that a separate black matrix pattern may be omitted from the upper substrate.

In step ST2, a gate insulating film is formed in a region covering the semiconductor layer and the first capacitor electrode, and a second capacitor is positioned above the gate insulating film and covers the gate electrode and the first capacitor electrode at a position covering the active region. Forming an electrode.

In this step, using the gate electrode and the first capacitor electrode as a mask, the source region and the drain region of the exposed semiconductor layer and the second region of the second capacitor electrode are impurity treated with p-type ions or n-type ions. Steps.

The ST3 is positioned in a region covering the gate electrode and the first capacitor electrode, and exposes the first and second contact holes and the second region of the first capacitor electrode to expose the source region and the drain region of the semiconductor layer. Forming an interlayer insulating film having a third contact hole, a source electrode and a drain electrode contacting the source and drain regions of the semiconductor layer through the first and second contact holes on the interlayer insulating film, and a third contact hole; Forming the auxiliary capacitor electrode in contact with the second region of the first capacitor electrode through.

This step includes a step of hydrogenating the exposed semiconductor layer and the first capacitor electrode region before forming the source electrode and the drain electrode and the auxiliary capacitor electrode.

The semiconductor layer, the gate electrode, the source electrode, and the drain electrode form a thin film transistor.

In addition, a gate wiring is formed in a first direction by being connected to the aforementioned gate electrode, a data wiring is formed in a second direction which is connected with the source electrode, and is crossed in a first direction, and the gate wiring and the data wiring are crossed. An area is defined as a pixel area.

ST4 is a step of forming a black matrix in an area covering the boundary portion and the thin film transistor for each pixel region. In this step, the black matrix is formed in an integrated pattern with the pixel area as an open portion.

In particular, the black matrix is preferably formed in an area completely covering the data line.

The material constituting the black matrix is selected from an insulating material, preferably black resin.

ST5 is a step of forming a first transparent conductive layer as a thin film on the entire surface of the substrate covering the black matrix, ST6 is a red, green, blue color for each open part by using a black matrix as a color boundary on the first transparent conductive layer. The color filter layer is formed by sequentially forming the filters, and in step ST7, a second transparent conductive layer is formed on the entire upper surface of the color filter layer, and then a pixel electrode including the first and second transparent conductive layers is formed for each pixel region through a patterning process. Forming.

In this step, the pixel electrode may be formed to be spaced apart from a neighboring data line by a predetermined distance, and the parasitic capacitance between the two metal materials may be minimized by the aforementioned black matrix positioned between the data line and the pixel electrode.

That is, in the present invention, unlike the existing high-opening structure, the process can be simplified by using the black matrix as a protective layer for the high-opening structure.

As described above, according to the COT liquid crystal display device including the top gate type thin film transistor according to the present invention and a method of manufacturing the same, the COT structure minimizes the bonding margin to increase the aperture ratio, and by using the polysilicon thin film transistor, The separate black matrix pattern can be omitted, and since the black matrix is formed as a protective layer, a high opening ratio structure can be easily applied through the process simplification, thereby increasing the production yield.

Claims (11)

A semiconductor layer made of polysilicon (p-Si) formed on the substrate; A gate electrode formed in a region covering a central portion of the semiconductor layer and a gate wiring connected to the gate electrode; A source electrode and a drain electrode connected to both sides of the semiconductor layer on the gate electrode, and a data line connected to the source electrode and intersecting the gate line; A first capacitor electrode formed of the same material as the semiconductor layer and spaced apart from each other; A second capacitor electrode made of the same material as the gate electrode so as to overlap with a central portion of the first capacitor electrode; A region where the gate line and the data line cross each other forms a pixel region, and the semiconductor layer, the gate electrode, the source electrode, and the drain electrode form a thin film transistor, and are formed at positions covering the boundary portion and the thin film transistor for each pixel region. A black matrix having an open portion at a position corresponding to the pixel region; A first transparent conductive layer formed in an area covering the black matrix and connected to the drain electrode; A color filter layer formed over the first transparent conductive layer and formed on the open part using the black matrix as a color boundary part; A pixel electrode formed on each of the pixel regions on the color filter layer, the pixel electrode including a first transparent conductive layer and a second transparent conductive layer connected to the first transparent conductive layer; And a sub-capacitor electrode connected to the first transparent conductive layer. The method of claim 1, And the pixel electrode is formed to overlap a neighboring data line at a predetermined interval, and the black matrix includes a region covering the data line. The method of claim 1, The material forming the black matrix is a substrate for a COT liquid crystal display device selected from black resin. The method of claim 1, And a semiconductor layer region connected to the source electrode and the drain electrode corresponds to an impurity treated region. The method of claim 1, A gate insulating film is interposed between the semiconductor layer and the gate electrode, an interlayer insulating film is interposed between the gate electrode and the source electrode and the drain electrode, and a contact hole exposing both sides of the semiconductor layer in the interlayer insulating film and the gate insulating film. The formed substrate for COT liquid crystal display device. The method of claim 5, wherein The first capacitor electrode is made of the same material as the semiconductor layer, and the second capacitor electrode is made of the same material as the gate electrode on the gate insulating layer, and the auxiliary capacitor electrode is the same as the source electrode and the drain electrode. The substrate of claim 1, wherein the first capacitor electrode is connected to one side of the first capacitor electrode, and an overlapping region of the first and second capacitor electrodes forms a storage capacitance. Forming a buffer layer on the substrate; Forming a semiconductor layer made of a polysilicon material on the buffer layer; Forming a first capacitor electrode spaced apart from the semiconductor layer; Forming a gate insulating film on the semiconductor layer; Forming a gate electrode overlapping the center portion of the semiconductor layer on the gate insulating layer and a gate wiring connected to the gate electrode; Forming a second capacitor electrode positioned at a central portion of the first capacitor electrode; Forming an interlayer insulating film in a region covering the gate electrode and the gate wiring; Forming first and second contact holes in the gate insulating film and the interlayer insulating film to partially expose both sides of the semiconductor layer; Forming a source electrode and a drain electrode connected to the semiconductor layer through the first and second contact holes, and a data line connected to the source electrode and intersecting the gate line on the interlayer insulating layer; Forming an auxiliary capacitor electrode connected to one side of the first capacitor electrode; A region where the gate line and the data line cross each other is defined as a pixel area, and the semiconductor layer, the gate electrode, the source electrode, and the drain electrode form a thin film transistor, and are located in an area covering the boundary portion and the thin film transistor for each pixel area. Forming a black matrix having a pixel area as an open part; Forming a first transparent conductive layer connected to the drain electrode in a region covering the black matrix; Forming a color filter layer on the open portion, using the black matrix as a color-specific boundary portion on the first transparent conductive layer; Forming a second transparent conductive layer connected to the first transparent conductive layer on the color filter layer, and patterning the first and second transparent conductive layers for each pixel area to form a pixel electrode Wherein the first transparent conductive layer is connected to the auxiliary capacitor electrode, and wherein overlapping regions of the first and second capacitor electrodes form a storage capacitance. Way. The method of claim 7, wherein The polysilicon material constituting the semiconductor layer is a method of manufacturing a substrate for a COT liquid crystal display device formed by a crystallization process using an amorphous silicon material. The method of claim 7, wherein And the pixel electrode is formed to overlap a neighboring data line at a predetermined interval, and the black matrix is formed to include a region covering the data line. delete The method of claim 7, wherein In the gate electrode forming step, using the gate electrode as a mask, the method of manufacturing a substrate for a COT liquid crystal display device comprising impurity treatment of both sides of the exposed semiconductor layer.

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