KR100935582B1 - Semiconductor memory device with simplified signal wiring - Google Patents

Abstract

Disclosed are a semiconductor memory device having a simplified signal line that can secure a margin between signal lines provided outside the sense amplifier block. The disclosed invention includes a sense amplifier block comprising a first signal transfer unit for transmitting a signal to a lower bit line, and a second signal transfer unit for transferring a signal to a higher bit line. A single bit line select signal line for providing a predetermined signal is disposed outside the sense amplifier, and a pair of bit line select signals having a different phase may be formed between the single bit line select signal line and the sense amplifier. Signal branch units provided to each of the first signal transfer unit and the second signal transfer unit are connected.

Sense Amplifier, Wiring, Wiring Pitch, Bit Line Selection Signal (BISL, BISH)

Description

Semiconductor Memory Apparatus Having Simplified Signal Line

1 is a schematic diagram illustrating bit line selection signal wires of a conventional semiconductor memory device;

2 is a block diagram schematically illustrating a semiconductor memory device having a simplified bit line selection signal wiring according to an embodiment of the present invention;

3 is a detailed circuit diagram of a sense amplifier block provided with simplified bit line selection signal wiring according to an embodiment of the present invention;

4 is a plan view illustrating a bank of a semiconductor memory device to which a signal wiring structure of the semiconductor memory device according to an embodiment of the present invention is applied;

FIG. 5 is a block diagram schematically illustrating a semiconductor memory device having a simplified bit line selection signal wire according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: sense amplifier block 150: signal branch unit

170: buffer unit 200: mat

210: subword line block 220: subhole area

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a simplified signal wiring.

Dynamic random access memory (DRAM) devices in a semiconductor memory device output data stored in a memory cell to the outside by using a sense amplifier. The sense amplifier is connected to the bit line of the memory cell to determine memory cell data by comparing a bit level precharge voltage with a voltage level charged and shared by the bit line. Currently, the sense amplifier is connected to two memory blocks to selectively sense memory cells in one memory block.

The sense amplifier includes first and second signal transfers for selecting one of the two memory blocks. These first and second signal transfer sections are selectively driven by bit line select signal pairs BISH and BISL that are out of phase.

In more detail, as illustrated in FIG. 1, the bit line selection signals BISL and BISH may include the first and second bit line selection signal lines 20a, which are disposed outside the sense amplifier 10. 20b) to the sense amplifiers 10, respectively. In this case, an amplifier 30 is provided between the first and second bit line selection signal lines 20a and 20b and the sense amplifier 10, respectively, and has a predetermined level of bit line selection signals BISL and BISH. Is provided to the sense amplifier 10.

However, as is known, the general sense amplifier 10 needs at least 24 input signals, and these input signals should be provided to the sense amplifier 10 through signal wires arranged outside the sense amplifier 10. Therefore, at least 24 signal wires are arranged outside the sense amplifier 10.

Furthermore, as the integration density of the semiconductor memory device decreases exponentially, the area of the outer area of the sense amplifier 10, that is, the space between the mats including the sense amplifier is also decreasing, while the number of signal wires is increasing or increasing. Therefore, the line width and spacing of the signal wires should be reduced.

When the line width and spacing of the signal wires are reduced in this way, the wiring resistance is increased to increase the signal delay time and cause coupling with the adjacent signal wiring.

Accordingly, an object of the present invention is to provide a semiconductor memory device having a simplified signal wiring that can secure the margin between signal wirings provided outside the sense amplifier.

In order to achieve the above object of the present invention, the semiconductor memory device of the present invention, the first signal transmission unit for receiving a signal to be provided to the lower bit line, and the second signal transmission for receiving a signal to be provided to the upper bit line A plurality of sense amplifier blocks comprising a portion; A single bit line select signal line disposed outside the plurality of sense amplifier blocks and transferring a lower bit line signal of a first level; Receiving the lower bit line signal from the single bit line selection signal line, generating an upper bit line signal having a second level opposite to the first level, and buffering the lower bit line signal, And a signal branch unit configured to provide the lower bit line signal to the first signal transfer unit and to provide the upper bit line signal to the second signal transfer unit.

A semiconductor memory device according to another embodiment of the present invention may include a memory bank including a plurality of mats, a sense amplifier block disposed at an edge of each mat, and sub-hole regions located at both sides of the sense amplifier block; A single bit line select signal wire disposed outside the sense amplifier block and transferring any one of a lower bit and an upper bit line select signal; And an upper bit line selection signal and a lower bit line selection signal having opposite phases, by being connected between the bit line selection signal line and the sense amplifier block to branch signals transmitted from the single bit line selection signal line. And a bit line selector configured to generate and provide the same to the sense amplifier block, wherein the bit line selector is disposed in the subhole region.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

The present embodiment provides a semiconductor memory device for reducing the number of signal wires arranged outside the sense amplifier to secure a margin between the signal wires. In this embodiment, the upper bit line selection signal wiring and the lower bit line selection signal wiring are integrated into one bit line selection signal wiring, and a signal branch unit is provided in the subhole area instead. The signal branch unit inverts the signal provided to the bit line select signal line and provides the sense amplifier to the sense amplifier, thereby eliminating the need for a separate line. Accordingly, since one wiring is reduced in the region where the wiring is formed, line width and spacing between the wirings can be secured, and further, the area of the region where the wiring is formed can be reduced. In addition, in the present exemplary embodiment, a signal branch unit may be referred to as a bit line selection unit as a unit providing a signal to an upper bit line selection signal and a lower bit line selection signal.

This semiconductor memory device will be described in more detail as follows.

Referring to FIG. 2, a single bit line selection signal wire 120 is disposed outside the sense amplifier block 100, and a signal branch unit is disposed between the sense amplifier block 100 and the single bit line selection signal wire 120. 160 is provided. In the present embodiment, the bit line selection signal line 120 may be applied with a BISL signal, which is a signal for selecting a bit line of a lower mat (hereinafter, referred to as a lower bit line selection signal). In this case, the bit line selection signal may be a programmed signal provided from the outside.

As illustrated in FIG. 3, the sense amplifier block 100 includes a first equalizing unit 110, a precharge unit 120, an amplifying unit 130, a second equalizing unit 140, and a data transfer unit 150. It can be composed of).

The first equalizing unit 110 equalizes the bit line of the upper mat and the bit line bar / BL. The first equalizing unit 110 may be composed of a first NMOS transistor N1 and a first signal transfer unit 113. The first NMOS transistor N1 is turned on by the bit line equalizing signal BLEQ to connect the bit line BL and the bit line bar / BL. The first signal transfer unit 113 includes second and third NMOS transistors N2 and N3 for switching data of the bit line pair of the upper mat. The second NMOS transistor N2 may include a gate configured to receive a selection line (hereinafter, referred to as an upper bit line selection signal BISH), a drain connected to the bit line BL, and a precharging unit. 120) is connected to a source. The third MOS transistor N3 includes a gate configured to receive an upper bit line selection signal BISH, a drain connected to the bit line bar / BL, and a source connected to the precharging unit 120.

The precharging unit 120 is composed of fourth and fifth NMOS transistors N4 and N5 connected in series between the bit line BL and the bit line bar / BL. The fourth NMOS transistor N4 includes a gate that receives the bit line equalizing signal BLEQ, a source connected to the bit line BL, and a drain connected to the fifth NMOS transistor N5. The fifth NMOS transistor N5 includes a gate receiving the bit line equalizing signal BLEQ, a drain connected to the fourth NMOS transistor, and a source connected to the bit line bar / BL. A VBLP voltage is input at the connection node of the fourth NMOS transistor N4 and the fifth NMOS transistor N5 to precharge the bit line BL and the bit line bar / BL.

The sense amplification unit 130 sense-amplifies the potential difference between the bit lines BL and / BL in the sense amplifier S / A. The sense amplifying unit 230 is composed of a pair of inverters I11 and I12 connected in a latch form. The inverter is a CMOS inverter composed of PMOS transistors P11 and P12 and NMOS transistors N11 and N12 as is well known.

The second equalizing unit 140 equalizes the bit line BL and the bit line bar / BL positioned on the lower mat. The second equalizing unit 140 may include a sixth NMOS transistor N6 and a second signal transfer unit 143 that substantially equalize the bit line BL and the bit line bar / BL of the lower mat. have. Like the first NMOS transistor N1, the sixth NMOS transistor N6 is connected between the bit line BL and the bit line bar / BL and is turned on by the bit line equalizing signal. Similarly to the first signal transfer unit 113, the second signal transfer unit 143 includes seventh and eighth NMOS transistors N7 and N8 driven by the lower bit line selection signal BISL.

The data transfer unit 150 transfers the signals of the amplified bit line pairs BL and / BL to the data line pairs SIO and / SIO when the Yi signal is input for data output. The data transfer unit 150 may be composed of ninth and tenth NMOS transistors N9 and N10. The ninth NMOS transistor N9 includes a gate configured to receive a Yi signal, a drain connected to the bit line BL, and a source connected to the data line bar / SIO. The tenth NMOS transistor N10 includes a gate configured to receive a Yi signal, a drain connected to the bit line bar / BL, and a source connected to the data line SIO.

Meanwhile, the signal branch unit 160 generates lower and upper bit line selection signals BISL and BISH having opposite phases from one bit line selection signal line 120. As illustrated in FIG. 2, the signal branch unit 160 may be configured of a first inverter IN1 and a second inverter IN2, and the first inverter IN1 and the second inverter IN2 may be formed as shown in FIG. 2. Connected in series. Here, the output terminal op1 of the first inverter IN1 is electrically connected to the gate G1 of the first signal transfer unit 113 of the sense amplifier 100, and the output terminal of the second inverter IN2 ( op2 is connected to the gate G2 of the second signal transfer unit 143.

Meanwhile, the single bit line selection signal line 120 may further include a buffer unit 170 as shown in FIG. 2. The buffer unit 170 serves to buffer the bit line selection signal provided to the bit line selection signal line 120 together with the signal branch unit 160 to have a constant level. In the present embodiment, the buffer unit 170 may be configured as an inverter IN3.

4 is a plan view illustrating a bank of a semiconductor memory device to which a signal wiring structure of the semiconductor memory device according to an exemplary embodiment of the present invention is applied.

Referring to FIG. 4, the memory bank 300 includes a plurality of mats MATs 200 arranged in a matrix form. Each mat 200 includes a sense amplifier block S / A: 100 positioned at one edge, and a subword line block SWL 210 positioned at an edge orthogonal to a surface on which the sense amplifier block 100 is located. ) And a sub hole region 220 positioned near each intersection point of the sense amplifier block 100 and the sub word line block 210. In the figure, MH represents the upper mat row and ML represents the lower mat row. The upper mat row MH and the lower mat row ML may be spaced apart from each other by a predetermined interval. In addition, the sense amplifier block 100 is involved in driving the lower bit line portion of the upper mat 200H and the upper bit line portion of the lower mat 200L.

A plurality of signal wires L for transmitting signals to the sense amplifier block 100 and each mat 200 are disposed between the mat columns MH and ML. Among the signal wires L, signal wires for driving the first and second signal transfer parts 113 and 143 of the sense amplifier block 100, that is, the bit line selection signal wires, are also included.

The conventional bit line selection signal wiring is composed of an upper bit line selection signal wiring and a lower bit line selection signal wiring to select the upper mat 200H and the lower mat 200L.

However, in the present exemplary embodiment, only one bit line selection signal line is disposed in the space between the mat columns MH and ML, and the signal BISH to be transmitted to the first signal transfer unit 113 by the signal branch unit 160. ) And a signal BISL to be transmitted to the second signal transmission unit 143.

Therefore, the number of signal wires formed between the mat columns MH and ML is reduced. As a result, a margin equal to the pitch (sum of line width and spacing) of the signal wiring is secured in the space between the mat columns MH and ML.

In addition, the signal branch unit 160 is disposed in the subhole region 220 having a relatively low integration density. Accordingly, a separate area for forming the signal branch unit 160 is not required.

The semiconductor memory device of this embodiment as described above is driven as follows.

First, when the lower bit line selection signal BISL is input to the bit line selection signal line 120, the lower bit line selection signal BISL is first inverted and amplified through the buffer unit 170.

The inverted lower bit line selection signal / BISL is then input to the signal branch unit 160.

The inverted lower bit line selection signal / BISL input to the signal branch unit 160 is inverted again by the first inverter IN1 to generate a buffered lower bit line selection signal BISL, which is then buffered. The lower bit line selection signal BISL is provided to the gate G1 of the first signal transfer unit 113 of the sense amplifier block 100.

In addition, the buffered lower bit line selection signal BISL is inverted again by the second inverter IN2 to generate an inverted lower bit line selection signal that is buffered, that is, an upper bit line selection signal BISH. The buffered upper bit line select signal BISH is provided to the gate G2 of the second signal transfer unit 143 of the sense amplifier block 100.

According to the present exemplary embodiment, two bit line selection signals BISL, which are different in phase by only one signal wire 120, by the signal branch unit 160 including the inverters IN1 and IN2 connected in series. BISH) can be generated. As a result, the number of signal wirings arranged between the mat columns can be reduced, and the margin of one wiring pitch can be ensured in the space between the mat rows.

Therefore, the space | interval and line | wire width between wiring which remain in the space | interval between mat rows can be ensured enough, and wiring resistance can be reduced. In addition, the spacing between mat rows can be reduced by one wiring pitch margin. In addition, since the reduction of the signal wiring occurs for each mat column, the area of the entire memory bank can be reduced.

In the present embodiment, the case where the lower bit line selection signal BISL is input to the single bit line selection signal line 120 has been described. However, the upper bit line selection signal BISH may be input to the single bit line selection signal line 120 instead of the lower bit line selection signal BISL. In this case, as shown in FIG. 5, the output signal of the first inverter IN1 of the signal branch unit 160 is provided to the gate G2 of the second signal transmission unit 143, and the second inverter IN2 is provided. The position of the connection line 180 may be changed such that the output signal of the N-th input signal is provided to the gate G1 of the first signal transfer unit 113.

Experimental Example

Table 1 shows a signal delay time of a bit line selection signal according to an embodiment of the present invention.

Table 1

Rising Delay (ps) Delay time when polling (ps) BISH 25 16 BISL 55 44

In the case of using two bit line select signal wires as in the related art, each bit line select signal delay time is about 60 ps for both rising and falling.

However, in the case where the signal branch unit 160 is provided while using a single bit line selection signal wiring as in the present embodiment, the line width of the bit line selection signal wiring can be increased, so that the upper bit line selection signal BISH can be used. The delay time during rising and polling was reduced to 25ps and 16ps, respectively, and the delay time during rising and polling of the lower bit line select signal BISL was reduced by 55ps and 44ps, respectively.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. Do.

As described in detail above, according to the present invention, two bit line selection signals having different phases may be generated by only one signal wire by a signal branch unit including inverters connected in series. As a result, the number of signal wires arranged between the mat columns can be reduced.

Therefore, the line width and spacing between the signal lines arranged between the mat rows can be increased, or the spacing between the mat rows can be reduced by the pitch of the reduced wiring.

Claims (13)

A plurality of sense amplifier blocks comprising a first signal transfer unit receiving a signal to be provided to a lower bit line, and a second signal transfer unit receiving a signal to be provided to an upper bit line; A single bit line select signal line disposed outside the plurality of sense amplifier blocks and transferring a lower bit line signal of a first level; And Receiving the lower bit line signal from the single bit line selection signal line, generating an upper bit line signal having a second level opposite to the first level, and buffering the lower bit line signal, And a signal branch unit configured to provide the lower bit line signal to a first signal transfer unit, and provide the upper bit line signal to the second signal transfer unit. The method of claim 1, The signal branch unit includes a first inverter and a second inverter connected in series. The method of claim 2, An output signal of the first inverter is provided to a first signal transfer unit, And an output signal of the second inverter is provided to a second signal transfer unit. The method of claim 2, An output signal of the first inverter is provided to a second signal transmission unit, And an output signal of the second inverter is provided to the first signal transfer unit. The method according to claim 3 or 4, The first and second signal transmission section is composed of a MOS transistor, Output signals of the first inverter and the second inverter are respectively provided to gates of MOS transistors constituting the first and second signal transfer units. The method of claim 1, And a buffering unit for inverting and amplifying the input signal in the bit line selection signal line. The method of claim 1, And a signal input to the bit line selection signal line is a lower bit line selection signal or an upper bit line selection signal programmed from the outside. The method of claim 1, An upper mat row and a lower mat row composed of a plurality of mats, The sense amplifier block is disposed between the mat of the upper mat row and the mat of the lower mat row corresponding thereto. delete The method of claim 8, A sub word line block disposed at the mat edge orthogonal to an edge at which the sense amplifier block is located; And And a sub hole area positioned near an intersection point of the sense amplifier block and the sub word line block. And the signal branch unit is disposed in the sub hole area. A memory bank including a plurality of mats, a sense amplifier block disposed at an edge of each mat, and sub-hole regions located at both sides of the sense amplifier block; A single bit line select signal wire disposed outside the sense amplifier block and transferring any one of a lower bit and an upper bit line select signal; And Connected between the bit line select signal line and the sense amplifier block to branch a signal transmitted from the single bit line select signal line to generate an upper bit line select signal and a lower bit line select signal having opposite phases to each other; And a bit line selector configured to provide the sense amplifier block to the sense amplifier block. The bit line selector is disposed in the subhole area. The method of claim 11, The sense amplifier block includes a first signal transfer unit for transmitting a signal to a lower bit line of the mat, and a second signal transfer unit for transferring a signal to an upper bit line of the mat, The first and second signal transmission unit is composed of a MOS transistor, And the bit line selector to provide a signal having a different phase to the gate of the first signal transfer unit and the gate of the second signal transfer unit. The method of claim 11, The bit line selector includes a first inverter and a second inverter connected in series. An output signal of the first inverter is provided to the first signal transfer unit, And an output signal of the second inverter is provided to the second signal transfer unit.

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