KR100947770B1 - LCD and its driving method - Google Patents

Abstract

 The present invention relates to a liquid crystal display device, comprising: a frame memory for storing pixel data of a previous frame; A comparator for comparing pixel data of the previous frame input from the frame memory with pixel data of the current frame currently input and outputting a difference value; A data modulator configured to generate modulated pixel data by modulating pixel data of the current frame according to a difference value from the comparator; A data driver converting the modulated pixel data into an auxiliary pixel signal in an analog form and converting the pixel data of the current frame into an analog main pixel signal to supply data lines of the liquid crystal panel; A gate driver supplying a scan signal to gate lines of the liquid crystal panel; And a timing controller for supplying the modulated pixel data from the data modulator and pixel data of the current frame to the data driver, and controlling driving timings of the gate driver and the data driver.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF DIRVING THE SAME}             

1 is a view schematically showing a conventional liquid crystal display device.

2 is a charging characteristic diagram of the liquid crystal cell shown in FIG.

3 is a schematic view of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a charging characteristic diagram of the liquid crystal cell shown in FIG. 3.

FIG. 5 is a block diagram illustrating a detailed configuration of a data modulator shown in FIG. 3. FIG.

<Description of Symbols for Main Parts of Drawings>

2, 12: liquid crystal panel 4, 14: gate driver

6, 16: data driver 8, 18: timing control unit

20: data modulator 22: frame memory

24: Comparator 26: Data Modulator

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of improving the response speed of liquid crystals.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel having a pixel matrix and a driving circuit for driving the liquid crystal display panel.

Specifically, the liquid crystal display includes a liquid crystal panel 2 having a pixel matrix as shown in FIG. 1, a gate driver 4 for driving gate lines GL0 to GLn of the liquid crystal panel 2, A data driver 6 for driving the data lines DL1 to DLm of the liquid crystal panel 2, and a timing controller 8 for controlling the driving timing of the gate driver 4 and the data driver 6. do.

The liquid crystal panel 2 includes a pixel matrix composed of pixels formed at regions defined by intersections of the gate lines GL and the data lines DL. Each of the pixels includes a liquid crystal cell Clc for adjusting light transmittance according to a pixel signal, and thin film transistors TFT for driving the liquid crystal cell Clc.

The thin film transistor TFT is turned on when the scan signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data line DL to the liquid crystal cell Clc. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell Clc.

The liquid crystal cell Clc is equivalently represented by a capacitor and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell Clc further includes a storage capacitor Cst so that the charged pixel signal is stably maintained until the next pixel signal is charged. In the liquid crystal cell Clc, an array state of liquid crystals having dielectric anisotropy varies according to pixel signals charged through the thin film transistor TFT, thereby adjusting grayscale.

The gate driver 4 shifts the gate start pulse GSP from the timing controller 8 according to the gate shift clock GSC to sequentially gate the gate lines GL1 to GLm. Supply a scan pulse of high voltage (VGH). The gate driver 14 supplies the gate low voltage VGL to the gate lines GL in the remaining periods during which the scan pulse of the gate high voltage VGH is not supplied. In addition, the gate driver 4 controls the pulse width of the scan pulse according to a gate output enable signal (hereinafter referred to as a GOE) signal from the timing controller 8. The gate driver 4 includes a plurality of gate drive ICs (Integrated Circuits) for dividing and driving the gate lines GL0 to DLn.

The data driver 6 generates a sampling signal by shifting the source start pulse (hereinafter referred to as SSP) from the timing controller 8 according to the source shift clock (hereinafter referred to as SSC). do. In addition, the data driver 6 latches the pixel data RGB according to the SSC according to the sampling signal and then lines by line in response to a source output enable signal (SOE). Supply. The data driver 6 converts pixel data RGB, which is supplied in units of lines, into analog pixel signals using different gamma voltages, and supplies them to the analog pixel signals and supplies them to the data lines DL1 through DLm. Here, the data driver 6 determines the polarity of the pixel signal in response to the polarity control (hereinafter referred to as POL) signal from the timing controller 8 when converting the pixel data into the pixel signal. The data driver 6 determines a period in which the pixel signal is supplied to the data lines DL1 to DLm in response to the SOE signal. The data driver 6 includes a plurality of data drive ICs for dividing and driving the data lines DL1 to DLm.

The timing controller 8 generates GSP, GSC, GOE signals, etc. for controlling the gate driver 4, and generates SSP, SSC, SOE, POL signals, etc., for controlling the data driver 6. In this case, the timing controller 8 transmits a data enable (DE) signal, a horizontal sync signal (Hsync), a vertical sync signal (Vsync), and pixel data (RGB) indicating a valid data section input from the outside. Control signals such as the GSP, GSC, GOE, SSP, SSC, SOE, and POL are generated by using a dot clock (DCLK) that determines timing.

FIG. 2 is a waveform diagram illustrating charging characteristics of a pixel signal in an arbitrary liquid crystal cell Clc illustrated in FIG. 1.                         

Referring to FIG. 2, an arbitrary liquid crystal cell Clc has a gate high voltage VGH in one horizontal period and a gate low voltage VGL in another horizontal period in a gate line GL connected through a thin film transistor TFT. Is supplied with a gate signal (G). In addition, the data signal DL whose liquid crystal cell Clc is connected through the thin film transistor TFT has a pixel signal alternately alternating positive and negative polarities based on a common voltage Vcom. D) is supplied. Accordingly, the liquid crystal cell Clc receives the rising period of the positive pixel signal D supplied to the data line DL through the thin film transistor TFT turned on by the gate high voltage VGH. And is charged. The voltage Vp charged in the liquid crystal cell Clc maintains the charging voltage level during the period in which the thin film transistor TFT is turned off by the gate low voltage VGL. In this case, at the point where the gate high voltage VGH drops to the gate low voltage VGL, the voltage Vp charged in the liquid crystal cell is reduced by the feed through voltage ΔVp. The reduced charging voltage Vp of the liquid crystal cell Clc is maintained until a new pixel signal is supplied in the next frame.

On the other hand, the liquid crystal has a disadvantage in that the response speed is slow due to intrinsic viscosity, elasticity, and the like as can be seen in the following equation (1).

는 액정 분자의 회전점도(Rotational Viscosity)를, d는 액정셀(Clc)의 셀갭을,

은 액정의 유전율을, V는 인가 전압을, Vth는 액정 분자가 경사운동을 하는 프리드릭 천이 전압(Freederick Transition Voltage)을 의미한다.Here, τ is a rising time (RS) for the liquid crystal to respond to the applied voltage,

Is the rotational viscosity of the liquid crystal molecules, d is the cell gap of the liquid crystal cell (Clc),

Denotes the dielectric constant of the liquid crystal, V denotes the applied voltage, and Vth denotes the Freederick Transition Voltage in which the liquid crystal molecules tilt.

Accordingly, although the response speed of the liquid crystal having an inverse relationship with the rising time (τ) of the liquid crystal may vary depending on the properties of the liquid crystal material and the distance between the electrodes, the voltage V applied to the liquid crystal, that is, the liquid crystal cell It has a proportional relationship with the voltage Vp. However, in general, as the output voltage of the pixel signal supplied from the data driver 6 to the data line DL is relatively low, the response speed of the liquid crystal is slow. For example, the rising time τ of the TN mode liquid crystal is usually 20-80 ms. Since the rising time τ of the liquid crystal is longer than one frame period (NTSC: 16.67 ms) of the video, the voltage of the next frame is applied before the liquid crystal reacts as desired according to the voltage applied in the current frame. In particular, when the video is displayed, a motion blurring phenomenon occurs in which the screen is blurred.

In particular, when the pixel signal voltage difference between the frames is relatively small, the liquid crystal response speed is slow, and when the pixel signal voltage is relatively large, the liquid crystal response speed is high.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof which can improve the liquid crystal response speed by using an impulse voltage according to the pixel signal voltage difference between frames.

In order to achieve the above object, the liquid crystal display according to the present invention comprises a frame memory for storing the pixel data of the previous frame; A comparator for comparing pixel data of the previous frame input from the frame memory with pixel data of the current frame currently input and outputting a difference value; A data modulator configured to generate modulated pixel data by modulating pixel data of the current frame according to a difference value from the comparator; A data driver converting the modulated pixel data into an auxiliary pixel signal in an analog form and converting the pixel data of the current frame into an analog main pixel signal to supply data lines of the liquid crystal panel; A gate driver supplying a scan signal to gate lines of the liquid crystal panel; And a timing controller for supplying the modulated pixel data from the data modulator and pixel data of the current frame to the data driver, and controlling driving timings of the gate driver and the data driver.
The data driver sequentially supplies the auxiliary pixel signal and the main pixel signal to the data line while the thin film transistor is turned on by the scan signal.
The auxiliary pixel signal has a voltage greater than or equal to the main pixel signal.
The data modulator generates the modulated pixel data corresponding to an auxiliary pixel signal of a relatively small voltage when the difference value from the comparator is large, and corresponds to an auxiliary pixel signal of a relatively large voltage when the difference value is small. Generate the modulated pixel data.
A method of driving a liquid crystal display according to the present invention includes storing pixel data of a previous frame in a frame memory; Comparing pixel data of the previous frame input from the frame memory with pixel data of the current frame currently input and outputting a difference value; Generating modulated pixel data by modulating pixel data of the current frame according to the difference value; Converting the modulated pixel data into an auxiliary pixel signal in an analog form and converting the pixel data of the current frame into an analog main pixel signal and supplying the same to the data lines of a liquid crystal panel; And supplying a scan signal to gate lines of the liquid crystal panel.
Other objects and advantages of the present invention in addition to the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

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Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 5.

3 is a plan view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

The liquid crystal display shown in FIG. 3 includes a liquid crystal panel 12 having a pixel matrix, a gate driver 14 for driving gate lines GL0 to GLn of the liquid crystal panel 12, and a liquid crystal panel 12. A data driver 16 for driving the data lines DL1 to DLm of the second component, a timing controller 18 for controlling the driving timing of the gate driver 14 and the data driver 16, and pixel data between the frames. And a data modulator 20 for generating the modulated data D and supplying the modulated data D to the timing controller 18.

The liquid crystal panel 12 includes a pixel matrix composed of pixels formed at respective regions defined by intersections of the gate lines GL and the data lines DL. Each of the pixels includes a liquid crystal cell Clc for adjusting light transmittance according to a pixel signal, and thin film transistors TFT for driving the liquid crystal cell Clc.

The gate lines GL1 to GLn turn on the thin film transistor TFT by supplying a scan pulse of the gate high voltage VGH from the gate driver 12. The gate lines GL1 to GLn supply the gate low voltage VGL from the gate driver 12 to turn off the thin film transistor TFT.

The data lines DL1 to DLm supply the pixel signal from the data driver 24. In particular, each of the data lines DL1 to DLm includes a pixel signal PS including an auxiliary pixel signal APS and a main pixel signal MPS as shown in FIG. 4 in a horizontal period in which the gate high voltage VGH is supplied. ) Is supplied to the data lines DL1 to DLm.

The thin film transistor TFT is turned on by the gate high voltage VGH of the gate line GL to supply the auxiliary pixel signal APS and the main pixel signal MPS sequentially supplied from the data line DL. (Clc) and turned off by the gate low voltage (VGL) to maintain the pixel signal charged in the liquid crystal cell (Clc).

The liquid crystal cell Clc is equivalently represented by a capacitor and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell Clc further includes a storage capacitor Cst so that the charged pixel signal is stably maintained until the next pixel signal is charged. The liquid crystal cell Clc charges the auxiliary pixel signal APS supplied with a relatively high voltage through the turned-on thin film transistor TFT and then charges the main pixel signal MPS. Done. In this case, as shown in FIG. 4, the area of the voltage Vp charged in the liquid crystal cell Clc increases in the auxiliary pixel signal APS having a relatively high voltage. In particular, the size of the auxiliary pixel signal MPS depends on the voltage difference between the main pixel signal MPS charged in the previous frame and the main pixel signal MPS to be charged in the current frame. For example, when the voltage difference between the main pixel signals MPS of two frames is small, the size of the auxiliary pixel signal MPS is set to be large, and when the voltage difference is large, the size of the auxiliary pixel signal MPS is set to be small. Accordingly, since the driving voltage of the liquid crystal cell Clc is increased, the rising time τ of the liquid crystal is reduced by the relationship as shown in Equation 1, thereby improving the liquid crystal response speed.

In the liquid crystal cell Clc, the arrangement state of the liquid crystal having the dielectric anisotropy varies according to the charged voltage Vp, thereby adjusting the light transmittance to realize gray scale.

The gate driver 14 shifts the gate start pulse GSP from the timing controller 18 according to the gate shift clock GSC to sequentially scan the gate high voltage VGH to the gate lines GL1 to GLm. To supply. The gate driver 14 supplies the gate low voltage VGL to the gate lines GL in the remaining periods during which the scan pulse of the gate high voltage VGH is not supplied. In addition, the gate driver 14 controls the pulse width of the scan pulse according to the gate output enable (GOE) signal from the timing controller 8.

The data driver 16 shifts the source start pulse SSP from the timing controller 18 in accordance with the source shift clock SSC to generate a sampling signal. Then, the data driver 16 latches the modulated pixel data MD input in accordance with the SSC and the normal pixel data D of the current frame to be displayed on the liquid crystal panel 12 according to the sampling signal, and then outputs the source output. Supply line by line in response to SOE signal. The data driver 16 converts the modulation pixel data MD supplied in units of lines into analog auxiliary pixel signals APS using different gamma voltages, and converts the normal pixel data D to be displayed in the current frame into the analog main. The signal is converted to the pixel signal MPS and supplied to the data lines DL1 to DLm. Here, the data driver 16 controls the polarity control from the timing controller 18 when converting the modulated pixel data MD and the normal pixel data D into the auxiliary pixel signal APS and the main pixel signal MPS. In response to the POL signal, polarities of the pixel signals APS and MPS are determined. The data driver 16 supplies the auxiliary pixel signal APS to the data lines DL1 to DLm in response to the SOE signal, and then supplies the main pixel signal MPS to the data lines DL1 to DLm. Supplies).

The timing controller 18 generates a gate control signal GCS including the GSP, GSC, and GOE signals for controlling the gate driver 14, and the SSP, SSC, SOE, and POL signals for controlling the data driver 16. Generate a data control signal DCS including the like. In this case, the timing controller 18 transmits a data enable (DE) signal, a horizontal sync signal (Hsync), a vertical sync signal (Vsync), and pixel data (RGB) indicating a valid data section input from the outside. Control signals such as the GSP, GSC, GOE, SSP, SSC, SOE, and POL are generated by using a dot clock (DCLK) that determines timing. The timing controller 18 aligns the modulated pixel data MD input from the data modulator 20 and the normal pixel data D of the current frame input from the outside to the data driver 16.

The data modulator 20 compares the pixel data of the previous frame with the pixel data of the current frame and generates modulation pixel data MD having different sizes according to the difference, and supplies the same to the timing controller 18.

To this end, as illustrated in FIG. 5, the data modulator 20 includes a frame memory 22 storing data of a previous frame, a previous frame pixel data D ′ from the frame memory 22, and a current frame. A comparator 24 for comparing the pixel data D and a data modulator 26 for modulating the pixel data D of the current frame according to the output of the comparator and supplying the modulated pixel data MD to the timing controller 18. ).

The frame memory 22 stores pixel data of the previous frame.

The comparator 24 compares the pixel data D 'of the previous frame with the pixel data D of the current frame from the frame memory 22 and outputs a difference value.

The data modulator 26 modulates and outputs data D of the current frame according to the difference value output from the comparator 24. For example, when the difference value of the comparator 24 is small, the data modulator 26 converts the data D of the current frame into modulated data MD to be converted into a relatively large auxiliary pixel signal APS. On the other hand, when the difference value of the comparator 24 is large, the data modulator 26 converts the data D of the current frame into modulated data MD to be converted into a relatively small auxiliary pixel signal APS. In this case, the modulation data MD is set such that the minimum value of the auxiliary pixel signal APS is greater than or equal to the corresponding main pixel signal MPS.

As described above, the liquid crystal display and the driving method thereof according to the present invention can increase the charging voltage of the liquid crystal cell by charging the auxiliary pixel signal determined according to the pixel signal voltage difference between the frames before the main pixel signal. Accordingly, the liquid crystal display device and the driving method thereof according to the present invention can improve the liquid crystal response speed.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A frame memory for storing pixel data of a previous frame; A comparator for comparing pixel data of the previous frame input from the frame memory with pixel data of the current frame currently input and outputting a difference value; A data modulator configured to generate modulated pixel data by modulating pixel data of the current frame according to a difference value from the comparator; A data driver converting the modulated pixel data into an auxiliary pixel signal in an analog form and converting the pixel data of the current frame into an analog main pixel signal to supply data lines of the liquid crystal panel; A gate driver supplying a scan signal to gate lines of the liquid crystal panel; And And a timing controller for supplying the modulated pixel data from the data modulator and pixel data of the current frame to the data driver, and controlling driving timings of the gate driver and the data driver. The method of claim 1, The data driver And the auxiliary pixel signal and the main pixel signal are sequentially supplied to the data line while the thin film transistor is turned on by the scan signal. The method of claim 1, And the auxiliary pixel signal has a voltage greater than or equal to that of the main pixel signal. delete The method of claim 1, The data modulator, When the difference value from the comparator is large, the modulation pixel data corresponding to the auxiliary pixel signal having a relatively small voltage is generated. When the difference value is small, the modulation pixel data corresponding to the auxiliary pixel signal having a relatively large voltage is generated. To produce a liquid crystal display device. Storing pixel data of a previous frame in a frame memory; Comparing pixel data of the previous frame input from the frame memory with pixel data of the current frame currently input using a comparator and outputting a difference value; Generating modulated pixel data by modulating pixel data of the current frame according to the difference value; Converting the modulated pixel data into an auxiliary pixel signal in an analog form and converting the pixel data of the current frame into an analog main pixel signal and supplying the same to the data lines of a liquid crystal panel; And And supplying a scan signal to gate lines of the liquid crystal panel. The method of claim 6, Generating the modulated pixel data, Generate the modulated pixel data corresponding to an auxiliary pixel signal having a relatively small voltage when the difference is large; And generating the modulated pixel data corresponding to the auxiliary pixel signal having a relatively large voltage when the pixel data difference value is small. The method of claim 6, And the auxiliary pixel signal and the main pixel signal are sequentially supplied to the data lines. The method of claim 6, And the auxiliary pixel signal has a voltage equal to or greater than that of the main pixel signal.

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