KR100956345B1 - Thin film transistor array panel - Google Patents

Abstract

The thin film transistor array panel according to the present invention includes a plurality of gate lines, a plurality of data lines, a plurality of first thin film transistors connected to the gate lines and the data lines, a plurality of pixel electrodes connected to the thin film transistors, and the pixel electrodes. A display area including a plurality of storage electrode lines overlapping each other, a test pad positioned outside the display area, electrically connected to the gate line or the data line, and configured to inspect the gate line or the data line; And a peripheral region including an electrostatic discharge protection circuit disposed closer to the edge than the pad, wherein the electrostatic discharge protection circuit includes at least one second thin film transistor. In this way, even if the static electricity is excessively introduced into the thin film transistor array panel by the electrostatic discharge circuit, it is possible to prevent the static electricity from being transferred to the display area.

Static electricity, test pads, thin film transistors, discharge protection circuits

Description

Thin film transistor array panels

1 is a schematic layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

2 is a layout view of one pixel of a thin film transistor array panel according to an exemplary embodiment of the present invention.

3A and 3B are cross-sectional views of the thin film transistor array panel of FIG. 2 taken along lines IIIa-IIIa 'and IIIb-IIIb', respectively.

4A is an enlarged layout view of a portion of the electrostatic discharge protection circuit of FIG. 1 according to an embodiment of the present invention;

4B is a cross-sectional view taken along the line IVb-IVb ′ of FIG. 4A.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to liquid crystal displays, and more particularly, to thin film transistor array panels for liquid crystal displays.

A typical liquid crystal display (LCD) includes a liquid crystal layer having dielectric anisotropy interposed between two display panels. The desired image is obtained by applying an electric field to the liquid crystal layer and adjusting the intensity of the electric field to adjust the transmittance of light passing through the liquid crystal layer. Such liquid crystal displays are typical among portable flat panel displays (FPDs) that are easy to carry. Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

In the display panel on which the thin film transistor is formed, a plurality of gate lines and data lines are formed in row and column directions, respectively, and pixel electrodes connected to the gate lines and data lines are formed through the thin film transistors. The thin film transistor controls the data signal transmitted through the data line according to the gate signal transmitted through the gate line and transmits the data signal to the pixel electrode. The gate signal is generated by combining a plurality of gate driving integrated circuits (ICs) supplied with the gate-on voltage Von and the gate-off voltage Voff generated by the driving voltage generator according to control from the signal controller. The data signal is obtained by converting the gradation signal from the signal controller into a plurality of data driving ICs into analog voltages. The signal control unit and the driving voltage generator are usually provided on a printed circuit board (PCB) located outside the display panel, and the driving IC is a flexible printed circuit (FPC) board located between the PCB and the display panel. It is mounted on the top. Two PCBs are usually placed in this case, one above and one left of the display panel. The left one is called a gate PCB and the top one is called a data PCB. A gate driver IC is positioned between the gate PCB and the display panel, and a data driver IC is positioned between the data PCB and the display panel, and receives signals from the corresponding PCB.

In the meantime, a visual inspection (VI) inspection is required to inspect the operation of the fabricated liquid crystal display. For this purpose, in the above-described COG structure, a separate inspection line connected to the gate line and the data line is respectively driven on the thin film transistor array panel. An inspection pad for providing inspection signals to these inspection lines is provided between the gate driving IC and the data driving IC, respectively.

However, separate test lines and test pads connected to the gate lines and the data lines of the thin film transistor array panel for the liquid crystal display device are often positioned at edges outside the display area including a set of pixels of the thin film transistor array panel.

As a result, since the inspection line and the inspection pad of the thin film transistor array panel having such a structure are located at edges outside the display area of the display panel, the static electricity is easily introduced into the pixels of the display panel by being exposed to static electricity generated during the manufacturing process. In particular, when the guard ring is installed, the static electricity introduced through the guard ring flows through the test line through the gate line and the data line, and is likely to destroy the thin film transistor.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array panel including an electrostatic discharge protection circuit capable of protecting elements of the display panel from electrostatic discharge.

In order to achieve the above object, the present invention provides the following thin film transistor array panel.

More specifically, a plurality of gate lines and a plurality of data lines, a plurality of first thin film transistors connected to the gate lines and the data lines, a plurality of pixel electrodes connected to the thin film transistors, and overlapping with the pixel electrodes. A display area having a plurality of storage electrode lines, positioned outside the display area, electrically connected to the gate line or the data line, a test pad for inspecting the gate line or the data line; A peripheral area including an electrostatic discharge protection circuit disposed in close proximity, wherein the electrostatic discharge protection circuit provides a thin film transistor array panel including at least one second thin film transistor.

The gate of the second thin film transistor is connected to a first pad receiving a gate-on voltage from the outside, a source is connected to a second pad receiving a common voltage from the outside, and a drain is connected to the storage electrode line. It is preferable.

In addition, it is preferable to further include a guard ring formed along the edge of the peripheral area.

In addition, the electrostatic discharge protection circuit is preferably located near one corner of the display panel.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Next, a thin film transistor substrate according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a thin film transistor array panel according to an exemplary embodiment of the present invention includes a plurality of gate lines G1 -Gn extending in a horizontal direction and a plurality of data lines D1 -Dm extending in a vertical direction. A plurality of pixel regions defined by intersections are divided into a display region A for displaying an image and a peripheral region B except for the display region A. FIG.

Each pixel area of the display area A has a gate line and a data line G1 -Gn through the thin film transistor Q and the thin film transistor Q connected to the gate lines and the data lines G1 -Gn and D1 -Dm. And a pixel electrode (not shown) electrically connected to D1-Dm. In addition, sustain electrode lines S1-S1 are formed between neighboring gate lines G1 -Gn, which overlap the pixel electrodes to form a storage capacitor, and gate lines G1 of neighboring pixel rows. It can be omitted when the storage capacitor is formed by overlapping Gn) with the pixel electrode.

In the peripheral area B, when the gate line and the data lines G1 -Gn and D1 -Dm are disconnected / disconnected, the data line for bypassing the signal transmitted through them to the outside of the display area A to transmit the signal. Repair lines 61 and 62 are formed to intersect the gate lines G1 -Gn and D1 -Dm.

In addition, a gate line test pad 126p is formed on a portion of the left edge of the peripheral area B to inspect the disconnection / short circuit of the gate lines G1 -Gn during the thin film transistor array panel manufacturing process. The data line test pad 176p is provided for inspecting disconnection / short of the data lines D1-Dm. In addition, inspection lines 126 and 176 for inspecting the gate lines G1 -Gn and the data lines D1 -Dm are connected to these inspection pads, respectively.

The inspection line 126 for inspecting the gate lines G1 -Gn mainly extends in the vertical direction, one side of which extends upward, and an inspection pad 126p is connected to an end thereof. Gate lines G1 -Gn are connected to the inspection line 126, and when the number of inspection lines 126 is two or more, the connection of the inspection line 126 and the gate lines G1 -Gn is alternately performed. For example, there are two inspection lines 126 in FIG. 1, one inspection line 126 has odd gate lines G1, G3,..., And the other inspection line 126 has an even gate line ( G2, G4, ...) are connected.                     

On the other hand, the inspection line 176 for inspecting the data lines D1-Dm mainly extends in the horizontal direction, one side thereof extends upward, and an inspection pad 176p is connected to the end thereof. The data lines D1-Dm are connected to the test line 176, and when the number of the test lines 176 is two or more, the connection of the test line 176 and the data lines D1-Dm is alternately performed. For example, in FIG. 1, there are two inspection lines 176, the upper inspection line 176 has odd-numbered data lines D1, D3, ..., and the lower inspection line 176 has an even-numbered data line ( D2, D4, ...) are connected.

The peripheral area B is further provided with a common voltage line CL connected to the sustain electrode lines S1 -Sl to transfer a common voltage, and the common voltage line CL is connected to the electrostatic discharge protection circuit 40.

The electrostatic discharge protection circuit 40 includes a plurality of transistors Q1-Q3 and is closer to the edge of the display panel 100 than the edge of the peripheral area B, more specifically, the data line test pad 176p, The display panel 100 is positioned near one corner of the display panel 100. Gates of the transistors Q1-Q3 are commonly connected to the gate voltage supply line SLg, and a source is connected to the common voltage supply line SLs. Pads p1 and p2 are provided at one end of the gate voltage supply line SLg and the common voltage supply line SLs, respectively, to receive the gate-on voltage Von and the common voltage Vcom.

A guard ring 50 is formed along the edge of the display panel 100. The guard ring prevents static electricity from flowing into the display panel 100.

The inspection lines 126 and 176 and the common voltage line CL are made of the same layer as the gate lines or the data lines G1 -Gn and D1 -Dm.

A thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 to 3B.

2 is a layout view of one pixel of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 3A and 3B are cut along the IIIa-IIIa 'line and the IIIb-IIIb' line of FIG. 2, respectively. It is sectional drawing.

2 to 3B, one pixel of the TFT panel according to the exemplary embodiment of the present invention may include a plurality of gate lines 121 and a plurality of storage electrode lines on the insulating substrate 110. electrode lines 131 are formed.

The gate line 121 and the storage electrode line 131 mainly extend in the horizontal direction and are separated from each other. The gate line 121 transmits a gate signal, and a portion of each gate line 121 protrudes upward to form a plurality of gate electrodes 124. The storage electrode line 131 receives a predetermined voltage such as a common voltage, and includes an expansion 137 that extends up and down in width.

The gate line 121 and the storage electrode line 131 include a conductive film formed of a silver-based metal such as silver (Ag) or a silver alloy having a low resistivity, or an aluminum-based metal such as aluminum (Al) or an aluminum alloy. In addition to conductive films, chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo) and alloys thereof with good physical, chemical and electrical contact properties with other materials, in particular ITO or IZO [see: Molybdenum-Tungsten (MoW) alloy] may have a multilayer film structure including another conductive film. An example of the combination of the lower layer and the upper layer is chromium / aluminum-neodymium (Nd) alloy.

Sides of the gate line 121 and the storage electrode line 131 are inclined, and the inclination angle is in a range of about 30-80 ° with respect to the surface of the substrate 110.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121 and the storage electrode line 131.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction, from which a plurality of extensions 154 extend toward the gate electrode 124.

A plurality of ohmic contacts 163 and 165 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the linear semiconductor 151. The ohmic contact 163 is connected to a linear ohmic contact (not shown) below the linear semiconductor 151, and is paired with the ohmic contact 165 and positioned above the protrusion 154 of the linear semiconductor 151. do.

Side surfaces of the linear semiconductor 151 and the ohmic contacts 163 and 165 are also inclined, and the inclination angle is 30-80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 163 and 165 and the gate insulating layer 140, respectively.

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 124. The drain electrode 175 extends toward the extension portion 137 of the storage electrode line 131 and has a protrusion 177 overlapping the extension portion 137. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor 151, and the channel of the thin film transistor is a source. A protrusion 154 is formed between the electrode 173 and the drain electrode 175. The data line 171 and the drain electrode 175 may also include a conductive film made of a silver metal or an aluminum metal. In addition to the conductive film, chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum (Mo) may be used. ) And other conductive films made of alloys thereof. Sides of the data line 171 and the drain electrode 175 are also inclined, and the inclination angle is in the range of about 30-80 ° with respect to the horizontal plane.

The ohmic contacts 163 and 165 exist only between the semiconductor 151 at the bottom thereof, the data line 171 and the drain electrode 175 thereon, and serve to lower the contact resistance. The linear semiconductor 151 has an exposed portion between the source electrode 173 and the drain electrode 175 and is not covered by the data line 171 and the drain electrode 175, and in most places, the linear semiconductor 151 is provided. Is smaller than the width of the data line 171. The semiconductor 151 may increase in width at a portion where the semiconductor 151 meets the gate line 121 to enhance insulation between the gate line 121 and the data line 171.

On the data line 171, the drain electrode 175, and the exposed portion of the semiconductor 151, an organic material having excellent planarization characteristics and photosensitivity, and plasma enhanced chemical vapor deposition (PECVD), is formed. A passivation layer 180 made of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or silicon nitride, which is an inorganic material, is formed.

In the passivation layer 180, a plurality of contact holes 182 and 187 exposing the end portion 179 and the drain electrode 175 of the data line 171 are formed.

A plurality of pixel electrodes 190 and a plurality of contact assistants 82 made of ITO or IZO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact hole 187 to receive a data voltage from the drain electrode 175.

The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules between the two electrodes by generating an electric field together with a common electrode of another display panel.

In addition, the pixel electrode 190 and the common electrode form a capacitor (hereinafter, referred to as a liquid crystal capacitor) to maintain an applied voltage even after the thin film transistor is turned off, and in parallel with the liquid crystal capacitor to enhance the voltage retention capability. The other capacitors are connected to one another and are called storage capacitors. The storage capacitor is made by superimposing the pixel electrode 190 and the neighboring gate line 121 (which is referred to as a prior gate line).

The pixel electrode 190 overlaps with the neighboring data line 171 to increase the aperture ratio, but may not overlap.

The contact auxiliary members 82 are connected to the end portions 179 of the data lines through the contact holes 182, respectively. The contact assisting member 82 is not essential to serve to protect adhesiveness between the end portion 129 of the data line 171 and an external device and to protect them, and application thereof is optional.

Finally, an alignment layer 11 is formed on the pixel electrode 190, the contact auxiliary member 82, and the passivation layer 180. The alignment layer 11 is in contact with the alignment layer 21 of the upper panel 200 where the spacer (not shown) is located.

Next, the electrostatic discharge protection circuit 40 (refer to FIG. 1) formed in the peripheral region B will be described in detail with reference to FIGS. 4A and 4B and FIGS. 1 to 3B.

FIG. 4A is an enlarged layout view of a portion of the electrostatic discharge protection circuit of FIG. 1, according to an exemplary embodiment. FIG. 4B is a cross-sectional view taken along the line IVb-IVb ′ of FIG. 4A.

4A and 4B, an electrostatic discharge protection circuit 40 according to an embodiment of the present invention shown in FIG. 1 includes a gate voltage supply line 125, an island type semiconductor 156, and a common voltage supply line 172d. 172s) and three thin film transistors.

The gate layer 121 is made of the same layer as the gate line 121 of the gate voltage supply line 125, and one end thereof is extended to form a gate electrode common to the three thin film transistors. The other end is a pad p1 as shown in FIG. 1 to receive a gate-on voltage.

The island-like semiconductor 156 is formed of the same layer as the linear semiconductor 151 of FIGS. 2 and 3A and is positioned on an extension of the gate voltage supply line 125. Three island-like ohmic contact members 166 are provided on the island-like semiconductor 156 facing each other, and are formed of the same layer as the ohmic contacts 163 and 165 of FIG. 3A.

The common voltage supply lines 172d and 172s are formed of the same layer as the data line 171 of FIGS. 2 and 3A and at least partially have three branches positioned on the ohmic contact 166. The upper common voltage supply line 172s corresponds to the symbol SLs of FIG. 1 and extends upward to become a pad p2 to receive a common voltage from the outside. The lower common voltage supply line 172d corresponds to the reference CL of FIG. 1 and is connected to the storage electrode line 131 of FIG. 2.

The electrostatic discharge protection circuit 40 made of such a thin film transistor is a semiconductor (156) that acts primarily as a non-conductor during the manufacturing process as well as during the inspection is blocked primarily, and when a very strong static electricity flows into the semiconductor ( Since 156 is destroyed, static electricity cannot enter the thin film transistor of the display area.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, an electrostatic discharge protection circuit may be added to the corner of the peripheral area of the thin film transistor array panel to prevent the static electricity from being transferred to the display area even when excessive amount of static electricity flows into the thin film transistor array panel.

Accordingly, a high quality thin film transistor array panel can be provided by minimizing defects caused by static electricity.

Claims (4)

A plurality of gate lines, a plurality of data lines, a plurality of first thin film transistors connected to the gate lines and the data lines, a plurality of pixel electrodes connected to the thin film transistors, and a plurality of sustain electrode lines overlapping the pixel electrodes. Display area, A test pad positioned outside the display area and electrically connected to the gate line or the data line, the test pad for inspecting the gate line or the data line, and an electrostatic discharge protection circuit disposed closer to an edge than the test pad; Surrounding area Including, The electrostatic discharge protection circuit includes at least one second thin film transistor, The gate of the second thin film transistor is connected to a first pad receiving a gate-on voltage from the outside, a source is connected to a second pad receiving a common voltage from the outside, and a drain is connected to the storage electrode line. Thin film transistor display panel. delete In claim 1, The thin film transistor array panel of claim 1, further comprising a guard ring formed along an edge of the peripheral area. In claim 1, The electrostatic discharge protection circuit is a thin film transistor array panel positioned near one corner of the display panel.

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